CX6140(456PBGA) [IDT]

Telecom IC,;
CX6140(456PBGA)
型号: CX6140(456PBGA)
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

Telecom IC,

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Product Brief  
CX6100  
Structured ASIC with PCI Express  
Product Description  
The CX6100 product family combines a built-in, silicon-proven, industry standard PHY for PCI  
Express with the well-proven X-Cell™ architecture, to provide industry leading performance  
using the UMC standard eight-metal 0.13-µm deep submicron process. Only two to four metal  
layers are used for customization, allowing prototypes to be manufactured, assembled, tested,  
and shipped in just 4 to 5 weeks.  
The built-in, silicon-proven PCI Express PHY, in combination with the ChipX synthesizable  
processors and PCI Express endpoint, root port, or bridge controllers, form a complete PCI  
Express subsystem capable of achieving PCI-SIG compliance. You can also use your own PCI  
Express controller where desired. The PCI Express subsystem on the CX6100 family of products  
removes complexity and the risk of IP selection and IP interoperability testing.  
The CX6100 product family builds on four generations of ChipX Structured ASIC products (see  
Table 1). The core technology combines our accumulated design expertise with a focus on  
Networking and Industrial PCI Express interface needs. The CX6100 PCI Express Structured  
ASIC platform delivers an ideal solution that is high performance and appropriate for low to  
high-volume production.  
Table 1 CX6100 SerDes/PCI Express Structured ASIC Platforms  
Memory  
(Kbits)  
(9-Kb  
Usable  
Gates  
(KGates)  
Cache  
Memory  
Blocks  
Maximum  
Configurable  
I/O2  
Part  
PCI  
Lanes  
PLL  
Packages  
Number1  
Banks)  
CX6140  
CX6142  
CX6143  
637  
743  
850  
1250  
(138)  
2 x 16 KB  
2 x 16 KB  
2 x 16 KB  
7
240  
248  
252  
4
4
4
256 LBGA,  
388 PBGA,  
456 PBGA  
1125  
(125)  
7
7
256 LBGA,  
388 PBGA,  
456 PBGA  
1000  
(111)  
256 LBGA,  
388 PBGA,  
456 PBGA  
1. ChipX will consider a private product for your company.  
2. Configurable I/O excludes PCI Express PHY pins and Power/Gnd connections  
Applications  
The CX6100 is optimized with IP content and size ranges to support specific system  
applications.  
June 4, 2007  
0289-6k-070-A  
1 of 2  
CX6100  
ChipX Product Brief  
Structured ASIC with PCI Express  
Industrial Markets  
Communications Markets  
Industrial  
Test and  
Advanced TCA  
platforms  
Routers  
computing/control  
Single board computer  
Medical equipment  
Audio/Video console  
instrumentation  
Factory automation  
Office automation  
Broadcast systems  
Multi-service switches  
Head-end equipment  
Wireless base stations  
Design Flow  
ChipX spends considerable development effort to ensure that taping out a design to a CX6100  
Structured ASIC is simple, painless, and low risk. ChipX provides libraries for Magma, Synopsys,  
and Synplicity ASIC synthesis tools.  
RTL, ASIC Netlist, or FPGA Netlist Handoff  
Many customers prefer to hand off their RTL designs early and let ChipX perform the entire  
timing closure loop, including synthesis and final simulations. Our integrated development tools  
allow faster overall design cycle with an RTL handoff. ChipX can also rapidly and reliably convert  
obsolete design netlists into prototypes.  
Key Features and Benefits  
PCI Express v1.1 PHY offers 2.5-Gbps operation, in four lanes, and 1 x 4, 4 x 1, 1 x 8 or 8 x  
1 modes  
Complete PCI Express subsystem from one vendor lowers implementation risk  
250 MHz maximum global operating frequency, 1 GHz local  
True ASIC gate count of 637K to 850K usable gates, using the ChipX 4th generation, fine  
grain Structured ASIC fabric  
Efficient gate and memory structures simplify timing closure  
High speed embedded SRAM of 1000 Kb to 1250 Kb  
Highly configurable RAM blocks of 9 Kb each for excellent memory use efficiency  
Single port, dual port, or FIFO RAM configurations  
Core operating voltage of 1.2 V  
I/O voltages of 1.5 V, 1.8 V, 2.5 V and 3.3 V; output drive strengths of up 16 mA  
Flexible I/O pads that can be power, ground, input, output or bidirectional  
I/O support: LVTTL, LVCMOS, HSTL, SSTL(18/2/3), LVDS (up to 640 Mbps), PCI, PCI-X,  
XOSC; DDR, DDRII including PHY and Controller  
Commercial and Industrial grade temperature libraries  
Up to seven configurable PLLs with Spread Spectrum tracking, output range of 10 MHz to  
1 GHz  
Multiple phase shift DLLs up to 400 MHz  
Packages from 256 LBGA to 456 PBGA  
Fast time to prototypes and production; Standard Cell ASIC migration available  
For more information, please visit our website: www.chipx.com  
© 2007 ChipX, Incorporated  
Disclaimer This document is provided for general information only. ChipX makes every effort to improve products for its customers  
on an ongoing basis. Specifications are subject to change without notice. Trademarks are property of their owners. Errors and  
omissions excluded (E&OE).  
ChipX, Inc.  
www.chipx.com Tel: 408-988-2445 Toll Free: 1-800-95-CHIPX Fax: 408-988-2449  
Email: moreinfo@chipx.com 2323 Owen Street Santa Clara, CA USA 95054  
2 of 2  
0289-6k-070-A  
June 4, 2007  

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