ERJ-2RKF1003X [IDT]
6 Bit Digital Step Attenuator;
| 型号： | ERJ-2RKF1003X |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 6 Bit Digital Step Attenuator |
| 文件： | 总22页 (文件大小：1552K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
GENERAL DESCRIPTION
FEATURES
Serial & 6 bit Parallel Interface
This document describes the specification for the IDT
F1912 Digital Step Attenuator. The F1912 is part of a
family of Glitch-FreeTM DSAs optimized for the
demanding requirements of Base Station (BTS) radio
cards and numerous other non-BTS applications.
These devices are offered in a compact 4mm x 4mm
20 pin QFN package with 50Ω impedances for ease of
integration.
31.5 dB Control Range
0.5 dB step
Glitch-FreeTM, low transient overshoot
3.0 V to 5.25 V supply
1.8 V or 3.3 V control logic
Attenuation Error < 0.22 dB @ 2 GHz
Low Insertion Loss < 1.6 dB @ 2 GHz
Ultra linear IIP3 >+59.5 dBm
IIP2 = +110 dBm typical
COMPETITIVE ADVANTAGE
Stable Integral Non-Linearity over temperature
Low Current Consumption 550 µA typical
-40 °C to +105 °C operating temperature
4mm x 4mm Thin QFN 20 pin package
Digital step attenuators are used in Receivers and
Transmitters to provide gain control. The F1912 is a
6-bit step attenuator optimized for these demanding
applications. The silicon design has very low insertion
loss and low distortion (> +60 dBm IIP3.) The device
has pinpoint accuracy. Most importantly, the F1912
includes IDT’s Glitch-FreeTM technology which results in
low overshoot & ringing during MSB transitions.
FUNCTIONAL BLOCK DIAGRAM
Glitch-FreeTM Technology so PA or ADC will not
TM
Glitch-FreeTM
be damaged during when transitions.
RF1
RF2
Extremely accurate with low distortion.
Lowest insertion loss for best SNR
APPLICATIONS
Bias
Decoder
SPI
Base Station 2G, 3G, 4G, TDD radio cards
Repeaters and E911 systems
Digital Pre-Distortion
Point to Point Infrastructure
Public Safety Infrastructure
WIMAX Receivers and Transmitters
Military Systems, JTRS radios
RFID handheld and portable readers
Cable Infrastructure
VMODE
LE
D[5:0]
CLK DATA
Part# Details
Freq Range
IL
Resolution /
Range (dB)
Part#
Control
Pinout
(MHz)
(dB)
PE43702
PE43701
Parallel &
Serial
F1950 150 - 4000 0.25 / 31.75
1.3
ORDERING INFORMATION
F1951 100 - 4000
0.50 / 31.5 Serial Only 1.2
0.50 / 15.5 Serial Only 0.9
Parallel &
HMC305
HMC305
Omit IDT
prefix
Tape &
Reel
0.8 mm height
package
F1952 100 – 4000
PE4302
DAT-31R5
F1953 400 – 4000
0.50 / 31.5
0.25 / 31.75
0.50 / 31.5
1.3
1.4
1.4
Serial
Parallel &
Serial
PE43705,
RFSA3715
F1956
F1912
1 - 4000
IDTF1912NCGI8
Parallel &
Serial
PE4312
PE4302
1 – 4000
Green
RF product Line
Glitch-FreeTM, Digital Step Attenuator
1
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Min
Max
Units
VDD to GND
VDD
-0.3
+5.5
V
Min (VDD-0.3,
3.6)
DATA, LE, CLK, D[5:0]
VLogic
VRF
-0.3
-0.3
V
RF1, RF2
+0.3
V
Maximum Input Power applied
to RF1 or RF2 (>100 MHz)
PRF
+34
dBm
Operating Case Temperature
Maximum Junction Temperature
Junction Temperature
+105
+140
140
°C
°C
°C
W
TJmax
Tjmax
Continuous Power Dissipation
Storage Temperature Range
Lead Temperature (soldering, 10s)
1.5
Tst
-65
150
°C
°C
260
Electrostatic Discharge – HBM
(JEDEC/ESDA JS-001-2012)
2000
(Class 2)
VESDHBM
VESDCDM
Volts
Volts
500
(Class C2)
ESD Voltage – CDM (Per JESD22-C101F)
Stresses above those listed above may cause permanent damage to the device. Functional operation of the device at
these or any other conditions above those indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
This product features proprietary protection circuitry. However, it may be damaged if subjected to high energy ESD.
Please use proper ESD precautions when handling to avoid damage or loss of performance.
PACKAGE THERMAL AND MOISTURE CHARACTERISTICS
θJA (Junction – Ambient)
50 °C/W
3 °C/W
MSL1
θJC (Junction – Case) [The Case is defined as the exposed paddle]
Moisture Sensitivity Rating (Per J-STD-020)
Glitch-FreeTM, Digital Step Attenuator
2
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
F1912 RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage(s)
Symbol
VDD
Conditions
Min
3
Typ
Max
5.25
4000
105
Units
V
Frequency Range
FRF
1
MHz
°C
Operating Temperature Range
TCASE
Exposed Paddle
RF1 or RF2
-40
See
Figure 1
RF CW Input Power
PCW
dBm
Source Impedance
Load Impedance
ZSource
ZLoad
Single Ended
Single Ended
50
50
Ω
Ω
32
28
24
20
16
12
8
4
0
0.01
0.10
1.00
10.00
100.00
1000.00
Frequency(MHz)
Figure 1 Maximum Continuous Operating RF input power versus Input Frequency
Glitch-FreeTM, Digital Step Attenuator
3
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
F1912 SPECIFICATION
Specifications apply at VDD = +3.3 V, TCASE = +25 °C, FRF = 2000 MHz, Pin = 0 dBm, Serial Mode (Vmode > VIH),
Zsource = ZLoad = 50 Ω unless otherwise noted. EvKit losses are de-embedded.
Parameter
Symbol
Conditions
All Control Pins
Min
Typ
Max Units
Logic Input High
VIH
VDD > 3.9 V
1.17
1.17
3.6
VDD-0.3
0.63
+35
V
V
3.0 ≤ VDD ≤ 3.9 V
All Control Pins
All Control Pins
VDD = 3.3 V
Logic Input Low
Logic Current
VIL
V
IIH, IIL
-35
μA
550
620
18
8301
Supply Current
IDD
μA
VDD = 5.0 V
900
RF1 Return Loss
RF2 Return Loss
Attenuation Step
S11
S22
dB
dB
dB
18
LSB
Least Significant Bit
0.5
Insertion Loss
(Minimum Attenuation)
Insertion Loss
(Maximum Attenuation)
AMIN
AMAX
D[5:0]=[000000] (IL State)
1.4
2.0
dB
dB
D[5:0]=[111111]=31.5 dB
322
33.0
0.10
Step Error
DNL
INL
dB
dB
Absolute Error
D[5:0]=[100111]= 19.5 dB
At 2 GHz
-0.7
+0.5
27
55
Insertion Phase Delta
ΦΔ
degrees
At 4 GHz
PIN = +10 dBm/tone,
Tone Spacing = 50 MHz
Attn = 0.0 dB, RFin = RF1
Attn = 0.0 dB, RFin = RF2
Attn =15.5 dB, RFin = RF1
Attn =15.5 dB, RFin = RF2
60
56
56
57
64.0
60.5
61.0
61.5
IIP3
dBm
Input IP3
Attn = 0.00 dB, RFin = RF1
PIN = +22 dBm per tone
1 MHz Tone Separation
FRF = 0.7 GHz
FRF = 1.8 GHz
FRF = 2.2 GHz
FRF = 2.6 GHz
60
58
58
57
62.5
61.5
61.0
60.5
PIN = +12dBm/tone, VDD=5.0V
F1=945 MHz, F2= 949 MHz
F1+F2 = 1894 MHz
RFIN= RF1
D[5:0] = [000000] = 0 dB
Input IP2
IIP2
P0.1
110
31
dBm
dBm
0.1dB Compression3
Note 1: Items in min/max columns in bold italics are Guaranteed by Test.
Note 2: Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization.
Note 3: The input 0.1dB compression point is a linearity figure of merit. Refer to Absolute Maximum Ratings section for the maximum RF input
power.
Note 4: Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2 MHz.
Note 5: Speeds are measured after SPI programming is completed (data latched with LE = HIGH).
Glitch-FreeTM, Digital Step Attenuator
4
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
F1912 SPECIFICATION (CONTINUED)
Specifications apply at VDD = +3.3 V, TCASE = +25 °C, FRF = 2000 MHz, Pin = 0 dBm, Serial Mode (Vmode > VIH),
Zsource = ZLoad = 50 Ω unless otherwise noted. EvKit losses are de-embedded.
Parameter
Symbol
Conditions
Min
Typ
Max Units
Start LE rising edge > VIH
End ±0.10 dB Pout settling for
15.5 dB to 16.0 dB transition
MSB Step Time
TLSB
500
ns
Maximum spurious level on
any RF port4
Maximum Switching
Frequency
SpurMAX
SWFREQ
-140
25
dBm
kHz
Max to Min Attenuation to
settle to within 0.5 dB of final
value
Min to Max Attenuation to
settle to within 0.5 dB of final
value
0.9
DSA Settling time
SET
s
1.8
6
Control Interface
Serial Clock Speed
SPIBIT
SPICLK
bit
25
MHz
Note 1: Items in min/max columns in bold italics are Guaranteed by Test.
Note 2: Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization.
Note 3: The input 0.1dB compression point is a linearity figure of merit. Refer to Absolute Maximum Ratings section for the maximum RF input
power.
Note 4: Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2 MHz.
Note 5: Speeds are measured after SPI programming is completed (data latched with LE = HIGH).
Glitch-FreeTM, Digital Step Attenuator
5
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
PROGRAMMING OPTIONS
F1912 can be programmed using either the parallel or serial interface which is selectable via VMODE (pin 13).
Serial mode is selected by floating VMODE or pulling it to a voltage logic high (greater than VIH) and parallel
mode is selected by setting VMODE to logic low (less than VIL).
SERIAL CONTROL MODE
F1912 Serial mode is selected by floating VMODE (pin 13) or pulling it to a voltage > VIH. The serial interface
is a 6 bit shift register to shift in the data MSB (D5) first. When serial programming is used, all the parallel
control input pins (1, 15, 16, 17, 19, 20) must be grounded.
Table 1 - 6 Bit SPI Word Sequence
D5
D4
D3
D2
D1
D0
Attenuation 16 dB Control Bit
Attenuator 8 dB Control Bit
Attenuator 4 dB Control Bit
Attenuator 2 dB Control Bit
Attenuator 1 dB Control Bit
Attenuator 0.5 dB Control Bit
Table 2 - Truth Table for Serial Control Word
D5
(MSB)
D0
(LSB)
Attenuation
D4
D3
D2
D1
(dB)
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0.5
1
2
4
8
16
31.5
Serial Mode REGISTER TIMING DIAGRAM: (Note the Timing Spec Intervals in Blue)
With serial control, the F1912 can be programmed via the serial port on the rising edge of Latch Enable (LE)
which loads the last 6 DATA line bits [formatted MSB (D5) first] resident in the SHIFT register followed by the
next 5 bits.
Glitch-FreeTM, Digital Step Attenuator
6
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
Figure 2 - Serial Register Timing Diagram
Note - When Latch enable is high, the shift register is disabled and DATA is NOT continuously clocked into
the shift register which minimizes noise. It is recommended that Latch enable be left high when the device is
not being programmed.
Table 3 - Serial Mode Timing Table
Interval
Symbol
Min
Spec
Max
Spec
Description
Units
Parallel to Serial Setup Time - From rising edge
of VMODE to rising edge of CLK for D5
tmc
tds
100
10
ns
ns
Clock high pulse width
LE Setup Time - From the rising edge of CLK
pulse for D0 to LE rising edge minus half the
clock period.
tcls
10
ns
tlew
tdsc
LE pulse width
30
10
ns
ns
Data Setup Time - From the starting edge of
Data bit to rising edge of CLK
Data Hold Time - From rising edge of CLK to
falling edge of the Data bit.
Tdht
10
ns
Glitch-FreeTM, Digital Step Attenuator
7
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
Serial Mode Default Startup Condition:
When the device is first powered up it will default to the Maximum Attenuation of 31.5 dB independent of the
VMODE and parallel pin [D5:D0] conditions.
Table 4 - Default Control Word for the Serial Mode
D5
(MSB)
D0
(LSB)
Attenuation
(dB)
D4
D3
D2
D1
1
1
1
1
1
1
31.5
PARALLEL CONTROL MODE
For the F1912 the user has the option of running in one of two parallel modes. Direct Parallel Mode or
Latched Parallel Mode.
Direct Parallel Mode:
Direct Parallel Mode is selected when VMODE (pin 13) is less than VIL and LE (pin 5) is greater than VIH. In this
mode the device will immediately react to any voltage changes to the parallel control pins [pins 1, 15, 16, 17,
19, 20]. Use direct parallel mode for the fastest settling time.
Latched Parallel Mode:
Latched Parallel Mode is selected when VMODE is less than VIL and LE (pin 5) is toggled from less than VIL to
greater than VIH. To utilize Latched Parallel Mode:
Set LE < VIL
Adjust pins [pins 1, 15, 16, 17, 19, 20] to the desired attenuation setting. (Note the device will not
react to these pins while LE < VIL.)
Pull LE > VIH. The device will then transition to the attenuation settings reflected by pins D5 – D0.
Latched Parallel Mode implies a default state for when the device is first powered up with VMODE < VIL and
LE < VIL. In this case the default setting is MAXIMUM Attenuation.
Table 5 - Truth Table for the Parallel Control Word
Attenuation
D5
D4
D3
D2
D1
D0
(dB)
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0.5
1
2
4
8
16
31.5
Glitch-FreeTM, Digital Step Attenuator
8
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
Figure 3 - Latched Parallel Mode Timing Diagram
Table 6 - Latched Parallel Mode Timing
Interval
Symbol
Min
Max
Spec
Description
Units
Spec
100
10
10
10
tsps
tpdh
tpds
tle
Serial to Parallel Mode Setup Time
Parallel Data Hold Time
LE minimum pulse width
Parallel Data Setup Time
ns
ns
ns
ns
Glitch-FreeTM, Digital Step Attenuator
9
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
TYPICAL OPERATING CONDITIONS (TOC)
Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply.
VDD = +3.30 V
TCASE = +25 °C
FRF = 2 GHz
PIN = 0 dBm for single tone measurements
PIN = +10 dBm/tone for multi-tone measurements
Tone Spacing = 50 MHz
EVKit connector and board losses are de-embedded
Glitch-FreeTM, Digital Step Attenuator
10
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
TYPICAL OPERATING CONDITIONS (- 1 -)
Insertion Loss vs Frequency
Insertion Loss vs Attenuation State
0.0
-0.5
-1.0
-1.5
-2.0
0
-5
-10
-15
-20
-25
-30
-35
-40 C / +3.3 V
+25 C / +3.3 V
+105 C / +3.3 V
-40 C / +5.0 V
+25 C / +5.0 V
+105 C / +5.0 V
-40 C / +3.3 V
+25 C / +3.3 V
+105 C / +3.3 V
-40 C / +5.0 V
+25 C / +5.0 V
+105 C / +5.0 V
-2.5
-3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuator State (dB)
Frequency (GHz)
RF1 (Input) Return Loss vs Frequency [All States]
RF1 (Input) Return Loss vs Attenuation State
0
-5
0
0.5 GHz
2.5 GHz
1.0 GHz
3.0 GHz
1.5 GHz
3.5 GHz
2.0 GHz
4.0 GHz
-5
-10
-15
-20
-25
-30
-10
-15
-20
-25
-30
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
RF2 (Output) Return Loss vs Frequency [All States]
RF2 (Output) Return Loss vs Attenuation State
0
-5
0
0.5 GHz
2.5 GHz
1.0 GHz
3.0 GHz
1.5 GHz
3.5 GHz
2.0 GHz
4.0 GHz
-5
-10
-15
-20
-25
-30
-10
-15
-20
-25
-30
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Glitch-FreeTM, Digital Step Attenuator
11
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
TYPICAL OPERATING CONDITIONS (- 2 -)
Relative Insertion Phase vs Frequency
Relative Insertion Phase vs Attenuation
60
55
50
45
40
35
30
25
20
15
10
5
60
55
50
45
40
35
30
25
20
15
10
5
0.5 GHz
2.5 GHz
1.0 GHz
3.0 GHz
1.5 GHz
3.5 GHz
2.0 GHz
4.0 GHz
0
0
-5
-5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.0
4.0
4.5
4.5
4.5
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Worst Case Absolute Accuracy vs Frequency
Absolute Accuracy vs Attenuation
1.0
1.0
0.8
-40 C / Min
+25 C / Min
+105 C / Min
-40 C / Max
+25 C / Max
+105 C / Max
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
0.5 GHz
2.5 GHz
1.0 GHz
3.0 GHz
1.5 GHz
3.5 GHz
2.0 GHz
4.0 GHz
-0.8
-1.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Worst Case Step Accuracy vs Frequency
Step Accuracy vs Attenuation
0.5
0.5
0.4
-40 C / Min
+25 C / Min
+105 C / Min
-40 C / Max
+25 C / Max
+105 C / Max
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0.0
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
0.5 GHz
2.5 GHz
1.0 GHz
3.0 GHz
1.5 GHz
3.5 GHz
2.0 GHz
4.0 GHz
-0.4
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Glitch-FreeTM, Digital Step Attenuator
12
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
TYPICAL OPERATING CONDITIONS (- 3 -)
Compression at 0 dB and 2 GHz
Input IP3 - 0 dB, +22 dBm, 1 MHz Tone Delta, RF1
0.2
75
70
65
60
55
0.1
0.0
-0.1
50
-0.2
-0.3
-40 C
IIP3-LS
45
+25 C
+105 C
IIP3-HS
40
18
20
22
24
26
28
30
30
30
32
32
32
34
34
34
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Input Power (dBm)
Frequency (GHz)
Compression at 15.5 dB and 2 GHz
Input IP3 (Low Side) vs attenuation at 2GHz
0.2
80
75
70
65
60
55
50
0.1
0.0
-0.1
-40 C / Pin = 10 dBm/Tone
+25 C / Pin = 10 dBm/Tone
+105 C / Pin = 10 dBm/Tone
-40 C / Pin = 15 dBm/Tone
+25 C / Pin = 15 dBm/Tone
+105 C / Pin = 15 dBm/Tone
-0.2
-0.3
-40 C
+25 C
+105 C
45
40
18
20
22
24
26
28
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Input Power (dBm)
Compression at 31.5 dB and 2 GHz
Input IP3 (High Side) vs attenuation at 2GHz
0.2
80
75
70
65
60
55
50
0.1
0.0
-0.1
-40 C / Pin = 10 dBm/Tone
+25 C / Pin = 10 dBm/Tone
+105 C / Pin = 10 dBm/Tone
-40 C / Pin = 15 dBm/Tone
+25 C / Pin = 15 dBm/Tone
+105 C / Pin = 15 dBm/Tone
-0.2
-0.3
-40 C
+25 C
+105 C
45
40
18
20
22
24
26
28
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Input Power (dBm)
Glitch-FreeTM, Digital Step Attenuator
13
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
PACKAGE DRAWING
(4 mm x 4 mm 20-pin TQFN), NCG20
Glitch-FreeTM, Digital Step Attenuator
14
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
LAND PATTERN DIMENSION
Glitch-FreeTM, Digital Step Attenuator
15
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
PIN DIAGRAM
TOP View
(looking through the top of the package)
20
19
18
17
16
15
14
13
12
11
D5
*RF1
DATA
CLK
LE
1
2
3
4
5
D4
*RF2
Exposed Pad
VMODE
GND
GND
6
7
8
9
10
* Device is RF Bi-Directional
Glitch-FreeTM, Digital Step Attenuator
16
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
PIN DESCRIPTION
PIN
NAME
FUNCTION
1
D5
16 dB Attenuation Control Bit. Pull high for 16 dB ATTN.
Device RF input or output (bi-directional). Internally DC
blocked.
2
RF1
3
4
DATA
CLK
Serial interface Data Input.
Serial interface Clock Input.
Serial interface Latch Enable Input. Internal pullup (100K
ohm).
5
LE
6
7
8
9
VDD
NC
Power supply pin.
Internally unconnected.
Internally unconnected.
Internally unconnected.
NC
NC
Connect to Ground. This pin is internally connected to the
exposed paddle.
10
GND
Connect to Ground. This pin is internally connected to the
exposed paddle.
11
12
13
GND
GND
Connect to Ground. This pin is internally unconnected.
Pull high for serial control mode. Ground for parallel control
mode.
VMODE
Device RF input or output (bi-directional). Internally DC
blocked.
14
RF2
15
16
17
18
19
20
D4
D3
8 dB Attenuation Control Bit. Pull high for 8 dB ATTN.
4 dB Attenuation Control Bit. Pull high for 4 dB ATTN.
2 dB Attenuation Control Bit. Pull high for 2 dB ATTN.
Connect to Ground. This pin is internally unconnected.
1 dB Attenuation Control Bit. Pull high for 1 dB ATTN.
0.5 dB Attenuation Control Bit. Pull high for 0.5 dB ATTN.
D2
GND
D1
D0
Exposed Pad. Internally connected to GND. Solder this
exposed pad to a PCB pad that uses multiple ground vias to
provide heat transfer out of the device into the PCB ground
planes. These multiple via grounds are also required to achieve
the specified RF performance.
Exposed
Paddle
EP
Glitch-FreeTM, Digital Step Attenuator
17
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
EVKIT PICTURE
Glitch-FreeTM, Digital Step Attenuator
18
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
EVKIT / APPLICATIONS CIRCUIT
Glitch-FreeTM, Digital Step Attenuator
19
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
EVKIT BOM
1 MHz to 4000 MHz
Item #
Part Reference
QTY
DESCRIPTION
Mfr. Part #
Mfr.
100nF ±10%, 50V, X7R Ceramic Capacitor
(0402)
1
GRM155R71H104K
C1, C11
C2, C12
R12, C13, C14
R1-R7
2
2
3
7
3
4
1
1
2
1
1
MURATA
MURATA
PANASONIC
PANASONIC
PANASONIC
PANASONIC
PANASONIC
PANASONIC
3M
2
3
10nF ±5%, 50V, C0G Ceramic Capacitor (0402)
0Ω Resistors (0402)
GRM155R71H103J
ERJ-2GE0R00X
ERJ-2RKF1000X
ERJ-2RKF3001X
ERJ-2RKF1002X
ERJ-2RKF1003X
ERJ-2RKF2673X
961102-6404-AR
961104-6404-AR
961108-6404-AR
4
100Ω ±1%, 1/10W, Resistor (0402)
3kΩ ±1%, 1/10W, Resistor (0402)
10kΩ ±1%, 1/10W, Resistor (0402)
100KΩ ±1%, 1/10W, Resistor (0402)
267KΩ ±1%, 1/10W, Resistor (0402)
CONN HEADER VERT SGL 2 X 1 POS GOLD
CONN HEADER VERT SGL 4 X 1 POS GOLD
CONN HEADER VERT SGL 8 X 1 POS GOLD
5
R9, R10, R11
R8, R15, R16, R17
R13
6
7
8
R14
9
J5, J7
10
11
J8
3M
J6
3M
Edge Launch SMA (0.250 inch pitch ground,
round)
12
J2, J3, J4
U1
3
1
1
1
142-0711-821
KAT1108E
Emerson Johnson
13
14
15
SWITCH 8 POSITION DIP SWITCH
DSA
E-Switch
IDT
U2
F1912Z
Printed Circuit Board (Rev 01)
F1953S Evkit Rev 01
IDT
16
Bill Of Material (Rev 01)
TOP MARKINGS
Part Number
IDTF19
12NCGI
Z515G
Assembler
Code
ASM
Test
Step
Date Code [YWW]
(Week 5 of 2015)
Glitch-FreeTM, Digital Step Attenuator
20
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
APPLICATIONS INFORMATION
F1912 Digital Pin Voltage & Resistance Values (pins not connected)
The following table lists the resistance between various pins and ground when no DC power is applied. When
the device is powered up with +5 Volts DC these same pins to should have the measured voltage to ground.
DC voltage
(volts)
Resistance
Pin
Name
(ohms)
100 kΩ pullup resistor
to internally regulated
2.5 V
13
VMODE
2.5V
100 kΩ pullup resistor
to internally regulated
2.5 V
3, 4, 5
DATA, CLK, LE
2.5V
Glitch-FreeTM, Digital Step Attenuator
21
Rev 1, May 2017
IDTF1912NCGI
Datasheet
6 Bit Digital Step Attenuator
1 MHz to 4000 MHz
Revision History
Revision
Revision Date
Description of Change
1
2017-May-26
2015-June-06
Corrected pin label on Page 16.
Initial release of the datasheet
O
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
www.IDT.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,
without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are d etermined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of a ny kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be
reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the
property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of
Integrated Device Technology, Inc. All rights reserved.
Glitch-FreeTM, Digital Step Attenuator
22
Rev 1, May 2017
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