ICS1562BM-201T [IDT]
Video Clock Generator, 260MHz, CMOS, PDSO16, 0.150 INCH, SKINNY, SOIC-16;
| 型号： | ICS1562BM-201T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Video Clock Generator, 260MHz, CMOS, PDSO16, 0.150 INCH, SKINNY, SOIC-16 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总20页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS1562B
Integrated
Circuit
Systems, Inc.
User Programmable Differential Output Graphics Clock Generator
Description
Features
The ICS1562B is a very high performance monolithic phase-
locked loop (PLL) frequency synthesizer. Utilizing ICS’s ad-
vanced CMOS mixed-mode technology, the ICS1562B
provides a low cost solution for high-end video clock genera-
tion.
•
Two programming options:
ICS1562B-001 (Parallel Programming)
ICS1562B-201 (Serial Programming)
Supports high-resolution graphics - CLK output to
260 MHz, with 400 MHz options available
•
•
•
Eliminates need for multiple ECL output crystal oscillators
Fully programmable synthesizer capability - not just a
clock multiplier
The ICS1562B hasdifferentialvideoclockoutputs (CLK+and
CLK-) that are compatible with industry standard video DAC.
Another clock output, LOAD, is provided whose frequency is
derived from the main clock by a programmable divider. An
additional clock output is available, LD/N2, which is derived
from the LOAD frequency and whose modulus may also be
programmed.
•
•
Circuitry included for reset of Brooktree RAMDAC pipe-
line delay
VRAM shift clock generation capability
(-201 option only)
•
•
•
External feedback loop capability (-201 option only)
Operating frequencies arefully programmable with direct con-
trol provided for reference divider, prescaler, feedback divider
and post-scaler.
Compact - 16-pin 0.150” skinny SOIC package
Fully backward compatible to ICS1562
Reset of the pipeline delay on Brooktree RAMDAC s may
be performed under register control. Outputs may also be set
to desired states to facilitate circuit board testing.
ICS1562B - 001 Pinout
Simplified Block Diagram - ICS1562B
LOOP
FILTER
AD0
XTAL1
XTAL2
STROBE
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD1
XTAL1
XTAL2
AD2
CRYSTAL
OSCILLATOR
PHASE-
/ R
CHARGE
PUMP
VCO
FREQUENCY
DETECTOR
AD3
VDD
VDDO
IPRG
CLK+
CLK-
PRESCALER
EXTFBK
BLANK
VSS
(-201 only)
MUX
/ A
/ M
LOAD
LD/N2
FEEDBACK DIVIDER
PROGRAMMING
INTERFACE
16-Pin SOIC
MUX
CLK+
/ 2
/ 4
DIFF.
OUTPUT
CLK−
ICS1562B - 201 Pinout
EXTFBK
XTAL1
XTAL2
DATCLK
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DATA
HOLD
BLANK
VDD
/ N1
MUX
DRIVER
LOAD
LD/N2
/ N2
VDDO
IPRG
CLK+
CLK-
DRIVER
VSS
LOAD
LD/N2
Figure 1
16-Pin SOIC
RAMDAC is a trademark of Brooktree Corporation.
1562 B Rev B 10/07/04
ICS1562B
Overview
PLL Post-Scaler
The ICS1562B is ideally suited to provide the graphics system Aprogrammablepost-scaler maybeinserted betweenthe VCO
clock signals required by high-performance video DACs. and the CLK+ and CLK- outputs of the ICS1562B. This is
Fully programmable feedback and reference divider capability useful in generating lower frequencies, as the VCO has been
allow virtually any frequency to be generated, not just simple optimized for high-frequency operation.
multiples of the reference frequency. The ICS1562B uses the
latest generation of frequency synthesis techniques developed The post-scaler allows the selection of:
by ICS and is completely suitable for the most demanding
video applications.
• VCO frequency
• VCO frequency divided by 2
• VCO frequency divided by 4
PLL Synthesizer Description -
Ratiometric Mode
• Internal register bit (AUXCLK) value
The ICS1562B generates its output frequencies using phase-
locked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency pro-
vided to the PLL (see Figure 1). The reference frequency is
generated by an on-chip crystal oscillator or the reference
frequency may be applied to the ICS1562B from an external
frequency source.
Load Clock Divider
The ICS1562B has an additional programmable divider (re-
ferred to in Figure 1 as the N1 divider) that is used to generate
the LOAD clock frequency for the video DAC. The modulus
of this divider may be set to 3, 4, 5, 6, 8, 10, 12, 16 or 20 under
register control. The design of this divider permits the output
duty factor to be 50/50, even when an odd modulus is selected.
The input frequency to this divider is the output of the PLL
post-scaler described above. Additionally, this divider can be
disabled under register control.
The phase-frequency detector shown in the block diagram
drives thevoltage-controlled oscillator, orVCO, to a frequency
that will cause the two inputs to the phase-frequency detector
to be matched in frequency and phase. This occurs when:
.
F(XTAL1) Feedback Divider
F(VCO): =
Digital Inputs - ICS1562B-001 Option
Reference Divider
This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency provided
to the part (assuming correctly programmed dividers).
The AD0-AD3 pins and the STROBE pin are used to load all
control registers of the ICS1562B (-001 option). The AD0-
AD3 and STROBE pins are each equipped with a pull-up and
will be at a logic HIGH level when not connected. They may
be driven with standard TTL or CMOS logic families.
The VCO gain is programmable, which permits the ICS1562B
to be optimized for best performance at all operating frequencies.
The address of the register to be loaded is latched from the
AD0-AD3 pins by a negative edge on the STROBE pin. The
data for that register is latched from the AD0-AD3 pins by a
positive edge on the STROBE pin. See Figure 2 for a timing
diagram. After power-up, theICS1562B-001 requires 32 reg-
ister writes for new programming to become effective. Since
only 13 registers are used at present, the programming system
can perform 19 “dummy” writes to address 13 or 14 to com-
plete the sequence.
The reference divider may be programmed for any modulus
from 1 to 128 in steps of one.
The feedback divider may be programmed for any modulus
from 37 through 448 in steps of one. Any even modulus from
448 through 896 can also be achieved by setting the “double”
bit which doubles the feedback divider modulus. The feedback
divider makes use of a dual-modulus prescaler technique that
allows the programmable counters to operate at low speed
without sacrificing resolution. This is an improvement over
conventional fixed prescaler architectures that typically im-
pose a factor-of-four penalty (or larger) in this respect.
Table1permits thederivator of “A”& “M”converterprogram-
ming directly from desired modulus.
2
ICS1562B
ICS1562B-201 Register Loading
This allows the synthesizer to be completely programmed for
the desired frequency before it is made active. Once the part
has been “unlocked” by the 32 writes, programming becomes
effective immediately.
8
DATCLK
6
7
DATA
HOLD
DATA_1
DATA_2
DATA_56
ALL registers identified in the data sheet (0-9, 11, 12 & 15)
MUSTbewrittenuponinitial programming.Theprogramming
registers are not initialized upon power-up, but the latched
outputs of those registers are. The latch is made transparent
after 32 register writes. If any register has not been written, the
stateupon power-up (random) willbecome effective. Registers
13 & 14 physically do not exist. Register 10 does exist, but is
reserved for future expansion. To insure compatibility with
possiblefuture modifications to thedatabase, ICS recommends
that all three unused locations be written with zero.
Figure 3
An additional control pin on the ICS1562B-201, BLANK can
perform either of two functions. It may be used to disable the
phase-frequency detector in line-locked applications. Alterna-
tively, the BLANK pin may be used as a synchronous enable
for VRAM shift clock generation. See sections on Line-Locked
Operations and VRAM shift clock generation for details.
ICS1562B-001 Register Loading
5
STROBE
1
2
3
4
Output Description
AD0-AD3
ADDRESS VALID
DATA VALID
The differential output drivers, CLK+ and CLK, are current-
mode and are designed to drive resistive terminations in a
complementary fashion. The outputs are current-sinking only,
with the amount of sink current programmable via the IPRG
pin. The sink current, which is steered to either CLK+or CLK-,
is four times the current supplied to the IPRG pin. For most
applications, a resistorfrom VDDO toIPRGwill setthecurrent
to the necessary precision. Additionally, minor adjustment to
the duty factor can be achieved under register control.
Figure 2
Digital Inputs - ICS1562B-201 Option
The programming of the ICS1562B-201 is performed serially
by using the DATCLK, DATA, and HOLD~pins to load an
internal shift register.
The LOAD output is a high-current CMOS type drive whose
frequency is controlled by a programmable divider that may be
selected for a modulus of 3, 4, 5, 6, 8, 10, 12, 16 or 20. It may
also be suppressed under register control. The load output may
be programmed to output the VCO frequency divided by 2 (see
AUX_N1 description in Register Mapping section), inde-
pendent of the differential output and N1 divider modulus.
DATA is shifted into the register on the rising edge of
DATCLK. The logic value on the HOLD~pin is latched at the
same time. When HOLD~ is low, the shift register may be
loaded without disturbing the operation of the ICS1562B.
When high, the shift register outputs are transferred to the
control registers, and the new programming information be-
comes active. Ordinarily, a high level should be placed on the
HOLD~ pin when the last data bit is presented. See Figure 3
for the programming sequence.
The LD/N2 output is high-current CMOS type drive whose
frequency is derived from the LOAD output. The programma-
ble modulus may range from 1 to 512 in steps of one.
3
ICS1562B
If an external reference frequency source is to be used with the
ICS1562B. it is important that it be jitter-free. The rising and
falling edges of that signal should be fast and free of noise for
best results.
Pipeline Delay Reset Function
The ICS1562Bimplements the clocking sequence required to
reset the pipeline delay on Brooktree RAMDACs when the
LOAD output is programmed for a modulus of either 3, 4, 5,
6, 8 or 10. This sequence can be generated by setting the
appropriate register bit (DACRST) to a logic 1 and then reset-
ting to logic 0.
The loop phase is locked to the falling edges of the XTAL1
input signals if the REFPOL bit is set to logic 0.
When changing frequencies, it is advisable to allow 500 mi-
croseconds after the new frequency is selected to activate the
Internal Feedback
reset function. The output frequency of the synthesizer should The ICS1562B supports LOAD (N1) and N2 divider
be stable enough at that point for the video DAC to correctly
execute its reset sequence. See Figure 4 for a diagram of the
pipeline delay reset sequence.
chains to act as the feedback divider for the PLL.
The N1 and N2 divider chains allow a much larger modulus to
beachieved than thePLL’s ownfeedbackdivider. Additionally,
the output of the N2 counter is accessible off-chip for perform-
ing horizontal reset of the graphics system, where necessary.
This mode is set under register control (ALTLOOP bit). The
reference divider (R counter) will ordinarily be set to divide by
1 in this mode, and the reference input will be supplied to
the XTAL1 input. The output frequency of the synthesizer
will then be:
Pipeline Delay Reset Timing
STROBE
or
DATCLK
11
10
9
CLK+
12
TCLK
LOAD
. .
(CLK) : = F (XTAL1) N1 N2.
F
Figure 4
By using the phase-detector hardware disable mode, the PLL
can be made to free-run at the beginning of the vertical interval
of the external video, and can be reactivated at its completion.
Reference Oscillator and Crystal
Selection
The ICS1562B has circuitry on-board to implement a Pierce
oscillator with the addition of only one external component, a
quartz crystal. Pierce oscillators operate the crystal in anti-
(also called parallel-) resonant mode. See the AC Charac-
teristics for the effective capacitive loading to specify when
ordering crystals.
ICS1562B-001 The ICS1562B-001 supports phase detector
disable via a special control mode. When the
PDRSTEN (phase detector reset enable) bit is
set and the last address latched is 15 (0Fh), a
high level on AD3 will disable PLL locking.
ICS1562B-201 The ICS1562B-201 supports phase detector
disable via the BLANK pin. When the
PDRSTEN bit is set, a high level on the
BLANK input will disable PLL locking.
Series-resonant crystals may also be used with the ICS1562B.
Be aware that the oscillation frequency will be slightly higher
than the frequency that is stamped on the can (typically 0.025-
0.05%).
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, we recommend that the
crystal bemountedas closelyas possible tothepackage. Avoid
routing digital signals or the ICS1562B outputs underneath or
near these traces. It is also desirable to ground the crystal can
to the ground plane, if possible.
4
ICS1562B
External Feedback Operation
Power-On Initialization
The ICS1562B-201 option also supports the inclusion of an The ICS1562B has an internal power-on reset circuit that
external counter as the feedback divider of the PLL. This mode performs the following functions:
is useful in graphic systems that must be “genlocked” to
external video sources.
1) Sets the multiplexer to pass the reference frequency
to the CLK+ and CLK- outputs.
When the EXTFBEN bit is set to logic 1, the phase-frequency
detector will use the EXTFBK pin as its feedback input. The
loop phasewillbelocked to therising edges of the signal applied
to the EXTFBK input if the FBKPOL bit is set to logic 0.
2) Selects the modulus of the N1 divider (for the
LOAD clock) to be four.
These functions should allow initialization of most graphics
systems that cannot immediately provide for register program-
ming upon system power-up.
VRAM Shift Clock Generation
The ICS1562B-201 option supports VRAM shift clock gen-
eration and interruption. By programming the N2 counter to
divide by 1, the LD/N2 output becomes a duplicate of the
LOAD output. When the SCEN bit is set, the LD/N2 output
may be synchronously started and stopped via the blank pin.
When BLANK is high, the LD/N2 will be free-running and in
phase with LOAD. When BLANK is taken low, the LD/N2
output is stopped at a low level. See Figure 5 for a diagram of
the sequence. Note that this use of the BLANKpin precludes its
use for phase comparator disable (see Line-Locked Operation).
Because the power-on reset circuit is on the VDD supply, and
because that supply is filtered, care must be taken to allow the
reset to de-assert before programming. A safe guideline is to
allow 20 microseconds after the VDD supply reaches 4 volts.
Programming Notes
•
VCO Frequency Range: Use the post-divider to keep the
VCO frequency as high as possible within its operating
range.
•
Divider Range: For best results in normal situations (i.e,
pixel clock generation for hi-res displays), keep the refer-
ence divider modulus as short as possible (for a frequency
at the output of the reference divider in the few hundred
kHz to several MHz range). If you need to go to a lower
phase comparator reference frequency (usually required
for increased frequency accuracy), that is acceptable, but
jitter performance will suffer somewhat.
VRAM Shift Clock Control
BLANK
LOAD
LD/N2
•
VCO Gain Programming: Use the minimum gain which
can reliably achieve the VCO frequency desired, as shown
on the following page:
Figure 5
5
ICS1562B
Power Supplies and Decoupling
VCO GAIN
MAX FREQUENCY
120 MHz
200 MHz
260 MHz
*
4
5
6
7
The ICS1562B has two VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). BOTH of these pins
should connect to the ground plane of the video board as close
to the package as is possible.
*SPECIAL APPLICATION. Contact factory for custom product above
260 MHz.
The ICS1562B has a VDDO pin which is the supply of +5 volt
power to all output drivers. This pin should be connected to the
power plane (or bus) using standard high-frequency decou-
plingpractice. That is, capacitors should have lowseries induc-
tance and be mounted close to the ICS1562B.
•
Phase Detector Gain: For most graphics applications and
divider ranges, set P[1, 0] = 10 and set P[2] = 1. Under
some circumstances, setting the P[2] bit “on” can reduce
jitter. During 1562 operation at exact multiples of the
crystal frequency, P[2] bit = 0 may provide the best jitter
performance.
The VDD pin is the power supply pin for the PLL synthesizer
circuitry and other lower current digital functions. We recom-
mend that RC decoupling or zener regulation be provided for
this pin (as shown in the recommended application circuitry).
This will allow the PLL to “track” through power supply
fluctuations without visible effects. See Figure 6 for typical
external circuitry.
Board Test Support
It is often desirable to statically control the levels of the output
pins for circuitboardtest.TheICS1562B supports this through
a register programmable mode, AUXEN. When this mode is
set, two register bits directly control the logic levels of the
CLK+/CLK- pins and the LOAD pin. This mode is activated
when the S[0] and S[1] bits are both set to logic 1. See Register
Mapping for details.
Figure 6
6
ICS1562B
a)
ICS1562B-001 Typical Interface
DATA BUS
0.1µF
+5V
1
2
3
4
5
6
7
8
AD0
AD1
AD2
AD3
VDD
16
15
14
13
22µF
XTAL1
XTAL2
STROBE
VSS
+
+5V
82
SELECT LOGIC
VDDO 12
82
VSS
LOAD
LD/N2
IPRG
CLK+
CLK-
11
10
9
10
0.1µF
TO
RAMDAC
+5V
820
820
510
0.1µF
b)
ICS1562B-201 Typical Interface
GRAPHICS
CONTROLLER
0.1µF
+5V
1
2
3
4
5
6
7
8
EXTFBK
XTAL1
XTAL2
DATCLK
VSS
DATA
HOLD
16
15
22µF
PROGRAMMING
INTERFACE
+
BLANK 14
VDD
13
12
11
10
9
+5V
VDDO
IPRG
CLK+
CLK-
VSS
82
82
10
LOAD
LD/N2
0.1µF
TO
RAMDAC
+5V
820
820
510
0.1µF
Figure 7
7
ICS1562B
Register Mapping - ICS1562B-001 (Parallel Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1562B. PC SOFTWARE IS AVAILABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.
REG#
BIT(S)
BIT REF.
DESCRIPTION
0
1
0-3
0-2
R[0]..R[3]
R[4]..R[6]
Reference divider modulus control bits
Modulus = value + 1
1
3
REFPOL
PLL locks to the rising edge of XTAL1 input when REFPOL=1 and
to the falling edge of XTAL1 when REFPOL=0.
2
0-3
A[0]..A[3]
Controls A counter. When set to zero, modulus=7. Otherwise,
modulus=7 for “value” underflows of the prescaler, and modulus=6
thereafter until M counter underflows.
3
4
0-3
0-1
M[0]..M[3]
M[4]..M[5]
M counter control bits
Modulus = value + 1
4
2
FBKPOL
External feedback polarity control bit. The PLL will lock to the falling
edge of EXTFBK when FBKPOL=1 and to the rising edge of
EXTFBK when FBKPOL=0.
4
5
3
DBLFREQ
Doubles modulus of dual-modulus prescaler (from 6/7 to 12/14).
0-3
N1[0]..N1[3]
Sets N1 modulus according to this table. These bits are set to imple-
ment a divide-by-four on power-up.
N1[3]
N1[2]
N1[1]
N1[0]
RATIO
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
3
4
0
4
0
5
1
6
1
8
1
8
1
10
12
16
16
20
X
X
X
X
X=Don’t Care
8
ICS1562B
REG#
BIT(S)
BIT REF.
DESCRIPTION
6
7
0-3
0-3
N2[0]..N2[3]
N2[4]..N2[7]
Sets the modulus of the N2 divider.
The input of the N2 divider is the output of the N1 divider in all clock
modes except AUXEN.
8
3
N2[8]
8
9
0-2
0-1
V[0]..V[1]
P[0]..P[1]
Sets the gain of the VCO.
Sets the gain of the phase detector according to this table.
V[2]
V[1]
V[0]
VCO GAIN
(MHz/VOLT)
1
1
1
1
0
0
1
1
0
1
0
1
30
45
60
80
9
3
[P2]
Phase detector tuning bit. Normally should be set to one.
P[1]
P[0]
GAIN (uA/radian)
0
0
1
1
0
1
0
1
0.05
0.15
0.5
1.5
10
1
LOADEN~
Load clock divider enable (active low). When set to logic 1, the
LOAD and LD/N2 outputs will cease toggling.
10
10
2
3
SKEW-
SKEW+
Differential output duty factor adjust.
SKEW+
SKEW-
0
0
0
1
Default
Reduces THIGH by approximately
100 ps
1
1
0
1
Increases THIGH by approximately
100 ps
Do not use
9
ICS1562B
REG#
11
BIT(S)
0-1
BIT REF.
S[0]..S[1]
DESCRIPTION
PLL post-scaler/test mode select bits
S[1] S[0]
DESCRIPTION
Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
0
0
1
1
0
1
0
1
AUXEN CLOCK MODE. The AUXCLK bit drives the differential
outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD
output which, in turn, drives the N2 divider.
11
11
2
3
AUX_CLK
AUX_N1
When in the AUXEN clock mode, this bit controls the differential
outputs.
When in the AUXEN clock mode, this bit controls the LOAD output
(and consequently the N2 output according to its programming).
When not in the AUXEN clock mode, this bit, if set to one, will over-
ride the N1 divider modulus and output the VCO frequency divided
by two [F(PLL)/2] at the LOAD output.
12
12
0
1
RESERVED
JAMPLL
Must be set to zero.
Tristates phase detector outputs; resets phase detector logic, and
resets R, A, M, and N2 counters.
12
2
DACRST
Set to zero for normal operation. When set to one, the CLK+output
is kept high and the CLK- output is kept low. (All other device func-
tions are unaffected.) When returned to zero, the CLK+ and CLK-
outputs will resume toggling on a rising edge of the LD output
(+/- 1 CLK period). To initiate a RAMDAC reset sequence,
simply write a one to this register bit followed by a zero.
12
15
3
0
SELXTAL
ALTLOOP
When set to logic 1, passes the reference frequency to the post-scaler.
Controls substitution of N1 and N2 dividers into feedback loop of PLL.
When this bit is a logic 1, the N1 and N2 dividers are used.
15
3
PDRSTEN
Phase-detector reset enable control bit. When this bit is set, the AD3
pin becomes a transparent reset input to the phase detector.
See "Internal Feedback Operation" section for more
details on the operation of this function.
10
ICS1562B
Register Mapping - ICS1562B-201 (Serial Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1562B. PC SOFTWARE IS AVAILABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.
BIT(S)
1-4
BIT REF.
DESCRIPTION
N1[0]..N1[3]
Sets N1 modulus according to this table. These bits are set to implement
a divide-by-four on power-up.
N1[3]
N1[2]
N1[1]
N1[0]
RATIO
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
3
4
0
4
0
5
1
6
1
8
1
8
1
10
12
16
16
20
X
X
X
X
5
6
RESERVED
JAMPLL
Must be set to zero.
Tristates phase detector outputs, resets phase detector logic, and resets
R, A, M, and N2 counters.
7
DACRST
Set to zero for normal operations. When set to one, the CLK+ output is
kept high and the CLK- output is kept low. (All other device functions are
unaffected.) When returned to zero, the CLK+ and CLK- outputs will
resume toggling on a rising edge of the LD output (+/−1 CLK period).
To initiate a RAMDAC reset sequence, simply write a one to this register
bit followed by a zero.
8
9
SELXTAL
ALTLOOP
When set to logic 1, passes the reference frequency to the post-scaler.
Controls substitution of N1 and N2 dividers into feedback loop of PLL.
When this bit is a logic 1, the N1 and N2 dividers are used.
10
11
12
SCEN
VRAM shift clock enable bit. When logic 1, the BLANK pin can be used
to disable the LD/N2 output.
EXTFBKEN
PDRSTEN
External PLL feedback select. When logic 1, the EXTFBK pin is used for
the phase-frequency detector feedback input.
Phase detector reset enable control bit. When this bit is set, a high level
on the BLANK input will disable PLL locking. See "Internal Feedback
Operation" section for more details on the operation of this function.
11
ICS1562B
BIT(S)
13-14
BIT REF.
S[0]..S[1]
DESCRIPTION
PLL post-scaler/test mode select bits.
S[1] S[0]
DESCRIPTION
0
0
1
1
0
1
0
1
Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divder
drives the LOAD output which, in turn, drives the N2 divider.
AUXEN CLOCK MODE. The AUXCLK bit drives the differential
outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD
output which, in turn, drives the N2 divider.
15
16
AUX_CLK
AUX_N1
When in the AUXEN clock mode, this bit controls the differential outputs.
When in the AUXEN clock mode, this bit controls the N1 output (and
consequently the N2 output according to its programming). When not in
the AUXEN clock mode, this bit, if set to one, will override the N1 divider
modulus and output the VCO frequency divided by two [F(PLL)/2] at the
LOAD output.
17-24
28
N2[0]..N2[7]
N2[8]
Sets the modulus of the N2 divider. The input of the N2 divider is the
output of the N1 divider in all clock modes except AUXEN.
25-27
V[0]..V[2]
Sets the gain of VCO according to this table.
V[2]
V[1]
V[0]
VCO GAIN
(MHz/VOLT)
1
1
1
1
0
0
1
1
0
1
0
1
30
45
60
80
29-30
P[0]..P[1]
Sets the gain of the phase detector according to this table.
P[1]
0
P[0]
0
GAIN (uA/radian)
0.05
0.15
0.5
0
1
1
0
1
1
1.5
31
32
RESERVED
P[2]
Set to zero.
Phase detector tuning bit. Should normally be set to one.
12
ICS1562B
BIT(S)
33-38
BIT REF.
DESCRIPTION
M[0]..M[5]
M counter control bits
Modulus = value +1
39
FBKPOL
External feedback polarity control bit. The PLL will lock to the falling
edge of EXTFBK when FBKPOL=1 and to the rising edge of EXTFBK
when FBKPOL=0.
40
DBLFREQ
A[0]..A[3]
Doubles modulus of dual-modulus prescaler (from 6/7 to 12/14).
41-44
Controls A counter. When set to zero, modulus=7. Otherwise,
modulus=7 for “value” underflows of the prescaler, and modulus=6
thereafter until M counter underflows.
45
46
RESERVED
LOADEN~
Set to zero.
Load clock divider enable (active low). When set to logic 1, the LOAD
and LD/N2 outputs will cease toggling.
47
48
SKEW-
SKEW+
Differential output duty factor adjust.
SKEW+
SKEW-
0
0
0
1
Default
Reduces THIGH by approximately
100 ps
1
1
0
1
Increases THIGH by approximately
100 ps
Do not use
49-55
56
R[0]..R[6]
REFPOL
Reference divider modulus control bits
Modulus = value + 1
PLL locks to the rising edge of XTAL1 input when REFPOL=1 and to
the falling edge of XTAL1 when REFPOL=0.
13
ICS1562B
Table 1 - “A” & “M” Divider Programming
Feedback Divider Modulus Table
A[2]..A[0]-
M[5]..M[0]
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
001
010
011
100
101
110
111
000
A[2]..A[0]-
M[5]..M[0]
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
001
010
011
100
101
110
111
000
199
205
211
217
223
229
235
241
247
253
259
265
271
277
283
289
295
301
307
313
319
325
331
337
343
349
355
361
367
373
379
385
200
206
212
218
224
230
236
242
248
254
260
266
272
278
284
290
296
302
308
314
320
326
332
338
344
350
356
362
368
374
380
386
201
207
213
219
225
231
237
243
249
255
261
267
273
279
285
291
297
303
309
315
321
327
333
339
345
351
357
363
369
375
381
387
202
208
214
220
226
232
238
244
250
256
262
268
274
280
286
292
298
304
310
316
322
328
334
340
346
352
358
364
370
376
382
388
203
209
215
221
227
233
239
245
251
257
263
269
275
281
287
293
299
305
311
317
323
329
335
341
347
353
359
365
371
377
383
389
204
210
216
222
228
234
240
246
252
258
264
270
276
282
288
294
300
306
312
318
324
330
336
342
348
354
360
366
372
378
384
390
205
211
217
223
229
235
241
247
253
259
265
271
277
283
289
295
301
307
313
319
325
331
337
343
349
355
361
367
373
379
385
391
231
238
245
252
259
266
273
280
287
294
301
308
315
322
329
336
343
350
357
364
371
378
385
392
399
406
413
420
427
434
441
448
7
14
13
19
20
26
21
25
27
33
28
31
32
34
40
35
37
38
39
41
47
42
43
44
45
46
48
54
49
49
50
51
52
53
55
61
56
55
56
57
58
59
60
63
61
62
63
64
65
66
67
70
67
68
69
70
71
72
73
77
73
74
75
76
77
78
79
84
79
80
81
82
83
84
85
91
85
86
87
88
89
90
91
98
91
92
93
94
95
96
97
105
112
119
126
133
140
147
154
161
168
175
182
189
196
203
210
217
224
97
98
99
100
106
112
118
124
130
136
142
148
154
160
166
172
178
184
190
196
101
107
113
119
125
131
137
143
149
155
161
167
173
179
185
191
197
102
108
114
120
126
132
138
144
150
156
162
168
174
180
186
192
198
103
109
115
121
127
133
139
145
151
157
163
169
175
181
187
193
199
103
109
115
121
127
133
139
145
151
157
163
169
175
181
187
193
104
110
116
122
128
134
140
146
152
158
164
170
176
182
188
194
105
111
117
123
129
135
141
147
153
159
165
171
177
183
189
195
Notes:
To use this table, find the desired modulus in the table. Follow the column up to find the A divider programming values.
Follow the row to the left to find the M divider programming. Some feedback divisors can be achieved with two or three
combinations of divider settings. Any are acceptable for use.
.
N =[(M +1) 6] +A
The formula for the effective feedback modulus is:
except when A=0, then:
.
N=(M +1) 7
Under all circumstances:
A ≤ M
14
ICS1562B
Pin Descriptions - ICS1562B-001
PIN#
NAME
DESCRIPTION
10
CLK+
Clock out (non-inverted)
Clock out (inverted)
9
7
CLK−
LOAD
XTAL1
XTAL2
AD0
Load output. This output is normally at the CLK frequency divided by N1.
Quartz crystal connection 1/external reference frequency input
Quartz crystal connection 2
2
3
1
Address/Data Bit 0 (LSB)
16
15
14
8
AD1
Address/Data Bit 1
AD2
Address/Data Bit 2
AD3
Address/Data Bit 3 (MSB)
LD/N2
STROBE
VDD
Divided LOAD output. See text.
4
Control for address/data latch
13
12
11
5,6
PLL system power (+5V. See application diagram.)
Output stage power (+5V)
VDDO
IPRG
VSS
Output stage current set
Device ground. Both pins must be connected to the same ground potential.
Pin Descriptions - ICS1562B-201
PIN#
NAME
DESCRIPTION
10
CLK+
Clock out (non-inverted)
Clock out (inverted)
9
7
CLK−
LOAD
XTAL1
XTAL2
DATCLK
DATA
Load output. This output is normally at the CLK frequency divided by N1.
Quartz crystal connection 1/external reference frequency input
Quartz crystal connection 2
2
3
4
Data Clock (Input)
16
15
14
8
Serial Register Data (Input)
HOLD~
BLANK
LD/N2
EXTFBK
VDD
HOLD (Input)
Blanking (Input). See Text.
Divided LOAD output/shift clock. See text.
External feedback connection for PLL (input). See text.
PLL system power (+5V. See application diagram.)
Output stage power (+5V)
1
13
12
11
5,6
VDDO
IPRG
Output stage current set
VSS
Device ground. Both pins must be connected.
15
ICS1562B
Absolute Maximum Ratings
VDD, VDDO (measured to VSS). . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS-0.5 to VDD + 0.5 V
Digital Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS-0.5 to VDDO + 0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . -55 to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Soldering Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Recommended Operating Conditions
VDD, VDDO (measured to VSS). . . . . . . . . . . . . . . . . . . . . . . 4.75 to 5.25 V
Operating Temperature (Ambient) . . . . . . . . . . . . . . . . . . . . . 0 to 70°C
DC Characteristics
TTL-Compatible Inputs
001 Option - (AD0-AD3, STROBE),
201 Option - (DATCLK, DATA, HOLD, BLANK, EXTFBK)
PARAMETER
Input High Voltage
SYMBOL
CONDITIONS
MIN
MAX
VDD+0.5
0.8
UNITS
V
Vih
Vil
Iih
2.0
Input Low Voltage
VSS-0.5
V
Input High Current
Vih=VDD
Vil=0.0
-
-
10
uA
uA
pf
Input Low Current
Iil
200
Input Capacitance
Cin
Vhys
-
8
Hysteresis (STROBE/DATCLK)
VDD=5V
.20
.60
V
XTAL1 Input
PARAMETER
Input High Voltage
SYMBOL
Vxh
CONDITIONS
MIN
3.75
MAX
VDD+0.5
1.25
UNITS
V
Input Low Voltage
Vxl
VSS-0.5
CLK+, CLK- Outputs
PARAMETER
SYMBOL
CONDITIONS
CONDITIONS
MIN
0.6
MAX
-
UNITS
V
Differential Output Voltage
LOAD, LD/N2 Outputs
PARAMETER
SYMBOL
MIN
2.4
-
MAX
-
UNITS
Output High Voltage (Ioh = 4.0mA)
Output Low Voltage (Iol = 8.0mA)
V
V
0.4
16
ICS1562B
AC Characteristics
SYMBOL
PARAMETER
MIN
40
TYP
20
MAX
UNITS
MHz
MHz
pf
Fvco
Fxtal
Cpar
Fload
Txhi
Txlo
Tlock
Idd
VCO Frequency (see Note 1)
Crystal Frequency
260
20
5
Crystal Oscillator Loading Capacitance
LOAD Frequency
80
MHz
ns
XTAL1 High Time (when driven externally)
XTAL1 Low Time (when driven externally)
PLL Acquire Time (to within 1%)
VDD Supply Current
8
8
ns
500
15
µs
t.b.d.
t.b.d.
mA
mA
Iddo
20
VDDO Supply Current (excluding CLK+/−
termination)
Thigh
Jclk
Differential Clock Output Duty Cycle
(see Note 2)
Differential Clock Output Cumulative Jitter
(see Note 3)
45
55
%
<0.06
pixel
DIGITAL INPUTS - ICS1562B-001
1
2
3
4
5
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
10
10
10
10
ns
ns
ns
ns
ns
STROBE Pulse Width (Thi or Tlo)
20
DIGITAL INPUTS - ICS1562B-201
6
7
8
DATA/HOLD~ Setup Time
DATA/HOLD~ Hold Time
10
10
ns
ns
ns
DATCLK Pulse Width (Thi or Tlo)
20
PIPELINE DELAY RESET
9
Reset Activation Time
Reset Duration
2*Tclk
ns
ns
ns
ns
10
11
12
4*Tload
Restart Delay
2*Tload
Restart Matching
-1*Tclk
+1.5*Tclk
DIGITAL OUTPUTS
13
14
260
+2
MHz
ns
CLK+/CLK− Clock Rate
LOAD To LD/N2 Skew (Shift Clock Mode)
-2
0
Note 1: Use of the post-divider is requiredfor frequencies lowerthan 40 MHzon CLK+& CLK-outputs. Useof thepost-divider
is recommended for output frequencies lower than 65 MHz.
Note 2: Using load circuit of Figure 6. Duty cycle measured at zero crossings of difference voltage between CLK+ and CLK-.
Note 3: Cumulative jitter is defined as the maximum error (in the domain) if any CLK edge, at any point in time, compared with
the equivalent edge generated by an ideal frequency source.
ICS laboratory testing indicates that the typical value shown above can be treated as a maximum jitter specification in
virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and register
programming.
17
ICS1562B Application Information
Output Circuit Considerations for the ICS1562B
Stripline is the other form a PCB transmission line can take. A
buried trace between ground planes (or between a power plane
and a ground plane) is common in multi-layer boards.
Attempting to create a workstation design without the use of
multi-layer boards would be adventurous to say the least, the
issue would more likely be whether to place the interconnect
on the surface or between layers. The between layer approach
would work better from an EMI standpoint, but would be more
difficult to lay out. A stripline is shown below:
Output Circuitry
The dot clock signals CLK and CLK- are typically the highest
frequency signals present in the workstation. To minimize
problems with EMI, crosstalk, and capacitive loading extra
care should be taken in laying out this area of the PC board.
The ICS1562B is packaged in a 0.2”-wide 16-pin SOIC pack-
age. This permits the clock generator, crystal, and related
components to be laid out in an area thesize of a postagestamp.
The ICS1562B should be placed as close as possible to the
RAMDAC. The CLK and CLK- pins are running at VHF
frequencies; one should minimize the length of PCB trace
connecting them to the RAMDAC so that they don’t become
radiators of RF energy.
At the frequencies that the ICS1562B is capable of, PC board
traces may be long enough to be a significant portion of a
wavelength of that frequency. PC traces for CLK and CLK-
should betreated as transmissionlines, notjust interconnecting
wires. These lines can take two forms: microstrip and stripline.
A microstrip line is shown below:
Using 1 oz. copper (0.0015” thick) and 0.040” thickness G10,
a 0.010” trace will exhibit a characteristic impedance of 75Ω
in a stripline configuration.
Typically, RAMDACs require a Vih of VAA-1.0 Volts as a
guaranteed logical “1” and a Vil of VAA-1.6 as a guaranteed
logical “0.” Worst case input capacitance is 10 pF.
Output circuitry for the ICS1562B is shown in the following
diagram. It consists of a 4/1 current mirror, and two open drain
output FETs along with inverting buffers to alternately enable
each current-sinking driver. Both CLK and CLK- outputs are
connected to the respective CLOCK and CLOCK inputs of the
RAMDAC with transmission lines and terminated in their
equivalent impedances by the Thevenin equivalent impedances
of R1 and R2 or R1’and R2’.
Essentially, the microstrip is a copper trace on a PCB over a
ground plane. Typically, the dielectric is G10 glass epoxy. It
differs from a standard PCB trace in that its width is calculated
to have a characteristic impedance. To calculate the charac-
teristic impedance ofa microstriplineonemustknow thewidth
and thickness of the trace, and the thickness and dielectric
constant of the dielectric. For G10 glass epoxy, the dielectric
constant (er) is about 5. Propagation delay is strictly a function
of dielectricconstant. For G10propagation, delay is calculated
to be 1.77 ns/ft.
18
ICS1562B Application Information
Cb is shown as multiple capacitors. Typically, a 22 µf tantalum
should be used with separate.1 µF and 220pf capacitors placed
as close to the pins as possible. This provides low series
inductance capacitors right at the source of high frequency
energy. Rd is used to isolate the circuitry from external
sources of noise. Five to ten ohms should be adequate.
The ICS1562B is incapable of sourcing current, so Vih must
be set by the ratios of these resistors for each of these lines. R1
and R2 are electrically in parallel from an AC standpoint
because Vdd is bypassed to ground through bypass-capacitor
network Cb. If we picked a target impedance of 75Ω for our
transmission line impedance, a value of 91Ω for R1 and R1’
and a value of 430Ω for R2 and R2’ would yield a Thevinin
equivalent characteristic impedance of 75.1Ω and a Vih value
of VAA-.873 Volts, a margin of 0.127 Volts. This may be
adequate; however, at higher frequencies one must contend
with the 10 pF input capacitance of the RAMDAC. Values of
82Ω for R1 and R1’and 820Ω for R2 and R2’would give us a
characteristic impedance of 74.5Ω and a Vih value of VAA-.45.
With a .55 Volt margin on Vih, this voltage level might be safer.
To set a value for Vil, we must determine a value for Iprg that
will cause the output FET’s to sink an appropriate current. We
desire Vil to be VAA-1.6 or greater. VAA-2 would seem to be a
safe value. Setting up a sink current of 25 milliamperes would
guarantee this through our 82Ω pull-up resistors. As this is
controlled by a 4/1 current mirror, 7 mAinto Iprg should set this
current properly. A510Ω resistor from Vdd to Iprg should work
fine.
ICS1562B Output Circuitry
Resistors Rt and Rt’ are shown as series terminating resistors
at the ICS1562B end of the transmission lines. These are not
required for operation, but may be useful for meeting EMI
requirements. Their intent is to interact with the input capaci-
tance of the RAMDAC and the distributed capacitance of the
transmission line to soften up rise and fall times and conse-
quently cut some of the high-order harmonic content that is
more likely to radiate RF energy. In actual usage they would
most likely be 10 to 20Ω resistors or possibly ferrite beads.
Great care must be used when evaluating high frequency
circuits to achieve meaningful results. The 10 pF input capaci-
tance and long ground lead of an ordinary scope probe will
make any measurements made with it meaningless. A low
capacitance FET probe with a ground connection directly
connected to the shield at the tip will be required. A 1GHz
bandwidth scope will be barely adequate, try to find a faster
unit.
19
ICS1562B
Package Dimensions
16-Pin Skinny SOIC Package
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Ordering Information
ICS1562BM-001 or ICS1562BM-201
Example:
ICS 1562B M -XXX
Pattern Number (LF=SOIC Pb free), (3 digit number for parts with ROM code patterns)
Package Type
M=SOIC
Device Type
Prefix
I C S = S t a n d a r d
20
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