ICS301M-XX-LF [IDT]
Clock Generator, 200MHz, CMOS, PDSO8, SOIC-8;型号: | ICS301M-XX-LF |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Clock Generator, 200MHz, CMOS, PDSO8, SOIC-8 光电二极管 |
文件: | 总4页 (文件大小:68K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ICS300/ICS301/ICS302
QTClock™ Quick Turn Clock Synthesizer
Description
Features
• Packaged as 8 pin SOIC
The ICS300 and ICS301 QTClocks™ generate a
high quality, high frequency clock output and a
reference from a low frequency crystal or clock
input. They are designed to replace crystals and
crystal oscillators in most electronic systems. The
ICS302 can accept a higher frequency clock input
to generate up to 200 MHz. The devices contain a
One Time Programmable (OTP) ROM which is
factory programmed with the PLL divider values
to output a broad range of frequencies, from 6 to
200 MHz, allowing customer requests for different
frequencies to be shipped in 1-3 days. Using
Phase-Locked-Loop (PLL) techniques, the devices
run from a standard fundamental mode,
• Quick turn frequency programming allows
samples in one to three days
• Replaces nearly any crystal or oscillator
• ICS300 produces up to 100 MHz at 3.3V,
ICS301 produces up to 200 MHz at 3.3V
ICS302 accepts up to 125 MHz clock input
• Easy to cascade with ICS5xx series
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 2 - 125 MHz
• Low jitter - 50 ps one sigma
inexpensive crystal, or clock. They are smaller and
less expensive than one oscillator.
• Compatible with all popular CPUs
• Duty cycle of 45/55
• Operating voltages of 3.0 to 5.5V
• Full CMOS level outputs with 25mA drive
capability at TTL levels
• Tri-state output + PLL power down pin
• Advanced, low power CMOS process
Block Diagram
VDD GND
OTP
ROM
with PLL
Divider
Output
Buffer
PLL
Clock
Synthesis
and Control
Circuitry
CLK
REF
Values
Crystal
or clock
input
X1/ICLK
Divide
Logic and
Output
Buffer
Crystal
Oscillator
X2
PDTS (both outputs and PLL)
MDS 300QT E
1
Revision 111000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel• www.icst.com
ICS300/ICS301/ICS302
QTClock™ Quick Turn Clock Synthesizer
Pin Assignments
X1/ICLK
8
7
6
5
1
X2
PDTS
DC
REF Clock Options
ICS300
ICS301
VDD
GND
REF
2
3
4
REF
Comments
CLK
Reference
Reference/2
CLK/2
Buffered oscillator output
Oscillator frequency divided by two
CLK frequency divided by two
Output stopped low. Lowest jitter
8
7
6
5
ICLK
PDTS
DC
GND
VDD
GND
REF
1
Off
2
3
4
ICS302
CLK
Pin Descriptions
Number Number Name
Type Description
300/1
302
8
1
2
3
4
5
6
7
8
X1/ICLK
VDD
GND
REF
I
P
P
O
O
-
Crystal connection or clock input. Clock only on ICS302.
Connect to +3.3V or +5V.
2
1, 3
4
Connect to ground.
Buffered crystal oscillator output clock, or variation per REF clock options table above.
Clock output. Fixed frequency between 6 and 200 MHz programmed at factory.
Don't Connect anything to this pin.
5
CLK
6
DC
7
PDTS
X2
I
Powers down PLL, and puts both outputs into high impedance state, when low.
Crystal connection. Leave unconnected for clock input.
-
O
Key: I = Input, O = output, P = power supply connection
Device Configuration
The specification is complete when the ICS300/301/302 QTClock Order Form accompanies this data
sheet. The order form lists the input, REF, and CLK actual frequencies, as well as any other available
options. This unique configuration is given a two character alphanumeric programming code, which must
be specified when referring to samples.
External Components / Crystal Selection
The ICS300/301/302 requires a 0.01µF decoupling capacitor to be connected between VDD and GND.
It must be connected close to the ICS300/301/302 to minimize lead inductance. No external power
supply filtering is required for this device. A 33Wterminating resistor can be used next to the CLK and
REF pins. The total on-chip capacitance is approximately 16 pF, so a parallel resonant, fundamental mode
crystal should be used. For crystals with a specified load capacitance greater than 16 pF, crystal capacitors
can be connected from each of the pins X1 and X2 to Ground. The value (in pF) of these crystal caps
should be = (C -16)*2, where C is the crystal load capacitance in pF. These external capacitors are only
L
L
required for applications where the exact frequency is critical. For a clock input, connect to X1/ICLK and
leave X2 unconnected (no capacitors on either).
MDS 300QT E
2
Revision 111000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel• www.icst.com
ICS300/ICS301/ICS302
QTClock™ Quick Turn Clock Synthesizer
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
7
VDD+0.5
VDD+0.5
70
V
V
-0.5
-0.5
0
Clock Output
V
Ambient Operating Temperature
Soldering Temperature
Storage temperature
°C
°C
°C
Max of 10 seconds
260
-65
150
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Operating Voltage, VDD
3
5.5
(VDD/2)-1
0.4
V
V
Input High Voltage, VIH, ICLK only
Input Low Voltage, VIL, ICLK only
Input High Voltage, VIH
ICLK (Pin 1)
ICLK (Pin 1)
PDTS
(VDD/2)+1
VDD/2
VDD/2
V
2
V
Input Low Voltage, VIL
PDTS
V
Output High Voltage, VOH
Output High Voltage, VOH
Output Low Voltage, VOL
IOH=-4mA
IOH=-25mA
IOL=25mA
VDD-0.4
2.4
V
V
0.4
V
IDD Operating Supply Current, 20 MHz crystal No Load, 100MHz
20
±70
270
4
mA
mA
kW
pF
Short Circuit Current
CLK output
Pin 7
On-Chip Pull-up Resistor, PDTS
Input Capacitance, PDTS
Pin 7
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Input Frequency, crystal input, ICS300 and 301
Input Frequency, clock input, ICS300 and 301
Input Frequency, clock input, ICS302
5
2
27
50
MH z
MH z
MH z
MH z
MH z
MH z
MH z
ns
50
6
125
160
100
200
200
Output Frequency, ICS300
VDD = 4.5 to 5.5V
VDD = 3.0 to 3.6V
VDD = 4.5 to 5.5V
VDD = 3.0 to 3.6V
0.8 to 2.0V
Output Frequency, ICS300
6
Output Frequency, ICS301 and ICS302
Output Frequency, ICS301 and ICS302
Output Clock Rise Time
6
6
1
Output Clock Fall Time
2.0 to 0.8V
1
49 to 51
±120
50
ns
Output Clock Duty Cycle (Note 1)
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
at programmed level
Deviation from mean
45
55
%
ps
ps
Power-up time, PDTS goes high until Refer. out Reference on REF clk
Power-up time, PDTS goes high until CLK out
3
10
20
ms
8
ms
Note 1: These are typical values. The actual minimum and maximum duty cycle limits are shown on the
ICS300/301/302 QTClock Order Form for each programmed version.
MDS 300QT E
3
Revision 111000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel• www.icst.com
ICS300/ICS301/ICS302
QTClock™ Quick Turn Clock Synthesizer
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
8 pin SOIC
Inches
Min
Millimeters
Symbol
A
Max
Min
1.35
0.10
0.33
1.91
4.80
3.80
1.27 BSC
5.80
0.25
0.41
Max
E
H
0.0532 0.0688
0.0040 0.0098
0.0130 0.0200
1.75
0.24
0.51
2.40
5.00
4.00
A1
Pin 1
B
C
0.075
0.098
D
E
e
0.1890 0.1968
0.1497 0.1574
.050 BSC
h x 45°
D
H
h
0.2284 0.2440
0.0099 0.0195
0.0160 0.0500
6.20
0.50
1.27
A
C
A1
L
B
L
e
Ordering Information
Part/Order Number
ICS300M-xx
Marking
Package
8 pin SOIC
8 pin SOIC on tape and reel
8 pin SOIC
8 pin SOIC on tape and reel
8 pin SOIC
Temperature
0 to 70 °C
0 to 70 °C
0 to 70 °C
0 to 70 °C
0 to 70 °C
0 to 70 °C
ICS300M
ICS300M
ICS301M
ICS301M
ICS302M
ICS302M
ICS300MT-xx
ICS301M-xx
ICS301MT-xx
ICS302M-xx
ICS302MT-xx
8 pin SOIC on tape and reel
xx represents a 2 character alphanumeric programming code assigned by the factory, which indicates the
output frequencies on CLK and REF. All samples are shipped with an ICS300/301/302 order form
describing the characteristics of the device.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc. (ICS) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any
ICS product for use in life support devices or critical medical instruments.
QTClock is a trademark of ICS
MDS 300QT E
4
Revision 111000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel• www.icst.com
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