ICS387G-XXIT [IDT]
Clock Generator, 200MHz, CMOS, PDSO16, TSSOP-16;
| 型号： | ICS387G-XXIT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 200MHz, CMOS, PDSO16, TSSOP-16 光电二极管 |
| 文件： | 总5页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY INFORMATION
ICS387
Quad PLL Quick Turn Clock Synthesizer
Description
Features
• Packaged as 16 pin TSSOP
The ICS387 QTClock™ generates up to 5 high quality,
high frequency clock outputs including a reference
from a low frequency crystal or clock input. It is designed
to replace crystals and crystal oscillators in most
electronic systems. The ICS387 contains a One Time
Programmable (OTP) ROM which is factory programmed
with PLL divider values to output a broad range of
frequencies up to 200 MHz, allowing customer
• Quick turn frequency programming allows
samples as quickly as one day
• Up to 2 outputs can be low-skew
• Can include 8 selectable output frequencies
• Up to 3 reference outputs
• Replaces multiple crystals and oscillators
• Output frequencies up to 200 MHz at 3.3V
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 2 - 50 MHz
• Duty cycle of 45/55
requests for different frequencies to be shipped in 1-3
days. Programming features include a selectable
frequency table and up to 2 low-skew outputs.
Using Phase-Locked-Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace multiple
crystals and oscillators, saving board space and cost.
• Operating voltages of 3.3 V or 5 V
• Advanced, low power CMOS process
Block Diagram
OTP
3
ROM
with PLL
Divider
Values
S2:S0
PLLA
CLK1
Divide
Logic
and
Output
Control
CLK2
CLK3
CLK4
CLK5
PLLB
PLLC
PLLD
Crystal
or clock
input
X1/ICLK
Crystal
Oscillator
X2
PDTS (all outputs and PLLs)
Capacitors are required with a crystal input.
MDS 387 A
1
Revision 050401
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA• 95126 •( 408) 295-9800 • www.icst.com
PRELIMINARY INFORMATION
ICS387
Quad PLL Quick Turn Clock Synthesizer
Pin Assignments
X2
X1/ICLK
1
2
3
4
5
6
7
16
15
14
VDD
S0
S1
PDTS
S2
CLK5
VDD
GND
13
12
VDD
GND
CLK3
CLK4
11
10
9
CLK1
CLK2
8
16 pin TSSOP
Pin Descriptions
Number Name Type Description
1
2
X1/ICLK
S0
XI Crystal connection. Connect to fundamental mode crystal or clock input.
I
I
Select pin 0 for frequency table/chip control. Internal pull-up resistor.
Select pin 1 for frequency table/chip control. Internal pull-up resistor.
Clock output.
3
S1
4
CLK5
VDD
GND
CLK1
CLK2
CLK4
CLK3
GND
VDD
S2
O
P
P
O
O
O
O
P
P
I
5
Connect to +3.3V or +5V. Must be same voltage as pins 12 and 15.
Connect to ground.
6
7
Clock output.
8
Clock output.
9
Clock output.
10
11
12
13
14
15
16
Clock output.
Connect to ground.
Connect to +3.3V or +5V. Must be same voltage as pins 5 and 15.
Select pin 2 for frequency table/chip control. Internal pull-up resistor.
All-chip Power Down when low. Note 1.
Connect to +3.3V or +5V. Must be same voltage as pins 5 and 12.
PDTS
VDD
X2
I
P
XO Crystal connection. Leave unconnected for clock input.
Key: XI, XO = crystal connections, I = input, O = output, P = power supply connection
Note 1: All outputs are internally high impedance with a weak internal pull-down resistor. When PDTS is
active, it is possible to overdrive the output pins for board-level testing.
MDS 387 A
2
Revision 050401
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA• 95126 •( 408) 295-9800 • www.icst.com
PRELIMINARY INFORMATION
ICS387
Quad PLL Quick Turn Clock Synthesizer
Device Configuration
The ICS387 QTClock provides the facility for up to 5 clock outputs. The outputs are derived from either the
reference input or from one of the 4 PLLs. All chip functions are controlled from an OTP ROM which has 3 input
control lines (S2, S1, S0), giving a total of 8 address locations. Each address location gives control of the following:
1) Each output can be turned off individually
2) The internal dividers for each PLL are controlled to generate any required frequency.
3) Each PLL can be turned off (powered down) individually.
4) The output divide and control logic can be configured to bring the appropriate clock to the correct pin.
5) Up to four low skew copies of the same clock can be enabled.
This chip architecture provides the user with unrivaled flexibility. For example, one of the input pins could be used
to control the power of the chip by shutting down PLLs and outputs when not used. The second and third could
be used to change the output clock frequencies.
The specification is complete when the ICS387 QTClock Order Form accompanies this data sheet. The order form
lists the input and CLK actual frequencies, as well as any other available options. This unique configuration is given
a two character alphanumeric programming code (ICS387-xx), which must be specified when referring to samples
or ordering parts.
Frequency Select Table
The ICS387 can be configured so that one PLL provides up to 8 frequency selections. For example, CPU
frequencies of 66.7 MHz, 100.0 MHz, 133.3 MHz, and 166.7 MHz could be included. This information should be
indicated on the Order Form when the ICS387 is initially defined.
External Components / Crystal Selection
The ICS387 requires a 0.01µF decoupling capacitor to be connected between VDD and GND on pins 5 and 6, and
another between pins 12 and 11. These must be connected close to the ICS387 to minimize lead inductance. No
external power supply filtering is required for this device. A 33 W series terminating resistor can be used next to
each CLK pin. For a crystal input, a parallel resonant, fundamental mode crystal should be used. Crystal capacitors
must be connected from each of the pins X1 and X2 to Ground. The value (in pF) of these crystal caps should equal
(C -6pf)*2, where C is the crystal load capacitance in pF. As an example, for a crystal with 16 pF load capacitance,
L
L
each crystal capacitor would be 20 pF [(16 - 6pf)*2 = 20].
For a clock input, connect to X1/ICLK and leave X2 unconnected (no capacitors on either X1 or X2).
MDS 387 A
3
Revision 050401
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA• 95126 •( 408) 295-9800 • www.icst.com
PRELIMINARY INFORMATION
ICS387
Quad PLL Quick Turn Clock Synthesizer
Electrical Specifications
Parameter
Conditions
Minimum Typical Maximum
Units
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
Commercial version
Industrial version
7
VDD+0.5
VDD+0.5
70
V
-0.5
-0.5
0
V
Clock Output
V
Ambient Operating Temperature
Ambient Operating Temperature
Soldering Temperature
Storage temperature
°C
°C
°C
°C
-40
85
Max of 10 seconds
260
-65
150
DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Operating Voltage, VDD
3.13
5.5
(VDD/2)-1
0.8
V
V
Input High Voltage, VIH, ICLK only
Input Low Voltage, VIL, ICLK only
Input High Voltage, VIH
ICLK (Pin 1)
(VDD/2)+1
ICLK (Pin 1)
V
PDTS, S0, S1, S2
PDTS, S0, S1, S2
IOH=-4mA
2
V
Input Low Voltage, VIL
V
Output High Voltage, VOH
Output High Voltage, VOH
Output Low Voltage, VOL
VDD-0.4
2.4
V
IOH=-25mA
V
IOL=25mA
0.4
V
IDD Operating Supply Current, 20 MHz crystaNo Load, 100MHz
20
±70
TBD
TBD
4
mA
mA
kW
W
pF
Short Circuit Current
CLK output
On-Chip Pull-up Resistor, inputs
On-Chip Pull-down Resistor, outputs
Input Capacitance, inputs
AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency
5
2
2
27
50
MHz
MHz
MHz
ns
200
Output Clock Rise Time
0.8 to 2.0V
1
1
Output Clock Fall Time
2.0 to 0.8V
ns
Output Clock Duty Cycle (Note 1)
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Pin to Pin Skew
at VDD/2
45
49 to 51
±TBD
TBD
55
%
Deviation from mean
ps
ps
Low skew outputs
-250
250
20
ps
Power-up time, PDTS goes high until CLK out
8
ms
Note 1: These are typical values. The actual minimum and maximum duty cycle limits are shown on the
ICS387 QTClock Order Form for each programmed version.
MDS 387 A
4
Revision 050401
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA• 95126 •( 408) 295-9800 • www.icst.com
PRELIMINARY INFORMATION
ICS387
Quad PLL Quick Turn Clock Synthesizer
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
16 pin TSSOP
Inches
Millimeters
Symbol Min
Max
0.047
Min
--
Max
A
A1
b
--
1.20
0.15
0.30
0.20
5.10
0.002 0.006 0.05
0.007 0.012 0.19
0.0035 0.008 0.09
0.193 0.201 4.90
E1
E
c
D
e
INDEX
AREA
.0256 BSC
0.65 BSC
6.40 BSC
E
.252 BSC
1
2
E1
L
0.169 0.177 4.30
0.018 0.030 0.45
4.50
0.75
D
A
A1
c
b
L
e
Ordering Information
Part/Order Number
ICS387G-xx
Marking
Package
Shipping
Tubes
Temperature
ICS387G-xx
ICS387G-xx
ICS387G-xxI
ICS387G-xxI
16 pin TSSOP
16 pin TSSOP
16 pin TSSOP
16 pin TSSOP
0 to 70 °C
0 to 70 °C
ICS387G-xxT
ICS387G-xxI
Tape and Reel
Tubes
-40 to 85 °C
-40 to 85 °C
ICS387G-xxIT
Tape and Reel
xx represents a 2 character alphanumeric programming code assigned by the factory, which indicates the output frequencies
on all CLKs and other features. All samples are shipped with an ICS387 order form describing the characteristics of the device.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc.
(ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which
would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other
extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to
change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support
devices or critical medical instruments.
QTClock is a trademark of ICS
MDS 387 A
5
Revision 050401
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA• 95126 •( 408) 295-9800 • www.icst.com
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