ICS650R-14LFT [IDT]
Clock Generator, 133.33MHz, CMOS, PDSO20, 0.150 INCH, SSOP-20;
| 型号： | ICS650R-14LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 133.33MHz, CMOS, PDSO20, 0.150 INCH, SSOP-20 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总7页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
NETWORKING SYSTEM CLOCK
ICS650-14
Description
Features
The ICS650-14 is a low-cost, low-jitter, high-performance
clock synthesizer customized for networking systems
applications. Using analog/digital Phase-Locked Loop (PLL)
techniques, the device accepts a 25 MHz clock or
• Packaged in 20-pin (150 mil) SSOP (QSOP)
• 25 MHz fundamental crystal clock or clock input
• One fixed output clock of 25 MHz
fundamental mode crystal input to produce multiple output
clocks of one fixed 25 MHz, a four (plus one) frequency
selectable bank, and two frequency selectable clocks. All
output clocks are frequency locked together. All of the
ICS650-14 outputs have zero ppm synthesis error.
• One bank of four frequency selectable output clocks
• Three frequency selectable clocks outputs
• Zero ppm synthesis error in all clocks
• Ideal for networking systems
• Full CMOS output swing
• Advanced, low-power sub-micron CMOS process
• Operating voltage of 3.3 V or 5 V
• Industrial temperature range available
• Pb-free, RoHS compliant package
Block Diagram
VDD
2
2
4
SELA 0:1
CLKA 1:4
2
SELB 0:1
Clock
CLKA5
Synthesis and
Control
SELC
Circuitry
CLKB
CLKC
Crystal
Buffer/
Crystal
X1/ICLK
25 MHz
Crystal or Clock
25 MHz
Oscillator
X2
2
OE (all outputs)
Optional crystal capacitors are shown and may be
required for tuning of initial accuracy (determined
once per board)
GND
IDT™ / ICS™ NETWORKING SYSTEM CLOCK
1
ICS650-14
REV H 051310
ICS650-14
NETWORKING SYSTEM CLOCK
CLOCK SYNTHESIZER
Table 1
Pin Assignment
SELA1
SELA0
CLKA1:4
33.33
50
CLKA5
66.66
75
1
2
20
19
18
17
16
15
14
13
12
11
SELC
SELA0
CLKA2
CLKA3
VDD
SELB0
X2
0
0
0
M
1
3
X1/ICLK
VDD
4
0
66.67
100
133.33
33.33
83.33
125
SELB1
GND
5
M
M
M
1
0
6
SELA1
GND
M
1
33.33
50
CLKB
7
CLKC
CLKA5
25M
8
CLKA4
CLKA1
OE
0
33.33
25
100
9
10
1
M
1
75
1
66.67
100
20-pin (150 mil) SSOP
Table 3
Table 2
SELB1
SELC
CLKC
CLKB/4
62.5
SELB0
CLKB
0
M
1
0
0
0
1
1
1
0
M
1
30
27
125
48
0
83.33
19.44
80
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
M
1
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
SELB0
X2
TI
Select pin for CLKB. See table 2.
XO
Crystal connection. Connect to a 25 MHz crystal or leave unconnected for clock
input.
3
4
X1/ICLK
VDD
XI
P
Crystal connection. Connect to a 25 MHz fundamental crystal or clock input.
Connect to 3.3 V or 5 V. Must be same as other VDDs.
Select pin for CLK B. See table 2.
5
SELB1
GND
I(Pu)
P
6
Connect to ground.
7
CLKB
CLKC
CLKA5
25M
O
Selectable clock output. See table 2.
8
O
Selectable clock output. See table 3.
9
O
Selectable clock output. See table 1.
10
11
12
Ou
I(Pu)
O
25 MHz clock output.
OE
Output enable. Tri-states all outputs when low. Internal pull-up.
Selectable clock output. See table 1.
CLKA1
IDT™ / ICS™ NETWORKING SYSTEM CLOCK
2
ICS650-14
REV H 051310
ICS650-14
NETWORKING SYSTEM CLOCK
CLOCK SYNTHESIZER
Pin
Number
Pin
Name
Pin
Type
Pin Description
13
14
15
16
17
18
19
20
CLKA4
GND
O
P
Selectable clock output. See table 1.
Connect to ground.
SELA1
VDD
TI
P
Select pin for CLKA1:4 and CLKA5 outputs. See table 1.
Connect to 3.3 Vor 5 V. Must be same as other VDDs.
Selectable clock output. See table 1.
CLKA3
CLKA2
SELA0
SELC
O
O
TI
TI
Selectable clock output. See table 1.
Select pin for CLKA1:4 and CLKA5 outputs. See table 1.
Select pin for CLKC output. See table 3.
Key: XI, XO = crystal connections; I = input; I(Pu) = input with pull-up; O = output; P = power supply connection; TI
= tri-level input
External Components
The ICS650-14 requires a minimum number of external
components for proper operation.
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should
be connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
Decoupling Capacitor
Decoupling capacitors of 0.01µF must be connected
between each VDD and GND (pins 4 and 6, pins 16 and 14),
as close to the device as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Crystal caps (pF) = (C - 6) x 2
L
In the equation, C is the crystal load capacitance. For a
L
crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2]
capacitors should be used.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ωresistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
IDT™ / ICS™ NETWORKING SYSTEM CLOCK
3
ICS650-14
REV H 051310
ICS650-14
NETWORKING SYSTEM CLOCK
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-14. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD (referecned to GND)
Inputs and Outputs (referecned to GND)
Ambient Operating Temperature
7 V
-0.5 V to VDD+0.5 V
0 to +70° C
Ambient Operating Temperature (industrial “I” version)
Soldering Temperature (max. of 20 seconds)
Storage Temperature
-40 to 85° C
-65 to +150° C
260°C
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature 0 to +70°C
Parameter
Symbol
Conditions
Min.
3.0
Typ.
Max.
Units
V
Operating Voltage
VDD
5.5
Input High Voltage (X1 pin only)
Input Low Voltage (X1 pin only)
Input High Voltage (SEL pins only)
Input Low Voltage (SEL pins only)
Input High Voltage (OE pin only)
Input Low Voltage (OE pin only)
Output High Voltage
V
Clock input
Clock input
VDD/2+1
V
IH
V
VDD/2-1
0.5
V
IL
V
VDD-0.5
2.0
V
IH
V
V
IL
V
V
IH
V
0.8
V
IL
V
V
I
I
I
= -12 mA
= -8 mA
= 12 mA
2.4
V
OH
OH
OH
OH
OL
Output High Voltage (CMOS level)
Output Low Voltage
VDD-0.4
V
V
0.4
V
OL
DD
Operating Supply Current
I
No load, VDD = 3.3 V
Each output
32
50
mA
mA
Short Circuit Current
IDT™ / ICS™ NETWORKING SYSTEM CLOCK
4
ICS650-14
REV H 051310
ICS650-14
NETWORKING SYSTEM CLOCK
CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature 0 to +70° C
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Input Frequency
25
MHz
ns
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Frequency Error
t
0.8 to 2.0 V
1.5
1.5
55
0
OR
t
2.0 to 0.8 V
At VDD/2
ns
OF
45
50
%
All clocks
ppm
ps
Absolute Jitter, short term
CLKB = 27M
CLKC = 62.5M
Other Clocks
250
300
350
ps
ps
Marking Diagram (ICS650R-14ILF)
Marking Diagram (ICS650R-14LF)
11
11
20
20
650R-14ILF
######
YYWW
650R-14LF
######
YYWW
1
10
1
10
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. ”LF” denotes Pb-free, RoHS compliant package.
4. “I” denotes industrial grade device.
5. Bottom marking: country of origin.
IDT™ / ICS™ NETWORKING SYSTEM CLOCK
5
ICS650-14
REV H 051310
ICS650-14
NETWORKING SYSTEM CLOCK
CLOCK SYNTHESIZER
Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
20
Symbol
Min
Max
1.75
0.25
1.50
0.30
0.25
8.75
6.20
4.00
Min
Max
A
A1
A2
b
1.35
0.10
--
0.20
0.18
8.55
5.80
3.80
0.053
0.004
--
0.008
0.007
0.337
0.228
0.150
0.069
0.010
0.059
0.012
0.010
0.344
0.244
0.157
E1
E
INDEX
AREA
c
D
E
E1
e
1 2
0.635 Basic
0.025 Basic
D
L
0.40
1.27
0.016
0.050
α
0°
8°
0°
8°
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
see page 5
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
-40 to 85° C
-40 to 85° C
650R-14LF
650R-14LFT
650R-14ILF
650R-14ILFT
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
Tape and Reel
Tubes
Tape and Reel
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ NETWORKING SYSTEM CLOCK
6
ICS650-14
REV H 051310
ICS650-14
NETWORKING SYSTEM CLOCK
CLOCK SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
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