ICS83940DYILF [IDT]
Low Skew Clock Driver, 83940 Series, 18 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32;
| 型号： | ICS83940DYILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 83940 Series, 18 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总19页 (文件大小：717K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to18
LVPECL-to-LVCMOS/LVTTL Fanout Buffer
ICS83940DI
DATA SHEET
General Description
Features
The ICS83940DI is a low skew, 1-to-18 LVPECL- to-LVCMOS/LVTTL
Fanout Buffer. The ICS83940DI has two selectable clock inputs. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The
low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω
series or parallel terminated transmission lines.
• Eighteen LVCMOS/LVTTL outputs
• Selectable LVCMOS_CLK or LVPECL clock inputs
• PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
• LVCMOS_CLK supports the following input types: LVCMOS or
LVTTL
The ICS83940DI is characterized at full 3.3V and 2.5V or mixed 3.3V
core, 2.5V output operating supply modes. Guaranteed output and
part-to-part skew characteristics make the ICS83940DI ideal for
those clock distribution applications demanding well defined
performance and repeatability.
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Part-to-part skew: 750ps (maximum)
• Operating supply modes:
• Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pulldown
CLK_SEL
Pulldown
PCLK
0
Pullup/Pulldown
nPCLK
18
Q0:Q17
Pulldown
LVCMOS_CLK
1
Pin Assignments
32 31 30 29 28 27 26 25
32 31 30 29 28 27 26 25
1
2
3
4
5
7
8
GND
Q6
Q7
Q8
24
23
22
21
20
GND
GND
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q6
GND
Q7
LVCMOS_CLK
LVCMOS_CLK
CLK_SEL
PCLK
Q8
ICS3940DI
ICS83940DI
VDD
Q9
CLK_SEL
PCLK
VDD
Q9
nPCLK
Q10
Q11
GND
nPCLK
Q10
Q11
GND
19
18
17
VDD
VDDO
VDO
9
10 11 12 13 14 15 16
9
10 11 12 13 14 15 16
32 Lead VFQFN
32-Lead LQFP
5mm x 5mm x 0.925mm package body
7mm x 7mm x 1.4mm package body
Y Package
Top View
K Package
Top View
ICS83940DYI REVISION C SEPTEMBER 7, 2010
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©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2, 12, 17, 25
3
Name
GND
Type
Description
Power supply ground.
Power
Input
LVCMOS_CLK
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Clock select input. When HIGH, selects LVCMOS_CLK input.
Pulldown When LOW, selects PCLK, nPCLK inputs.
LVCMOS / LVTTL interface levels.
4
CLK_SEL
Input
5
6
PCLK
Input
Input
Pulldown Non-inverting differential LVPECL clock input.
Pullup/
nPCLK
Inverting differential LVPECL clock input. VDD/2 default when left floating.
Pulldown
7, 21
VDD
Power
Power
Power supply pin.
Output supply pins.
8, 16, 29
VDDO
9, 10, 11,
13, 14, 15,
18, 19, 20,
22, 23, 24,
26, 27, 28,
30, 31, 32
Q17, Q16, Q15,
Q14, Q13, Q12,
Q11, Q10, Q9,
Q8, Q7, Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
Power Dissipation Capacitance
(per output)
CPD
6
pF
ROUT
Output Impedance
18
28
Ω
ICS83940DYI REVISION C SEPTEMBER 7, 2010
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©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Function Tables
Table 3A. Clock Select Function Table
Control Input
Clock
CLK_SEL
PCLK, nPCLK
Selected
LVCMOS_CLK
De-selected
Selected
0
1
De-selected
Table 3B. Clock Input Function Table
Inputs
Outputs
CLK_SEL
LVCMOS_CLK
PCLK
nPCLK
Q[0:17]
LOW
Input to Output Mode
Polarity
0
0
0
0
0
0
1
1
–
–
–
–
–
–
0
1
0
1
Differential to Single-Ended
Differential to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
1
Biased; NOTE 1
HIGH
HIGH
LOW
Biased; NOTE 1
0
1
–
–
Biased; NOTE 1
Inverting
–
–
LOW
Non-Inverting
Non-Inverting
HIGH
NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels.
ICS83940DYI REVISION C SEPTEMBER 7, 2010
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ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
3.6V
-0.3V to VDD + 0.3V
-0.3V to VDDO + 0.3V
20mA
Outputs, VO
Input Current, IIN
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. DC Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VDD
Units
V
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
2.4
Input Low Voltage
Input Current
0.8
V
IIN
200
µA
V
VOH
VOL
Output High Voltage
Output Low Voltage
IOH = -20mA
IOL = 20mA
2.4
0.5
V
Peak-to-Peak Input Voltage;
NOTE 1
VPP
PCLK, nPCLK
500
1000
mV
Common Mode Input Voltage; PCLK, nPCLK
NOTE 1, 2
VCMR
IDD
VDD – 1.45
VDD – 0.6
25
V
Power Supply Current
mA
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
Table 4B. DC Characteristics, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VDD
Units
V
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
2.4
Input Low Voltage
Input Current
0.8
V
IIN
200
µA
V
VOH
VOL
Output High Voltage
Output Low Voltage
IOH = -20mA
IOL = 20mA
1.8
0.5
V
Peak-to-Peak Input Voltage;
NOTE 1
VPP
PCLK, nPCLK
300
1000
mV
Common Mode Input Voltage; PCLK, nPCLK
NOTE 1, 2
VCMR
IDD
VDD – 1.4
VDD – 0.6
25
V
Power Supply Current
mA
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
ICS83940DYI REVISION C SEPTEMBER 7, 2010
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©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 4C. DC Characteristics, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VDD
Units
V
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
2
Input Low Voltage
Input Current
0.8
V
IIN
200
µA
V
VOH
VOL
Output High Voltage
Output Low Voltage
IOH = -12mA
IOL = 12mA
1.8
0.5
V
Peak-to-Peak Input Voltage;
NOTE 1
VPP
PCLK, nPCLK
300
1000
mV
Common Mode Input Voltage; PCLK, nPCLK
NOTE 1, 2
VCMR
IDD
VDD – 1.4
VDD – 0.6
25
V
Power Supply Current
mA
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
ICS83940DYI REVISION C SEPTEMBER 7, 2010
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©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
250
3.0
3.0
3.3
3.2
150
150
1.4
1.2
1.7
1.4
850
750
1.1
55
MHz
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ps
ps
ns
ꢀ
PCLK, nPCLK; NOTE 1, 5
LVCMOS_CLK; NOTE 2, 5
PCLK, nPCLK; NOTE 1, 5
LVCMOS_CLK; NOTE 2, 5
PCLK, nPCLK
ƒ ≤ 150MHz
ƒ ≤ 150MHz
ƒ > 150MHz
ƒ > 150MHz
1.6
1.8
1.6
1.8
Propagation
Delay
tPLH
Propagation
Delay
Output Skew;
NOTE 3, 5
Measured on the Rising Edge
@ VDDO/2
tsk(o)
LVCMOS_CLK
PCLK, nPCLK
ƒ ≤ 150MHz
ƒ ≤ 150MHz
ƒ > 150MHz
ƒ > 150MHz
Part-to-PartSkew;
NOTE 6
LVCMOS_CLK
PCLK, nPCLK
Part-to-PartSkew;
NOTE 6
tsk(pp)
LVCMOS_CLK
PCLK, nPCLK
Part-to-PartSkew;
NOTE 4, 5
Measured on the Rising Edge
@ VDDO/2
LVCMOS_CLK
tR / tF
odc
Output Rise/Fall Time
0.5V to 2.4V
ƒ < 134MHz
0.3
45
40
50
50
Output Duty Cycle
134MHz ≤ ƒ ≤ 250MHz
60
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at VDDO/2.
ICS83940DYI REVISION C SEPTEMBER 7, 2010
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©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 5B. AC Characteristics, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
250
3.2
3.0
3.4
3.3
150
150
1.5
1.3
1.8
1.5
850
750
1.2
55
MHz
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ps
ps
ns
ꢀ
PCLK, nPCLK; NOTE 1, 5
LVCMOS_CLK; NOTE 2, 5
PCLK, nPCLK; NOTE 1, 5
LVCMOS_CLK; NOTE 2, 5
PCLK, nPCLK
ƒ ≤ 150MHz
ƒ ≤ 150MHz
ƒ > 150MHz
ƒ > 150MHz
1.7
1.7
1.6
1.8
Propagation
Delay
tPLH
Propagation
Delay
Output Skew;
NOTE 3, 5
Measured on the Rising Edge
@ VDDO/2
tsk(o)
LVCMOS_CLK
PCLK, nPCLK
ƒ ≤ 150MHz
ƒ ≤ 150MHz
ƒ > 150MHz
ƒ > 150MHz
Part-to-PartSkew;
NOTE 6
LVCMOS_CLK
PCLK, nPCLK
Part-to-PartSkew;
NOTE 6
tsk(pp)
LVCMOS_CLK
PCLK, nPCLK
Part-to-PartSkew;
NOTE 4, 5
Measured on the Rising Edge
@ VDDO/2
LVCMOS_CLK
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
0.5V to 1.8V
ƒ < 134MHz
0.3
45
50
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at VDDO/2.
ICS83940DYI REVISION C SEPTEMBER 7, 2010
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©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 5C. AC Characteristics, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
200
3.8
3.2
3.7
3.6
200
200
2.6
1.7
2.2
1.7
1.2
1.0
1.2
55
MHz
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ꢀ
PCLK, nPCLK; NOTE 1, 5
LVCMOS_CLK; NOTE 2, 5
PCLK, nPCLK; NOTE 1, 5
LVCMOS_CLK; NOTE 2, 5
PCLK, nPCLK
ƒ ≤ 150MHz
ƒ ≤ 150MHz
ƒ > 150MHz
ƒ > 150MHz
1.2
1.5
1.5
2.0
Propagation
Delay
tPLH
Propagation
Delay
Output Skew;
NOTE 3, 5
Measured on the Rising Edge
@ VDDO/2
tsk(o)
LVCMOS_CLK
PCLK, nPCLK
ƒ ≤ 150MHz
ƒ ≤ 150MHz
ƒ > 150MHz
ƒ > 150MHz
Part-to-PartSkew;
NOTE 6
LVCMOS_CLK
PCLK, nPCLK
Part-to-PartSkew;
NOTE 6
tsk(pp)
LVCMOS_CLK
PCLK, nPCLK
Part-to-PartSkew;
NOTE 4, 5
Measured on the Rising Edge
@ VDDO/2
LVCMOS_CLK
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
0.5V to 1.8V
ƒ < 134MHz
0.3
45
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at VDDO/2.
ICS83940DYI REVISION C SEPTEMBER 7, 2010
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©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Parameter Measurement Information
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
V
DD,
V
V
DD,
V
DDO
DDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
2.05V 5ꢀ
1.25V 5ꢀ
V
DD
SCOPE
V
DD
nPCLK
VPP
VCMR
Cross Points
V
DDO
Qx
PCLK
GND
GND
LVCMOS
-1.25V 5ꢀ
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
Differential Input Level
Part 1
VDDO
VDDO
Qx
Qy
2
Qx
Qy
2
Part 2
VDDO
2
VDDO
2
tsk(o)
tsk(pp)
Part-to-Part Skew
Output Skew
ICS83940DYI REVISION C SEPTEMBER 7, 2010
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©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Parameter Measurement Information, continued
1.8V
tF
2.4V
tF
1.8V
tR
2.4V
tR
0.5V
0.5V
0.5V
0.5V
Q0:Q17
Q0:Q17
3.3V Output Rise/Fall Time
2.5V Output Rise/Fall Time
nPCLK
PCLK
VDD
VDDO
2
Q0:Q17
tPW
tPERIOD
2
LVCMOS_CLK
VDDO
2
tPW
Q0:Q17
x 100ꢀ
odc =
tpLH
tPERIOD
Output Duty Cycle/Pulse Width/Period
Propagation Delay
ICS83940DYI REVISION C SEPTEMBER 7, 2010
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©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VDD/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VDD = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VDD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS83940DYI REVISION C SEPTEMBER 7, 2010
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©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both differential signals must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
3.3V
R1
R2
50Ω
50Ω
Zo = 50Ω
Zo = 50Ω
PCLK
PCLK
R1
100Ω
nPCLK
Zo = 50Ω
nPCLK
LVPECL
LVPECL
Input
CML Built-In Pullup
CML
Input
Figure 2A. PCLK/nPCLK Input
Figure 2B. PCLK/nPCLK Input
Driven by a CML Driver
Driven by a Built-In Pullup CML Driver
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125Ω
R4
125Ω
3.3V
R3
84
R4
84
Zo = 50Ω
Zo = 50Ω
C1
C2
Zo = 50Ω
Zo = 50Ω
3.3V LVPECL
PCLK
PCLK
nPCLK
nPCLK
LVPECL
Input
LVPECL
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84Ω
R2
84Ω
Figure 2C. PCLK/nPCLK Input
Figure 2D. PCLK/nPCLK Input Driven by
a 3.3V LVPECL Driver with AC Couple
Driven by a 3.3V LVPECL Driver
2.5V
3.3V
2.5V
R3
R4
120
120
Zo = 60Ω
Zo = 60Ω
PCLK
nPCLK
LVPECL
Input
SSTL
R1
120
R2
120
Figure 2E. PCLK/nPCLK Input
Driven by an SSTL Driver
ICS83940DYI REVISION C SEPTEMBER 7, 2010
12
©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 3. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
PCLK/nPCLK Inputs
LVCMOS Outputs
For applications not requiring the use of the differential input, both
PCLK and nPCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from PCLK to
ground.
All unused LVCMOS output can be left floating. There should be no
trace attached.
LVCMOS_CLK Input
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the LVCMOS_CLK input to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
ICS83940DYI REVISION C SEPTEMBER 7, 2010
13
©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Reliability Information
Table 6A. θJA vs. Air Flow Table for a 32 Lead LQFP
θJA vs. Air Flow
Linear Feet per Minute
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
Table 6B. θJA vs. Air Flow Table for a 32 Lead VFQFN
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
40.2°C/W
35.1°C/W
31.5°C/W
Transistor Count
The transistor count for ICS83940DI is: 820
ICS83940DYI REVISION C SEPTEMBER 7, 2010
14
©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Package Outline and Package Dimensions
Package Outline - Y Suffix for 32 Lead LQFP
Table 7A. Package Dimensions for 32 Lead LQFP
JEDEC Variation: ABC - HD
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
1.60
0.15
1.45
0.45
0.20
A1
0.05
1.35
0.30
0.09
0.10
1.40
0.37
A2
b
c
D & E
D1 & E1
D2 & E2
e
9.00 Basic
7.00 Basic
5.60 Ref.
0.80 Basic
0.60
L
0.45
0°
0.75
7°
θ
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
ICS83940DYI REVISION C SEPTEMBER 7, 2010
15
©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
N & N
Even
Seating Plane
(N -1)x e
(Ref.)
A1
IndexArea
L
A3
E2
e
2
N
N
(Ty p.)
If N & N
are Even
Anvil
1
Singulation
2
(N -1)x e
(Re f.)
E2
2
TopView
D
b
(Ref.)e
N &N
Odd
Thermal
Base
A
D2
2
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
Bottom View w/Type A ID
Bottom View TypB ID
Bottom View w/Type C ID
4
2
1
2
1
2
1
CHAMFER
RADIUS
N N-1
4
N N-1
DD
N N-1
4
4
There are 3 methods of indicating pin 1 corner
at the back of the VFQFN package are:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type B: Dummy pad between pin 1 and N.
4
AA
4
3. Type C: Mouse bite on the paddle (near pin 1)
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 7B.
Table 7B. Package Dimensions
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
0
1.00
0.05
A1
A3
0.25 Ref.
0.25
b
ND & NE
D & E
D2 & E2
e
0.18
0.30
8
5.00 Basic
3.0
3.3
0.50 Basic
0.40
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
ICS83940DYI REVISION C SEPTEMBER 7, 2010
16
©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Ordering Information
Table 8. Ordering Information
Part/Order Number
83940DYI
Marking
Package
32 Lead LQFP
32 Lead LQFP
Shipping Packaging
Tray
1000 Tape & Reel
Tray
1000 Tape & Reel
Tray
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS83940DYI
ICS83940DYI
ICS83940DYIL
ICS83940DYIL
ICS83940DIL
ICS83940DIL
83940DYIT
83940DYILF
83940DYILFT
83940DKILF
83940DKILFT
“Lead-Free” 32 Lead LQFP
“Lead-Free” 32 Lead LQFP
“LP
“LeeaaRdd--FFree” 32 Lead VFQFN
O
ree
P
” 32
O
Le
S
ad
E
VF
D
QFN
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS83940DYI REVISION C SEPTEMBER 7, 2010
17
©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
T2
2
Pin Characteristics table - changed ROUT 25Ω maximum to 28Ω maximum.
Delete RPULLUP row.
7
3.3V Output Load AC Test Circuit diagram - corrected GND equation to read
A
12/12/02
-1.65V... from -1.165V...
Added LVTTL to title.
Updated format.
1
9
Features Section - added Lead-Free bullet.
Application Information Section - added Recommendations for Unused Input and
Output Pins.
A
A
B
11/27/06
2/21/07
8/13/09
10
13
Application Information Section - added LVPECL Clock Input Interface.
Ordering Information Table - added Lead-Free part number, marking, and note.
Updated datasheet format.
T8
3
Absolute Maximum Ratings - corrected Storage Temperature from
"-40°C to 125°C" to "-65°C to 150°C".
1
Added 32 Lead VFQFN Pin Assignment.
Added VFQFN Thermal Release Path section.
Added 32 VFQFN Thermal Table.
Added 32 Lead VFQFN Package and Dimensions Table.
Ordering Information Table - added 32 Lead VFQFN ordering information.
Converted datasheet format.
13
14
16
17
T6B
T7B
T8
T2
2
11
16
Pin Characteristics Table - ROUT error, typical spec deleted.
Updated Wiring the Differential Input to Accept Single-Ended Levels.
Updated 32 VFQFN Package Outline.
C
9/7/10
ICS83940DYI REVISION C SEPTEMBER 7, 2010
18
©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
We’ve Got Your Timing Solution
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
San Jose, California 95138
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2010. All rights reserved.
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