ICS840245IAGILF [IDT]
Clock Generator;
| 型号： | ICS840245IAGILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator |
| 文件： | 总11页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS840245I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
• Five LVCMOS outputs, 15Ω typical output impedance
• Crystal oscillator interface
The ICS840245I is a low skew, 1-to-5 LVCMOS/
ICS
LVTTL SATA/SAS Clock Generator and is a
member of the HiPerClocksTM family of high
performance clock solutions from ICS. The
ICS840245I can synthesize 75MHz reference
HiPerClockS™
• Supports the following output frequency: 75MHz
• Output skew: 45ps (typical)
clock frequencies with a 25MHz crystal. Each of the 5 outputs
on the ICS840245I can drive two series terminated 50Ω
transmission lines, effectively making the ICS840245I a 1-to-10
clock generator. An output enable (OE) pin, which controls
only the Q4 output, allows the application to use Q4 as an
optional output (for example, test output pin).The ICS840245I
uses ICS’ 3rd generation low phase noise VCO technology
and can achieve 1ps or lower typical random rms phase
jitter.The ICS840245I is packaged in a 16-pin TSSOP package.
• RMS phase jitter @ 75MHz (900kHz - 7.5MHz):
0.454ps (typical)
• Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
Pullup
1
2
3
4
5
6
7
8
XTAL_OUT
XTAL_IN
VDDA
OE
VDD
GND
PLL_SEL
GND
16
15
14
13
12
11
10
9
VDDO
Q0
Q1
GND
Q2
Q3
PLL_SEL
Q1
Q2
Q3
Q4
0
25MHz
XTAL_IN
Phase
Detector
VCO
600MHz
OSC
1
N = 8
VDDO
Q4
XTAL_OUT
M = 24
(fixed)
ICS840245I
16-LeadTSSOP
4.4mm x 5.0mm x 0.92mm
package body
Pullup
OE
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
840245AGI
www.icst.com/products/hiperclocks.html
REV.A APRIL 28, 2006
1
PRELIMINARY
ICS840245I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1,
2
XTAL_OUT,
XTAL_IN
Input
Power
Input
Crystal oscillator interface.
3
VDDA
Analog supply pin.
Output clock enable pin. When HIGH, Q4 output is enabled. When
LOW, forces Q4 to Hi-Z state. LVCMOS/LVTTL interface levels.
4
OE
Pullup
Pullup
5
VDD
Power
Power
Core supply pin.
6, 8, 13
GND
Power supply ground.
PLL select pin. Selects between PLL and bypass mode. When HIGH,
PLL is enabled. LVCMOS/LVTTL interface levels.
7
PLL_SEL
Input
9, 11, 12,
14, 15
Q4, Q3, Q2,
Q1, Q0
Output
Power
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply pins.
10, 16
VDDO
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
8
pF
pF
kΩ
Ω
CPD
Power Dissipation Capacitance
Input Pullup Resistor
RPULLUP
51
15
TBD
3.3V 5%
2.5V 5%
ROUT
Output Impedance
Ω
TABLE 3. CONTROL FUNCTION TABLE
Control Input
Output
Q0:Q4
Hi-Z
OE
0
1
Active
840245AGI
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REV.A APRIL 28, 2006
2
PRELIMINARY
ICS840245I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
3.3
3.3
41
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.08
3.135
V
mA
mA
mA
IDDA
IDDO
8
36
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
3.3
2.5
40
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.465
3.465
2.625
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.08
2.375
V
mA
mA
mA
IDDA
IDDO
8
27
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
2.5
2.5
38
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.625
2.625
2.625
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.08
2.375
V
mA
mA
mA
IDDA
IDDO
8
27
840245AGI
www.icst.com/products/hiperclocks.html
REV.A APRIL 28, 2006
3
PRELIMINARY
ICS840245I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85C
Symbol Parameter
Test Conditions
VDD = 3.3V
Minimum Typical Maximum Units
2
VDD + 0.3
VDD + 0.3
0.8
V
V
VIH
VIL
Input High Voltage
VDD = 2.5V
1.7
-0.3
-0.3
VDD = 3.3V
V
Input Low Voltage
VDD = 2.5V
0.7
V
IIH
IIL
Input High Current OE, PLL_SEL
Input Low Current OE, PLL_SEL
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
VDDO = 3.3V 5%
5
µA
µA
V
-150
2.6
VOH
Output High Voltage; NOTE 1
V
DDO = 2.5V 5%
1.8
V
VOL
Output Low Voltage; NOTE 1
VDDO = 3.3V or 2.5V 5%
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Fundamental
25
Typical Maximum Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pf parallel resonant crystal.
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
75
45
MHz
ps
tsk(o)
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
tjit(Ø)
Integration Range: 900kHz - 7.5MHz
20% to 80%
0.503
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
475
50
ps
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
840245AGI
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REV.A APRIL 28, 2006
4
PRELIMINARY
ICS840245I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
75
55
MHz
ps
tsk(o)
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
tjit(Ø)
Integration Range: 900kHz - 7.5MHz
20% to 80%
0.494
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
475
50
ps
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6C. AC CHARACTERISTICS, VDD =VDDA =VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
75
45
MHz
ps
tsk(o)
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
tjit(Ø)
Integration Range: 900kHz - 7.5MHz
20% to 80%
0.454
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
475
50
ps
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
840245AGI
www.icst.com/products/hiperclocks.html
REV.A APRIL 28, 2006
5
PRELIMINARY
ICS840245I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 75MHZ @ 3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
75MHz
RMS Phase Jitter (Random)
900kHz to 7.5MHz = 0.503ps (typical)
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 75MHZ @ 2.5V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
75MHz
RMS Phase Jitter (Random)
900kHz to 7.5MHz = 0.454ps (typical)
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
840245AGI
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REV.A APRIL 28, 2006
6
PRELIMINARY
ICS840245I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2.05V 5%
2.05V 5%
1.25V 5%
1.65V 5%
1.65V 5%
SCOPE
SCOPE
VDD,
VDDO
VDD
VDDA
VDDA
Qx
VDDO
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5%
-1.25V 5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V 5%
1.25V 5%
VDDO
SCOPE
VDD,
VDDO
Qx
Qy
2
VDDA
Qx
LVCMOS
VDDO
2
GND
tsk(o)
-1.25V 5%
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Phase Noise Plot
VDDO
2
Q0:Q5
tPW
Phase Noise Mask
tPERIOD
tPW
Offset Frequency
x 100%
odc =
f1
f2
tPERIOD
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
tF
80%
tR
20%
20%
Clock
Outputs
OUTPUT RISE/FALL TIME
840245AGI
www.icst.com/products/hiperclocks.html
REV.A APRIL 28, 2006
7
PRELIMINARY
ICS840245I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS840245I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V or 2.5V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840245I has been characterized with 18pF parallel below were determined using a 25MHz 18pF parallel reso-
resonant crystals. The capacitor values shown in Figure 2 nant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
TBD
X1
18pF Parallel Crystal
XTAL_OUT
C2
TBD
22p
ICS840245I
Figure 2. CRYSTAL INPUt INTERFACE
840245AGI
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REV.A APRIL 28, 2006
8
PRELIMINARY
ICS840245I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840245I is: 1965
840245AGI
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REV.A APRIL 28, 2006
9
PRELIMINARY
ICS840245I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
840245AGI
www.icst.com/products/hiperclocks.html
REV.A APRIL 28, 2006
10
PRELIMINARY
ICS840245I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS840245AGI
ICS840245AGIT
ICS840245AGILF
ICS840245AGILFT
840245AI
840245AI
40245AIL
40245AIL
16 Lead TSSOP
tube
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
16 Lead TSSOP
2500 tape & reel
tube
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
840245AGI
www.icst.com/products/hiperclocks.html
REV.A APRIL 28, 2006
11
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