ICS843241I-04 [IDT]
FEMTOCLOCKS⢠CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR; FEMTOCLOCKSâ ?? ¢ CRYSTAL - TO- 3.3V ， 2.5V LVPECL时钟发生器
| 型号： | ICS843241I-04 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FEMTOCLOCKS⢠CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR |
| 文件： | 总14页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FEMTOCLOCKS™ CRYSTAL-TO-3.3V,
2.5V LVPECL CLOCK GENERATOR
ICS843241I-04
GENERAL DESCRIPTION
FEATURES
The ICS843241I-04 is a Serial ATA (SATA)/Serial
• One differential LVPECL output
ICS
HiPerClockS™
Attached SCSI (SAS) Clock Generator and a
• Crystal oscillator interface, 18pF parallel resonant crystal
(20.833MHz - 28.3MHz)
member of the HiPerClocksTM family of high
performance devices from IDT. For SATA/SAS
applications, a 25MHz crystal is used to produce
150MHz.The ICS843241I-04 is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
• Maximum output frequency: 150MHz
• VCO range: 500MHz - 680MHz
• RMS phase jitter @ 150MHz, using a 25MHz crystal
(12kHz - 20MHz): 1.2ps (typical)
• 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
N Divider
XTAL_IN
VCCA
XTAL_OUT
XTAL_IN
VEE
VCC
Q
1
2
3
4
8
7
6
5
Q
nQ
VCO
Phase
÷4
OSC
500MHz - 680MHz
Detector
nQ
nc
XTAL_OUT
ICS843241I-04
M = ÷24 (fixed)
8-Lead TSSOP
4.4mm x 3.0mm x 0.925mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ 150MHZ, 3.3V, 2.5V LVPECLCLOCK GENERATOR
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PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VCCA
Power
Input
Analog supply pin.
2,
3
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
4
5
VEE
nc
Power
Input
Negative supply pin.
No connect.
6, 7
8
nQ, Q
VCC
Output
Power
Differential clock outputs. LVPECL interface levels.
Core supply pin.
IDT™ / ICS™ 150MHZ, 3.3V, 2.5V LVPECLCLOCK GENERATOR
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PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
DD
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance, θJA 129.5°C/W (0 mps)
Storage Temperature, T -65°C to 150°C
STG
TABLE 2A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
VCCA
ICC
Core Supply Voltage
3.135
3.3
3.3
60
3.465
VCC
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
VCC – 0.10
V
mA
mA
ICCA
10
TABLE 2B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical Maximum Units
VCC
VCCA
ICC
Core Supply Voltage
2.5
2.5
60
2.625
VCC
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
VCC – 0.10
V
mA
mA
ICCA
10
TABLE 2C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC = 3.3V
2
VCC + 0.3
VCC + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
V
CC = 2.5V
VCC = 3.3V
CC = 2.5V
1.7
-0.3
-0.3
Input Low Voltage
V
0.7
IDT™ / ICS™ 150MHZ, 3.3V, 2.5V LVPECLCLOCK GENERATOR
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PRELIMINARY
TABLE 2D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 2E. LVPECL DC CHARACTERISTICS, VCC = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.4
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 0.9
VCC - 1.5
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 3. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
20.833
Typical Maximum Units
Fundamental
Mode of Oscillation
Frequency
28.3
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 4A. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
150
MHz
RMS Phase Jitter ( Random);
NOTE 1
150MHz @ Integration Range:
12kHz - 20MHz
tjit(Ø)
1.2
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
50
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plot following this section.
TABLE 4B. AC CHARACTERISTICS, VCC = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
150
MHz
RMS Phase Jitter ( Random);
NOTE 1
150MHz @ Integration Range:
12kHz - 20MHz
tjit(Ø)
1.42
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
50
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plot following this section.
IDT™ / ICS™ 150MHZ, 3.3V, 2.5V LVPECLCLOCK GENERATOR
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PRELIMINARY
TYPICAL PHASE NOISE AT 150MHZ (3.3V)
SATA/SAS Jitter Filter
150MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 1.2ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding a
SATA/SAS Filter to raw data
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 150MHZ (2.5V)
SATA/SAS Jitter Filter
150MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 1.42ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding a
SATA/SAS Filter to raw data
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ 150MHZ, 3.3V, 2.5V LVPECLCLOCK GENERATOR
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PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
2V
2V
2V
SCOPE
SCOPE
VCC
VCC
Qx
Qx
VCCA
VCCA
LVPECL
LVPECL
nQx
nQx
VEE
VEE
-0.5V 0.125V
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
nQ
nQ
80ꢀ
tF
80ꢀ
Q
VSWING
20ꢀ
tPW
tPERIOD
20ꢀ
Q
tR
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Phase Noise Plot
Phase Noise Mask
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
IDT™ / ICS™ 150MHZ, 3.3V, 2.5V LVPECLCLOCK GENERATOR
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PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS843241I-04
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and VCCA should
be individually connected to the power supply plane through vias,
and 0.01µF bypass capacitors should be used for each pin. Fig-
ure 1 illustrates this for a generic V pin and also shows that
VCCA requires that an additional10Ω CrCesistor along with a 10µF
bypass capacitor be connected to the VCCA pin.
3.3V or 2.5V
VCC
.01μF
10Ω
VCCA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843241I-04 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
XTAL_IN
C1
33p
X1
18pF Parallel Crystal
XTAL_OUT
C2
33p
FIGURE 2. CRYSTAL INPUt INTERFACE
IDT™ / ICS™ 150MHZ, 3.3V, 2.5V LVPECLCLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO- 3.3V, 2.5V LVPECL CLOCK GENERATOR
PRELIMINARY
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance.In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω.This can also be accomplished by removing
R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise.This configuration requires that the output
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_I N
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are rec-
ommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal dis-
tortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board design-
ers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ 150MHZ, 3.3V, 2.5V LVPECLCLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO- 3.3V, 2.5V LVPECL CLOCK GENERATOR
PRELIMINARY
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to V - 2V. For V = 2.5V, the V - 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination
is shown in Figure 5C.
CC
CC
CC
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
R1
R3
250
250
+
Zo = 50 Ohm
Zo = 50 Ohm
+
-
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
IDT™ / ICS™ 150MHZ, 3.3V, 2.5V LVPECLCLOCK GENERATOR
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843241I-04.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843241I-04 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 60mA = 207.9mW
MAX
CC_MAX
EE_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
Total Power
(3.465V, with all outputs switching) = 207.9mW + 30mW = 237.9mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
= Junction-to-Ambient Thermal Resistance
JA
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used. Assuming no
JA
air flow and a multi-layer board, the appropriate value is 129.5°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.238W * 129.5°C/W = 115.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE θ FOR 8-PIN TSSOP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
129.5°C/W
125.5°C/W
123.5°C/W
IDT™ / ICS™ 150MHZ, 3.3V, 2.5V LVPECLCLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO- 3.3V, 2.5V LVPECL CLOCK GENERATOR
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V – 2V.
CC
•
•
For logic high, V = V
= V
– 0.9V
OUT
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
– V
CC_MAX
For logic low, V = V
= V
– 1.7V
CC_MAX
OUT
OL_MAX
)
= 1.7V
OL_MAX
(V
– V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
– 2V))/R ] * (V
– V
) = [(2V - (V
– V
– V
/R ] * (V
– V
) =
OH_MAX
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
L
L
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
– 2V))/R ] * (V
– V
) = [(2V – (V
/R ] * (V
– V ) =
OL_MAX
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
L
L
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ 150MHZ, 3.3V, 2.5V LVPECLCLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO- 3.3V, 2.5V LVPECL CLOCK GENERATOR
PRELIMINARY
RELIABILITY INFORMATION
TABLE 6. θ VS. AIR FLOW TABLE FOR 8 LEAD TSSOP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
123.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
129.5°C/W
125.5°C/W
TRANSISTOR COUNT
The transistor count for ICS843241I-04 is: 1732
PACKAGE OUTLINE AND DIMENSIONS
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
E1
e
4.30
4.50
0.65 BASIC
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ 150MHZ, 3.3V, 2.5V LVPECLCLOCK GENERATOR
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PRELIMINARY
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS843241AGI-04
Marking
1AI04
1AI04
TBD
Package
Shipping Packaging
tube
Temperature
8 Lead TSSOP
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS843241AGI-04T
ICS843241AGI-04LF
ICS843241AGI-04LFT
8 Lead TSSOP
2500 tape & reel
tube
8 Lead "Lead-Free" TSSOP
8 Lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 150MHZ, 3.3V, 2.5V LVPECLCLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO- 3.3V, 2.5V LVPECL CLOCK GENERATOR
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
netcom@idt.com
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
+480-763-2056
www.IDT.com/go/contactIDT
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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