ICS84329BV-01LF [IDT]
Clock Generator, 700MHz, PQCC28, 11.60 X 11.40 MM, 4.10 MM HEIGHT, PLASTIC, MS-018, LCC-28;
| 型号： | ICS84329BV-01LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 700MHz, PQCC28, 11.60 X 11.40 MM, 4.10 MM HEIGHT, PLASTIC, MS-018, LCC-28 时钟 外围集成电路 晶体 |
| 文件： | 总21页 (文件大小：773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
700MHZ, LOW JITTER, CRYSTAL-TO-
ICS84329B-01
3.3V LVPECL FREQUENCY SYNTHESIZER
General Description
Features
The ICS84329B-01 is a general purpose, single
• Fully integrated PLL, no external loop filter requirements
• One differential 3.3V LVPECL output pair
• Crystal oscillator interface
S
IC
output high frequency synthesizer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from IDT. The VCO operates at a
frequency range of 250MHz to 700MHz. The VCO
HiPerClockS™
• Output frequency range: 31.25MHz – 700MHz
• VCO range: 250MHz – 700MHz
frequency is programmed in steps equal to the value of the crystal
frequency divided by 16. The VCO and output frequency can be
programmed using the serial or parallel interfaces to the
configuration logic. The output can be configured to divide the
VCO frequency by 1, 2, 4, and 8. Output frequency steps as small
as 125kHz to 1MHz can be achieved using a 16MHz crystal
depending on the output dividers.
• Parallel interface for programming counter and output dividers
during power-up
• Serial 3 wire interface
• RMS period jitter: 5.5ps (maximum)
• Cycle-to-cycle jitter: 35ps (maximum)
• 3.3V supply voltage
Pin Assignments
• 0°C to 70°C ambient operating temperature
ICS84329B-01
28 Lead SOIC
M0
M1
M2
M3
M4
M5
M6
M7
M8
N0
N1
VEE
TEST
1
2
3
4
5
6
7
8
28 nP_LOAD
27
VCC
26 XTAL_OUT
25 XTAL_IN
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
7.5mm x 18.05mm x 2.25mm
package body
M Package
Top View
nc
nc
VCCA
S_LOAD
S_DATA
S_CLOCK
VCC
FOUT
nFOUT
VEE
24
23
22
21
20
19
18
17
16
15
9
10
11
12
13
VCC 14
Block Diagram
25 24 23 22 21 20 19
XTAL_IN
OSC
26
27
28
1
N1
17 N0
S_CLOCK
18
XTAL_OUT
S_DATA
S_LOAD
M8
M7
M6
16
15
14
13
÷16
VCCA
nc
2
PLL
nc
M5
M4
3
PHASEDETECTOR
÷M
÷1
÷2
÷4
÷8
XTAL_IN
4
12
5
6
7
8
9
10 11
1
0
FOUT
nFOUT
VCO
Pulldown
Pulldown
Pulldown
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
ICS84329B-01
28 Lead PLCC
11.6mm x 11.4mm x 4.1mm
package body
V Package
CONFIGURATION
INTERFACE
LOGIC
TEST
Pullup
Pullup
Pullup
M0:M8
N0:N1
Top View
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 16MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 6, NOTE 1.
nP_LOAD input is LOW. The data on inputs M0 through M8 and N0
through N1 is passed directly to the M divider and N output divider.
On the LOW-to-HIGH transition of the nP_LOAD input, the data is
latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs. The TEST
output is Mode 000 (shift register out) when operating in the
parallel input mode. The relationship between the VCO frequency,
the crystal frequency and the M divider is defined as follows:
fVCO = fXTAL x M
The ICS84329B-01 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
parallel resonant, fundamental crystal is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16 prior
to the phase detector. With a 16MHz crystal this provides a 1MHz
reference frequency. The VCO of the PLL operates over a range
of 250MHz to 700MHz. The output of the M divider is also applied
to the phase detector.
16
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock are defined as
250 ≤ M ≤ 511. The frequency out is defined as follows:
fout = fVCO = fXTAL x M
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency ÷ 16 by adjusting
the VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty
cycle.
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider when S_LOAD transitions from
LOW-to-HIGH. The M divide and N output divide values are
latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is
held HIGH, data at the S_DATA input is passed directly to the M
divider on each rising edge of S_CLOCK. The serial mode can be
used to program the M and N bits and test bits T2:T0. The internal
resistors T2:T0 determine the state of the TEST output as follows:
The programmable features of the ICS84329B-01 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial. Figure 1
shows the timing diagram for each mode. In parallel mode the
T2
0
T1
0
T0
0
TEST Output
fOUT
fOUT
fOUT
fOUT
Shift Register Out
HIGH
0
0
1
0
1
0
PLL Reference XTAL ÷16
0
1
1
(VCO ÷ M) /2 (non 50% Duty Cycle M Divider)
fOUT, LVCMOS Output Frequency < 200MHz
LOW
fOUT
1
0
0
fOUT
1
0
1
fOUT
1
1
0
S_CLOCK ÷ M (non 50% Duty Cycle M Divider)
fOUT ÷ 4
S_CLOCK ÷ N Divider
fOUT
1
1
1
SERIAL LOADING
S_CLOCK
T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
S_DATA
S_LOAD
t
t
S
H
t
nP_LOAD
S
PARALLEL LOADING
M, N
M0:M8, N0:N1
nP_LOAD
t
t
H
S
nP_LOAD
Time
Figure 1. Parallel & Serial Load Operations
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Name
Type
Description
M0, M1, M2, M3, M4,
M5, M6, M7, M8
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS/LVTTL interface levels.
Input
Pullup
Pullup
Determines N output divider value as defined in Table 3C, Function Table.
LVCMOS/LVTTL interface levels.
N0, N1
VEE
Input
Power
Output
Negative supply pins.
Test output which is used in the serial mode of operation.
Single-ended LVPECL interface levels.
TEST
VCC
FOUT, nFOUT
nc
Power
Output
Unused
Core supply pins.
Differential output pair for the synthesizer. LVPECL interface levels.
No connect.
Clocks the serial data present at S_DATA input into the shift register on the rising edge
of S_CLOCK. LVCMOS/LVTTL interface levels.
S_CLOCK
S_DATA
Input
Input
Pulldown
Pulldown
Pulldown
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the M divider.
LVCMOS/LVTTL interface levels.
S_LOAD
VCCA
Input
Power
Input
Analog supply pin.
XTAL_IN
XTAL_OUT
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is loaded into M divider,
and when data present at N1:N0 sets the N output divider value. LVCMOS/LVTTL
interface levels.
nP_LOAD
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA Conditions
X
X
X
X
X
X
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to the M divider and
N output divider. TEST mode 000.
L
↑
Data
Data
X
Data
Data
X
X
L
L
↑
X
X
↑
L
X
Data is latched into input registers and remains loaded until
next LOW transition or until a serial event occurs.
X
Serial input mode. Shift register is loaded with data on S_DATA
on each rising edge of S_CLOCK.
H
H
Data
Data
Contents of the shift register are passed to the M divider and
N output divider.
X
X
H
H
X
X
X
X
↓
L
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
L
X
NOTE:L = LOW
H = HIGH
X = Don’t care
↑ = Rising edge transition
↓ = Falling edge transition
Table 3B. Programmable VCO Frequency Function Table
256
M8
0
128
M7
1
64
M6
1
32
M5
1
16
M4
1
8
M3
1
4
M2
0
2
M1
1
1
M0
0
VCO Frequency
(MHz)
M Divide
250
251
252
253
•
250
251
252
253
•
0
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
509
510
511
509
510
511
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
Table 3C. Programmable Output DividerFunction Table
Inputs
Output Frequency (MHz)
Minimum Maximum
250 700
N1
0
N0
0
N Divider Value
1
2
4
8
0
1
125
62.5
350
175
87.5
1
0
1
1
31.25
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC+ 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
28 Lead SOIC
28 Lead PLCC
46.2°C/W (0 lfpm)
37.8°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
3.465
125
Units
V
VCC
VCCA
ICC
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
mA
mA
ICCA
15
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VCC + 0.3
0.8
Units
VIH
VIL
Input High Voltage
2
V
V
Input Low Voltage
-0.3
S_CLOCK,
S_DATA, S_LOAD
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
150
5
µA
µA
µA
Input
High Current
IIH
nP_LOAD,
M0:M8, N0, N1
S_CLOCK,
S_DATA, S_LOAD
-5
Input
Low Current
IIL
nP_LOAD,
M0:M8, N0, N1
VCC = 3.465V, VIN = 0V
VCC = 3.3V 5%
-150
2.6
µA
V
VOH
VOL
Output High Voltage TEST; NOTE 1
Output
TEST; NOTE 1
Low Voltage
VCC = 3.3V 5%
0.5
V
NOTE 1: Outputs terminated with 50Ω to VCC/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 4C. LVPECL DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC – 1.4
VCC– 2.0
0.6
Typical
Maximum
VCC – 0.9
VCC – 1.7
1.0
Units
µA
Output High Current; NOTE 1
Output Low Current; NOTE 1
Peak-to-Peak Output Voltage Swing
VOL
µA
VSWING
V
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Frequency
Fundamental
10
25
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
Table 6. Input Frequency Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
Units
MHz
MHz
XTAL_IN, XTAL_OUT; NOTE 1
S_CLOCK
10
25
50
Input
fIN
Frequency
NOTE 1: For the crystal frequency range, the M value must be set to achieve the minimum or maximum VCO frequency range of 250MHz
to 700MHz range. Using the minimum input frequency of 10MHz, valid values of M are 400 ≤ M ≤ 511. Using the maximum input
frequency of 25MHz, valid values of M are 160 ≤ M ≤ 448.
AC Electrical Characteristics
Table 7. AC Characteristics, VVCC = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
700
35
Units
MHz
ps
fOUT
Output Frequency
f
OUT ≥ 50MHz
fOUT < 50MHz
OUT ≥ 65MHz
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 2
Period Jitter, RMS; NOTE 1, 2
50
ps
f
5.5
ps
tjit(per)
fOUT < 65MHz
20% to 80%
12
ps
tR / tF
tS
Output Rise/Fall Time
Setup Time
300
5
800
ps
ns
tH
Hold Time
5
ns
odc
tLOCK
Output Duty Cycle
PLL Lock Time
45
50
55
10
%
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
See Parameter Measurement Information section.
Characterized using XTAL inputs.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: See Applications Section.
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Parameter Measurement Information
2V
VOH
VREF
SCOPE
V
CC,
Qx
VOL
V
CCA
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
LVPECL
nQx
Histogram
Reference Point
(Trigger Edge)
VEE
Mean Period
(First edge after trigger)
-1.3V 0.165V
3.3 LVPECL Output Load AC Test Circuit
Period Jitter
nFOUT
FOUT
nFOUT
FOUT
80%
80%
tR
VSWING
20%
➤
➤
tcycle n
tcycle n+1
➤
➤
20%
tjit(cc) = tcycle n – tcycle n+1
tF
|
|
1000 Cycles
Cycle-to-Cycle Jitter
Output Rise/Fall Time
S_DATA
nFOUT
FOUT
tPW
tHOLD
S_CLOCK
tSET-UP
tPERIOD
S_LOAD
tPW
odc =
x 100%
tPERIOD
tSET-UP
M0:M8
N0:N1
Output Duty Cycle/Pulse Width/Period
tHOLD
nP_LOAD
tSET-UP
Setup and Hold Time
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The ICS84329B-01
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and VCCA should
be individually connected to the power supply plane through vias,
and 0.01µF bypass capacitors should be used for each pin. Figure
2 illustrates this for a generic VCC pin and also shows that VCCA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10µF
Figure 2. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
TEST Output
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
The unused TEST output can be left floating. There should be no
trace attached.
LVPECL Outputs
The unused LVPECL output pair can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or terminated.
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Crystal Input Interface
The ICS84329B-01 has been characterized for either series or
parallel mode operation. The ICS84329B-01 has a built-in crystal
oscillator circuit. This interface can accept either a series or parallel
crystal without additional components and generate frequencies
with accuracy suitable for most applications. Additional accuracy
can be achieved by adding two small capacitors C1 and C2 as
shown in Figure 3.
XTAL_IN
C1
18p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
Figure 3. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VCC
VCC
R1
0.1µf
50Ω
Ro
Rs
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 4. General Diagram for LVCMOS Driver to XTAL Input Interface
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
60
50
40
30
20
10
0
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525
Output Frequency (MHz)
Figure 5A. Cycle-to-Cycle Jitter vs. fOUT (using a 16MHz crystal)
14
12
10
8
6
4
2
0
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525
Output Frequency (MHz)
Figure 5B. RMS Jitter vs. fOUT (using a 16MHz crystal)
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 6A and 6B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Z
o = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
Zo = 50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
Figure 6A. 3.3V LVPECL Output Termination
Figure 6B. 3.3V LVPECL Output Termination
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Layout Guideline
The schematic of the ICS84329B-01 layout example used in this
layout guideline is shown in Figure 7A. The ICS84329B-01
recommended PCB board layout for this example is shown in
Figure 7B. This layout example is used as a general guideline. The
layout in the actual system will depend on the selected component
types, the density of the components, the density of the traces, and
the stack up of the P.C. board.
C1
0.1uF
C3
16MHz,18pF
X1
22p
VCC
VCC=3.3V
C4
R7
10
SP = Space (i.e. not intstalled)
M4
12
13
14
15
16
17
18
4
22p
M4
M5
M6
M7
M8
N0
N1
XTALI N
3
M5
M6
M7
M8
N2
N1
M[8:0]= 110010000 (400)
nc
2
N[1:0] =01 (Divide by 2)
nc
1
VCCA
VCCA
28
S_LOAD
27
S_DATA
26
C11
0.01u
C16
10u
S_CLOCK
U1
84329BV_01
C1
VCC
0.1uF
Zo = 50 Ohm
Fout = 200 MHz
RU0
SP
RU1
SP
RU7
RU8
1K
RU9
SP
RU10
1K
RU11
SP
C2
0.1u
1K
Zo = 50 Ohm
R2
50
R1
50
RD0
1K
RD1
1K
RD7
SP
RD8
SP
RD9
1K
RD10
SP
RD6
1K
R3
50
Figure 7A. ICS84329B-01 Schematic of Recommended Layout
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
• The differential 50Ω output traces should have the same
length.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
Power and Grounding
Place the decoupling capacitors C1, C2 and C3, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This can
reduce unwanted inductance between the decoupling capacitor
and the power pin caused by the via.
• Keep the clock traces on the same layer. Whenever
possible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power and
ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the VCCA pin as possible.
Clock Traces and Termination
• Make sure no other signal traces are routed between the
clock trace pair.
Poor signal integrity can degrade the system performance or cause
system failure. In synchronous high-speed digital systems, the
clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Crystal
The crystal X1 should be located as close as possible to the pins
4 (XTAL_IN) and 5 (XTAL_OUT). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
X1
C3
U1
GND
VCC
PIN 2
C16
C11
R7
VCCA
VIA
PIN 1
VCCA
Signals
Traces
C1
C2
50 Ohm
Traces
Figure 7B. PCB Board Layout for ICS84314-02
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS84329B-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84329B-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.3V, with all outputs switching) = 485mW + 30mW = 515mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate
air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 8A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.515W * 31.1°C/W = 86°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (multi-layer).
Table 8A. Thermal Resistance θJA for 28 Lead PLCC, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8°C/W
31.1°C/W
28.3°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 8B. Thermal Resistance θJA for 28 Lead SOIC, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
76.2°C/W
46.2°C/W
60.8°C/W
39.7°C/W
53.2°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
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700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of VCC – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
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700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Reliability Information
Table 9A. θJA vs. Air Flow Table for a 28 Lead SOIC
θJA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
76.2°C/W
46.2°C/W
60.8°C/W
39.7°C/W
53.2°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 9B. θJA vs. Air Flow Table for a 28 Lead PLCC
Linear Feet per Minute
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8°C/W
31.1°C/W
28.3°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS84329B-01 is: 4408
Pin compatible with the SY89429
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
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700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Package Outline and Package Dimensions
Package Outline - M Suffix for 28 Lead SOIC
Table 10A. Package Dimensions for 28 Lead SOIC
JEDEC: 300 MIL
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
A1
A2
B
C
D
E
28
2.65
0.10
2.05
0.33
0.18
17.70
7.40
2.55
0.51
0.32
18.40
7.60
e
1.27 Basic
10.00
H
h
10.65
0.75
1.27
8°
0.25
0.40
0°
L
α
Reference Document: JEDEC Publication 95, MS-013, MS-119
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Package Outline - V Suffix for 28 Lead PLCC
Table 10B. Package Dimensions for 28 Lead PLCC
JEDEC
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
28
4.19
2.29
1.57
0.33
0.19
12.32
11.43
4.85
4.57
3.05
2.11
0.53
0.32
12.57
11.58
5.56
A1
A2
b
c
D & E
D1 & E1
D2 & E2
Reference Document: JEDEC Publication 95, MS-018
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
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700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Ordering Information
Table 11. Ordering Information
Part/Order Number
84329BV-01
84329BV-01T
84329BM-01
84329BM-01T
84329BM-01LF
84329BM-01LFT
Marking
Package
28 Lead PLCC
28 Lead PLCC
28 Lead SOIC
28 Lead SOIC
Shipping Packaging
Tube
500 Tape & Reel
Tube
1000 Tape & Reel
Tube
1000 Tape & Reel
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS84329BV-01
ICS84329BV-01
ICS84329BM-01
ICS84329BM-01
ICS84329BM-01LF
ICS84329BM-01LF
“Lead-Free” 28 Lead SOIC
“Lead-Free” 28 Lead SOIC
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
2
Paragraph 2 changed series resonant crystal to parallel resonant crystal.
Ordering Information Table - added ""ICS"" to the marking.
A
11/1/04
T11
18
1
2
Features Section - added Lead-Free bullet.
Updated Parallel & Serial Load Operations diagram.
T3A
4
Parallel & Serial Mode Function Table - corrected S_LOAD column 3rd row, from X to
L.
A
5/23/05
T5
6
Crystal Table - added Drive Level.
T11
18
Ordering Information Table - added Lead-Free part numbers and note.
A
B
1
1
Features Section - corrected Output frequency range from 25MHz to 31.25MHz.
6/10/05
3/26/09
PLCC Pin Assignment, corrected pin 5 typo from XTAL2_OUT to XTAL_OUT.
Converted datasheet format.
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
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ICS84329BM-01 REV. B MARCH 26, 2009
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700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Contact Information:
www.IDT.com
Corporate Headquarters
Sales
Technical Support
Integrated Device Technology, Inc.
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
+480-763-2056
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
www.IDT.com/go/contactIDT
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
www.IDT.com
Printed in USA
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