ICS8432BYI-01T [IDT]
Clock Generator, 700MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32;
| 型号： | ICS8432BYI-01T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 700MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 |
| 文件： | 总9页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8432-01I
Integrated
Circuit
Systems, Incꢀ
700MHZ
LVPECLFREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8432-01I is a general purpose, dual out- • Dual differential 3.3V LVPECLoutput
put high frequency synthesizer and a member of
• Selectable crystal oscillator interface and
the HiPerClockS™ family of High Performance
LVCMOS reference input
HiPerClockS™
Clocks Solutions from ICS. The VCO operates at
a frequency range of 250MHz to 700MHz.
• 31.25MHz to 700MHz output frequency
The VCO frequency is programmed in steps equal to the value
of the input reference or crystal frequency. The VCO and out-
put frequency can be programmed using the serial
or parallel interfaces to the configuration logic.
• 14MHz to 25MHz crystal or reference frequency
• Parallel or serial interface for programming counter
and output dividers
• VCO range: 250MHz to 700MHz
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
XTAL_SEL
TEST_CLK
0
32 31 30 29 28 27 26 25
XTAL1
1
M5
OSC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL1
XTAL2
M6
M7
M8
N0
N1
nc
TEST_CLK
XTAL_SEL
VCCA
ICS8432-01I
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
0
VEE
MR
VCO
FOUT0
nFOUT0
FOUT1
nFOUT1
÷ N
9
10 11 12 13 14 15 16
÷ M
1
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
M0:M8
N0:N1
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8432BYI-01
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REV. B JULY 30, 2001
1
PRELIMINARY
ICS8432-01I
Integrated
Circuit
Systems, Incꢀ
700MHZ
LVPECLFREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1.
The ICS8432-01I features a fully integrated PLL and therefore requires no external component for setting the loop bandwidth.
A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is fed into the
phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over
a range of 250MHz to 700MHz. The output of the loop divider is also applied to the phase detector.
The phase detector and the loop filter divider force the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve lock.
The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides
a 50% output duty cycle.
The programmable features of the ICS8432-01I support two input modes and programmable PLL loop divider and output
divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel
mode the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the ripple
counter. On the LOW-to-HIGH transition of the nP_LOAD input the data is latched and the ripple counter remains loaded until
the next LOW transition on nP_LOAD or until a serial event occurs. As a result the M and N bits can be hardwired to set the
ripple counter to a specific default state that will automatically occur during power-up. The TEST output is LOW when operat-
ing in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the loop divider is
defined as follows:
fVCO = fxtal x M
The M count and the required values of M0 through M8 are shown in Table 4B, Programmable VCO Frequency Function.
Valid M values for which the PLL will achieve lock are defined as 10 ≤ M ≤ 28. The frequency out is defined as follows:
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the
S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the ripple counter when
S_LOAD transitions from LOW-to-HIGH. The ripple counter divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH data at the S_DATA input is passed directly to the ripple counter on each rising edge of
S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1
determine the state of the TEST output as follows:
T1 T0
TEST Output
LOW
0
0
1
1
0
1
0
1
S_Data
Output of M divider
CMOS Fout
T1
T0 *NULL N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_DATA
S_CLOCK
S_LOAD
M0:M8, N0:N2
nP_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
NOTE: *The NULL timing slot must be observed.
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REV. B JULY 30, 2001
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PRELIMINARY
ICS8432-01I
Integrated
Circuit
Systems, Incꢀ
700MHZ
LVPECLFREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Description
1
M5
Input
Input
M counter/divider inputs. Data latched on LOW-to-HIGH transistion
of nP_LOAD input. LVCMOS / LVTTL interface levels.
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Pulldown
Pulldown
Determines output divider value as defined in Table 4C Function
table. LVCMOS / LVTTL interface levels.
5, 6
N0, N1
Input
7
nc
Unused
Power
Unused pin.
8, 16
VEE
Power supply ground pin. Connect to ground.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS interface levels.
9
TEST
VCC
Output
Power
Output
Power
Output
10
Core power supply pin.
Differential output for the synthesizer.
3.3V LVPECL interface levels.
11, 12
13
FOUT1, nFOUT1
VCCO
Output power supply connection. Connect to 3.3V.
Differential output for the synthesizer.
3.3V LVPECL interface levels.
14, 15
FOUT0, nFOUT0
Forces outputs LOW, but does not effect loaded M, N, and T
values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLK.
Shift register serial input. Data sampled on the rising edge of
S_CLK.
17
18
19
MR
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pulldown
S_CLOCK
S_DATA
Controls transition of data from shift register into the ripple counter.
LVCMOS / LVTTL interface levels.
20
21
S_LOAD
VCCA
Input
Power
Analog power supply pin. Connect to 3.3V.
Selects between crystal or test inputs as the PLL reference
source. LVCMOS / LVTTL interface levels. Selects XTAL inputs
when HIGH. Selects TEST_CLK when LOW.
22
Input
Pullup
XTAL_SEL
23
TEST_CLK
Input
Input
Pulldown Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator inputs.
24, 25
XTAL1, XTAL2
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into ripple counter, and when data present at N1:N0 sets
the output divide value. LVCMOS / LVTTL interface levels.
26
27
nP_LOAD
VCO_SEL
Input
Input
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS / LVTTL interface levels.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions Minimum Typical Maximum Units
TEST_CLK,
XTAL1, XTAL2
4
pF
VCO_SEL, S_DATA,
XTAL_SEL, S_LOAD,
nP_LOAD, S_CLOCK,
MR, M0:M8, N0:N1
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
51
KΩ
KΩ
RPULLDOWN Input Pulldown Resistor
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REV. B JULY 30, 2001
3
PRELIMINARY
ICS8432-01I
Integrated
Circuit
Systems, Incꢀ
700MHZ
LVPECLFREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODES FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Reset. M and N counters reset.
Data on M and N inputs passed directly to the
ripple counter and output divider.
TEST output forced LOW.
Data is latched into input registers and remains
loaded until next LOW transition or until a serial
event occurs.
L
L
Data Data
Data Data
X
X
X
L
↑
L
X
X
Serial input mode. Shift register is loaded with
data on S_DATA on each rising edge of
S_CLOCK.
Contents of the shift register are passed to the
ripple counter and output divider.
Ripple counter and output divide values are
latched.
L
L
H
H
X
X
X
X
L
↑
Data
Data
↑
L
L
L
H
H
X
X
X
X
↓
L
Data
X
L
X
Parallel or serial input do not affect shift registers.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
0
32
16
M4
0
8
M3
1
4
M2
0
2
M1
1
1
M0
0
VCO Frequency
(MHz)
M Count
M5
0
0
0
0
•
250
275
300
325
•
10
11
12
13
•
0
0
0
0
1
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
675
700
26
27
28
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1
1
0
1
1
0
0
0
1
1
1
0
0
NOTE 1: These M count values and the resulting frequency correspond to crystal or test clock input frequency of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Output Frequency
Inputs
N Divider
Value
(MHz)
N1
0
N0
0
Minimum
250
Maximum
700
1
2
4
8
0
1
125
350
1
0
62.5
175
1
1
31.25
87.5
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REV. B JULY 30, 2001
4
PRELIMINARY
ICS8432-01I
Integrated
Circuit
Systems, Incꢀ
700MHZ
LVPECLFREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCX
Inputs, VI
Outputs, VO
4.6V
-0.5V to VCC + 0.5 V
-0.5V to VCC + 0.5V
Package Thermal Impedance, θJA 46°C/W
Storage Temperature, TSTG -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any conditions beyond those listed in the DC Character-
istics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
TABLE 4A. DC POWER SUPPLY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
CC, VCCA, VCCO
Parameter
Test Conditions
Minimum
Typical
Maximum Units
V
Power Supply Voltage
Power Supply Current
Analog Power Supply Current
3.135
3.3
3.465
110
V
IEE
mA
mA
ICCA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VCCx = 3.465V
VCCx = 3.465V
Minimum Typical Maximum Units
VCO_SEL, XTAL_SEL, S_LOAD,
nP_LOAD, S_DATA, S_CLOCK,
N0:N1, M0:M8, MR
2
3.765
3.765
0.8
V
V
V
Input
VIH
High Voltage
TEST_CLK
1.7
-0.3
VCO_SEL, XTAL_SEL, S_LOAD,
nP_LOAD, S_DATA, S_CLOCK,
N0:N1, M0:M8, MR
V
CCx = 3.135V
Input
VIL
Low Voltage
TEST_CLK
VCCx = 3.135V
1.3
V
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, , nP_LOAD
*VCCx = VIN
=
150
µA
3.465V
Input
IIH
High Current
VCCx = VIN
3.465V
=
M5, XTAL_SEL, VCO_SEL
5
µA
µA
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, , nP_LOAD
VCCx = 3.465V,
IN = 0V
VCCx = 3.465V,
IN = 0V
-5
V
Input
IIL
Low Current
M5, XTAL_SEL, VCO_SEL
-150
2.6
µA
V
V
VCCx = 3.135V,
IOH = -36mA
Output
VOH
TEST
TEST
High Voltage
VCCx = 3.135V,
IOL = 36mA
Output
VOL
0.5
V
Low Voltage
*NOTE 1: VCCx denotes VCC, VCCA, and VCCO
.
8432BYI-01
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REV. B JULY 30, 2001
5
PRELIMINARY
ICS8432-01I
Integrated
Circuit
Systems, Incꢀ
700MHZ
LVPECLFREQUENCY SYNTHESIZER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT0,
nFOUT0
FOUT1,
nFOUT1
FOUT0,
nFOUT0
FOUT1,
nFOUT1
FOUT0,
nFOUT0
Output High Voltage;
NOTE 1
VOH
*VCCx = 3.3V
2.1
V
V
V
Output Low Voltage;
NOTE 1
VOL
VCCx = 3.3V
1.6
Peak-to-Peak
VSWING
3.135V ≤ VCCx ≤ 3.465V
0.6
0.85
Output Voltage Swing FOUT1,
nFOUT1
NOTE 1: FOUT0, nFOUT0, FOUT1, nFOUT1 outputs terminated with 50 Ω to VCCO - 2V.
NOTE 2: VCCx denotes VCC, VCCA, VCCO
.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Crystal Cut / Mode of Oscillation
Frequency
AT / Fundamental
14
-50
25
50
MHz
ppm
ppm
µW
Ω
Frequency Tolerance
Frequency Stability
Drive Level
-100
100
0.1
18
Equivalent Series Resistance (ESR)
Shunt Capacitiance
Load Capaacitance
Series Pin Inductance
Operating Temperature Range
Aging
50
80
7
pF
10
3
32
7
pF
nH
0
70
5
°C
Per year @ 25°C
-5
ppm
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK;
NOTE 1
XTAL1, XTAL2;
NOTE 1
14
14
25
25
MHz
MHz
Maximum
fIN
Input Frequency
S_CLOCK
TEST_CLK
TEST_CLK
TBD
TBD
TBD
MHz
ns
tR
tF
Input Rise Time
Input Fall Time
Measured at 20% to 80% points
Measured at 20% to 80% point
ns
Input Reference
Duty Cycle
tDC
TEST_CLK
TBD
TBD
%
NOTE 1: For the input crystal and reference frequency range the M value must be set for the VCO to operate within the
250MHz to 700MHz range. Using the minimum input frequency of 14MHz valid values of M are 18 ≤ M ≤ 50. Using the
maximum frequency of 25MHz valid values of M are 10 ≤ M ≤ 28.
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REV. B JULY 30, 2001
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PRELIMINARY
ICS8432-01I
Integrated
Circuit
Systems, Incꢀ
700MHZ
LVPECLFREQUENCY SYNTHESIZER
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
Units
MHz
ps
FOUT
tjit(acc)
tjit(per)
tsk(o)
odc
Output Frequency
31.25
700
Accumulative Period Jitter, RMS
Period Jitter, RMS
ps
Output Skew
10
53
ps
Output Duty Cycle
47
%
FOUT0, nFOUT0
tR
Output Rise Time
Output Fall Time
20% to 80%
20% to 80%
300
800
800
ps
FOUT1, nFOUT1
FOUT0, nFOUT0
FOUT1, nFOUT1
tF
300
TBD
TBD
ps
ns
ns
M, N to nP_LOAD
S_DATA to
S_CLOCK
S_CLOCK to
S_LOAD
tS
Setup Time
Hold Time
TBD
TBD
TBD
ns
ns
ns
M, N to nP_LOAD
S_DATA to
S_CLOCK
S_CLOCK to
S_LOAD
tH
TBD
ns
tLOCK
tPW
PLL Lock Time
Pulse Width
TBD
TBD
TBD
ms
ns
ns
nP_LOAD
S_LOAD
*NOTE 1: VCCx denotes VCC, VCCA, and VCCO
.
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REV. B JULY 30, 2001
7
PRELIMINARY
ICS8432-01I
Integrated
Circuit
Systems, Incꢀ
700MHZ
LVPECLFREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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REV. B JULY 30, 2001
8
PRELIMINARY
ICS8432-01I
Integrated
Circuit
Systems, Incꢀ
700MHZ
LVPECLFREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS8432BYI-01
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
-40°C to 85°C
-40°C to 85°C
ICS8432BI-01
ICS8432BI-01
ICS8432BYI-01T
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. B JULY 30, 2001
9
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