ICS85214AGT-LF [IDT]
Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40, 0.92 MM HEIGHT, MO-153, TSSOP-20;
| 型号： | ICS85214AGT-LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40, 0.92 MM HEIGHT, MO-153, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总16页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS85214 is a low skew, high performance • 5 differential HSTL compatible outputs
1-to-5 Differential-to-HSTL Fanout Buffer and a
• Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL
clock inputs
HiPerClockS™
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
CLK0, nCLK0 pair can accept most standard dif-
• CLK0, nCLK0 pair can accept the following differential
ferential input levels. The single ended CLK1 input accepts
LVCMOS or LVTTLinput levels. Guaranteed output and part-
to-part skew characteristics make the ICS85214 ideal for
those clock distribution applications demanding well de-
fined performance and repeatability.
input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
• CLK1 can accept the following input levels:
LVCMOS or LVTTL
• Output frequency up to 700MHz
• Translates any single ended input signal to HSTLlevels
with resistor bias on nCLK0 input
• Output skew: 30ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.8ns (maximum)
• 3.3V core, 1.8V output operating supply
• 0°C to 85°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
1
2
3
4
5
6
20
19
18
17
16
15
14
13
12
11
VDDO
nCLK_EN
VDD
D
nCLK_EN
Q
LE
nc
CLK0
nCLK0
0
CLK1
CLK0
nCLK0
nc
CLK_SEL
GND
Q0
nQ0
1
CLK1
7
8
9
10
Q1
nQ1
CLK_SEL
nQ4
Q2
nQ2
ICS85214
Q3
nQ3
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Q4
Top View
nQ4
85214AG
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REV. A JULY 17, 2003
1
ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
GND
Type
Description
Output
Output
Output
Output
Output
Power
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Power supply ground.
3, 4
5, 6
7, 8
9, 10
11
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0, nCLK0 input. LVTTL / LVCMOS interface levels.
12
CLK_SEL
Input
Pulldown
Pullup
13, 17
14
nc
Unused
Input
No connect.
nCLK0
CLK0
CLK1
VDD
Inverting differential clock input.
15
Input
Pulldown Non-inverting differential clock input.
Pulldown Clock input. LVTTL / LVCMOS interface levels.
Core supply pin.
16
Input
18
Power
Synchronizing clock enable. When LOW, clock outputs follow clock input.
Pulldown When HIGH, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
19
nCLK_EN
Input
20
VDDO
Power
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
85214AG
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ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
nQ0:nQ4
Enabled
nCLK_EN
Q0:Q4
0
1
Enabled
Disabled; LOW
Disabled; HIGH
After nCLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 inputs as described in Table 3B.
Enabled
Disabled
nCLK0
CLK0
nCLK_EN
nQ0:nQ4
Q0:Q4
FIGURE 1. nCLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK0, CLK1
nCLK0
Q0:Q4
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQ0:nQ4
HIGH
LOW
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDX
Inputs, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
Outputs, VDDO
Package Thermal Impedance, θJA 73.2°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Input Power Supply Voltage
3.465
2.0
V
V
Output Power Supply Voltage
Power Supply Current
1.6
1.8
80
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
nCLK_EN, CLK_SEL
CLK1
2
VDD + 0.3
V
V
V
V
VIH
VIL
Input High Voltage
2
VDD + 0.3
nCLK_EN, CLK_SEL
CLK1
-0.3
-0.3
0.8
Input Low Voltage
1.3
CLK1, CLK_SEL,
nCLK_EN
CLK1, CLK_SEL,
nCLK_EN
IIH
IIL
Input High Current
Input Low Current
VDD = VIN = 3.465V
150
µA
µA
VDD = 3.465V, VIN = 0V
-5
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
nCLK0
CLK0
V
DD = VIN = 3.465V
5
µA
µA
µA
µA
V
IIH
Input High Current
VDD = VIN = 3.465V
150
nCLK0
CLK0
V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-150
-5
IIL
Input Low Current
V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
V
DD - 0.85
V
NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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REV. A JULY 17, 2003
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ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4D. HSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Output High Voltage;
NOTE 1
VOH
1
1.4
V
Output Low Voltage;
NOTE 1
VOL
0
38% x (VOH - VOL) + VOL
0.6
0.4
60% x (VOH - VOL) + VOL
1.1
V
V
V
VOX
Output Crossover Voltage
Peak-to-Peak
Output Voltage Swing
VSWING
NOTE 1: Outputs terminated with 50Ω to ground.
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK0, nCLK0
CLK1
700
300
1.8
30
MHz
MHZ
ns
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
IJ 700MHz
1.0
tsk(o)
tsk(pp)
tR
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
ps
250
700
700
54
ps
20% to 80%
20% to 80%
200
200
46
ps
tF
Output Fall Time
ps
CLK0, nCLK0
CLK1
%
odc
Output Duty Cycle
45
55
%
All parameters measured at fMAX unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from either the differential input crossing point or VDD/2 to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
85214AG
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REV. A JULY 17, 2003
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ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
1.8V±0.2V
3.3V±5%
VDD
SCOPE
VDD
Qx
nCLK0
CLK0
VDDO
VPP
VCMR
Cross Points
HSTL
nQx
GND
GND = 0V
3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
nQx
PART 1
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
80%
80%
CLK1
VSWING
20%
Clock
20%
nQ0:nQ4
Outputs
tF
tR
Q0:Q4
tPD
OUTPUT RISE/FALL TIME
nQ0:nQ4
Q0:Q4
nCLK0
CLK0
Pulse Width
tPERIOD
nQ0:nQ4
tPW
Q0:Q4
odc =
tPD
tPERIOD
odc, tPW & tPERIOD
PROPAGATION DELAY
85214AG
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REV. A JULY 17, 2003
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ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1. This bias circuit clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin. The ratio and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3D show inter-
face examples for the ICS85214 clock input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver com-
ponent to confirm the driver termination requirements. For ex-
ample in Figure 3A, the input termination applies for ICS
HiPerClockS HSTLdrivers. If you are using an HSTL driver from
another vendor, use their termination recommendations.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiver
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
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REV. A JULY 17, 2003
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ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example of the ICS85214. In this
near the power pin. For ICS85214, the unused outputs can be
example, the input is driven by an ICS HiPerClockS HSTL left floating.
driver. The decoupling capacitors should be physically located
Zo = 50
Zo = 50
+
-
R2
50
R1
50
U1
1.8V
R12 1K
11
12
13
14
15
16
17
18
19
20
10
9
8
7
6
5
4
3
2
1
GND
CLK_SEL
nc
nCLK
CLK
SCLK
nc
VDD
nCLK_EN
VDDO
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
Zo = 50
+
-
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50
3.3V
C2
nQ0
Q0
1.8V
R4
50
R3
50
LVHSTL Driver
R9
50
R10
50
0.1u
C1
0.1u
ICS85214
Zo = 50
+
-
R11
1K
Zo = 50
R8
50
R7
50
FIGURE 4. ICS85214 HSTL BUFFER SCHEMATIC EXAMPLE
85214AG
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ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85214.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85214 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 80mA = 227.2mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 32.8mW = 164mW
Total Power_MAX (3.465V, with all outputs switching) = 227.2mW + 164mW = 391.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.391W * 66.6°C/W = 111°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE qJA FOR 20-PIN TSSOP, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85214AG
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ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 5.
VDDO
Q1
VOUT
RL
Ω
50
FIGURE 5. HSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
- V
)
)
OH_MIN
L
DDO_MAX
OH_MIN
/R ) * (V
OL_MAX
L
DDO_MAX
OL_MAX
Pd_H = (1.0V/50Ω) * (2V - 1.0V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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REV. A JULY 17, 2003
11
ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
98.0°C/W
88.0°C/W
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85214 is: 674
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ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - G SUFFIX
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Maximum
20
SYMBOL
Minimum
N
A
A1
A2
b
--
1.20
0.05
0.80
0.19
0.09
6.40
0.15
1.05
0.30
c
0.20
D
6.60
E
6.40 BASIC
4.50
E1
e
4.30
0.65 BASIC
0.75
L
0.45
0°
α
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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REV. A JULY 17, 2003
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ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS85214AG
Marking
Package
Count
72 per tube
2500
Temperature
0°C to 85°C
0°C to 85°C
ICS85214AG
ICS85214AG
20 lead TSSOP
ICS85214AG
20 Lead TSSOP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
85214AG
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REV. A JULY 17, 2003
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ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Throughout data sheet changed LVHSTL to HSTL.
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
Date
A
7/17/03
2
2
85214AG
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REV. A JULY 17, 2003
15
ICS85214
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Throughout data sheet changed LVHSTL to HSTL.
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
Date
A
7/17/03
2
2
85214AG
www.icst.com/products/hiperclocks.html
REV. A JULY 17, 2003
15
相关型号：
ICS8521AY
Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32
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ICS8521AYI-03LF
Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
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ICS8521AYI-03LFT
Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
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ICS8521AYLF
Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32
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ICS8521AYYT
Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32
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