ICS85310AY-11 [IDT]
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32;
| 型号： | ICS85310AY-11 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 |
| 文件： | 总15页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS85310-11 is a low skew, high perfor- • 10 differential 2.5V/3.3V LVPECL / ECLoutputs
mance 1-to-10 Differential-to-2.5V/3.3V ECL/
LVPECL Fanout Buffer and a member of the
• 2 selectable differential input pairs
HiPerClockS™
HiPerClockS™ family of High Performance
Clock Solutions from ICS. The CLKx, nCLKx
• CLKx, nCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
pairs can accept most standard differential input levels.
The ICS85310-11 is characterized to operate from either
a 2.5V or a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS85310-11
ideal for those clock distribution applications demanding
well defined performance and repeatability.
• Maximum output frequency: 700MHz
• Translates any single ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
• Output skew: 30ps (typical)
• Part-to-part skew: 140ps (typical)
• Propagation delay: 2ns (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.8V
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
CLK0
nCLK0
0
1
CLK1
nCLK1
Q1
nQ1
32 31 30 29 28 27 26 25
Q2
nQ2
VCC
CLK_SEL
CLK0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q3
nQ3
Q4
CLK_SEL
CLK_EN
Q3
nQ3
nCLK0
nQ4
Q5
ICS85310-11
D
Q4
nQ4
CLK_EN
CLK1
Q
nQ5
Q6
LE
nCLK1
Q5
nQ5
nQ6
VEE
Q6
9
10 11 12 13 14 15 16
nQ6
Q7
nQ7
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Q8
nQ8
Y Package
Top View
Q9
nQ9
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REV. B MAY 29, 2002
1
ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VCC
Power
Positive supply pin.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.
2
CLK_SEL
Input Pulldown
3
4
CLK0
Input Pulldown Non-inverting differential clock input.
nCLK0
Input
Pullup
Inverting differential clock input.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
5
CLK_EN
Input
Pullup
6
7
CLK1
nCLK1
VEE
Input Pulldown Non-inverting differential clock input.
Input
Power
Power
Pullup
Inverting differential clock input.
8
Negative supply pin.
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
VCCO
Output supply pins.
nQ9, Q9 Output
nQ8, Q8 Output
nQ7, Q7 Output
nQ6, Q6 Output
nQ5, Q5 Output
nQ4, Q4 Output
nQ3, Q3 Output
nQ2, Q2 Output
nQ1, Q1 Output
nQ0, Q0 Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
KΩ
RPULLDOWN Input Pulldown Resistor
KΩ
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ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
Selected Source
Q0:Q9
Disabled; LOW
Enabled
Q0:Q9
Disabled; HIGH
Enabled
0
1
CLK0, nCLK0
CLK1, nCLK1
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 inputs as described
in Table 3B.
Enabled
Disabled
CLK0, nCLK0
CLK1, CLK1
CLK_EN
nQ0:nQ9
Q0:Q9
FIGURE 1 - CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK0 or CLK1
nCLK0 or nCLK1
Q0:Q9
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQ0:Q9
HIGH
LOW
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
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ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCCO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
47.9°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 2.375V -3.8V, TA = -40°C TO 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum
2.375
Typical
3.3
Maximum Units
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
3.8
3.8
30
V
V
VCCO
IEE
2.375
3.3
mA
Table 4B. LVCMOS DC Characteristics, VCC = VCCO = 2.375V - 3.8V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK_SEL,
CLK_EN
CLK_SEL,
CLK_EN
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
CC = VIN = 3.8V
CC = VIN = 3.8V
5
µA
µA
µA
µA
IIH
V
150
V
CC = 3.8V, VIN = 0V
CC = 3.8V, VIN = 0V
-150
-5
IIL
Input Low Current
V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 2.375V - 3.8V, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
CC = VIN = 3.8V
Minimum
Typical
Maximum Units
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
V
150
5
µA
µA
µA
µA
V
VCC = VIN = 3.8V
CC = 3.8V, VIN = 0V
CC = 3.8V, VIN = 0V
V
V
-5
-150
IIL
Input Low Current
nCLK0, nCLK1
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VCC + 0.3V.
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ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 2.375V -3.8V, TA = -40°C TO 85°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum Units
700
2.5
55
MHz
ns
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
IJ 500MHz
2
tsk(o)
tsk(pp)
tR
30
ps
140
340
700
700
53
ps
20% to 80%
20% to 80%
200
200
47
ps
tF
Output Fall Time
ps
odc
Output Duty Cycle
%
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
VCC, VCCO
SCOPE
Qx
LVPECL
VCC, VCCO = 2V
nQx
VEE = -0.375V to -1.8V
3.3V OUTPUT LOAD TEST CIRCUIT
VCC
nCLK0, nCLK1
VPP
VCMR
Cross Points
CLK0, CLK1
VEE
DIFFERENTIAL INPUT LEVEL
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ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
nQx
Qx
nQy
Qy
tsk(o)
OUTPUT SKEW
nQx
PART 1
Qx
nQy
PART 2
Qy
tsk(pp)
PART-TO-PART SKEW
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
INPUT AND OUTPUT RISE AND FALL TIME
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ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
nCLK0, nCLK1
CLK0, CLK1
nQ0:nQ9
Q0:Q9
tPD
PROPAGATION DELAY
nQ0:nQ9
Q0:Q9
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
odc & tPERIOD
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ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 2 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECLcompatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
5
2
5
Zo
Zo
2
FIN
FOUT
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
➤
V
CC - 2V
Zo = 50Ω
RTT
1
3
2
3
2
Zo
RTT =
Zo
Zo
(VOH + VOL / VCC –2) –2
FIGURE 3A - LVPECL OUTPUT TERMINATION
FIGURE 3B - LVPECL OUTPUT TERMINATION
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ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85310-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85310-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 30mA = 114mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30.2mW = 302mW
Total Power_MAX (3.8V, with all outputs switching) = 114mW + 302mW = 416mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.416W * 42.1°C/W = 102.5°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE qJA FOR 32-PIN LQFP, FORCED CONVECTION
q by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
Figure 4 - LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CCO_MAX
)
= 1.0V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
))
/R ] * (V
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
) = [(2V - (V
- V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
OH_MAX
CCO _MAX
OH_MAX
L
CCO
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
/R ] * (V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
- V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
OL_MAX
CCO_MAX
OL_MAX
L
CCO
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L= 30.2mW
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ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
q by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85310-11 is: 1034
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ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS85310AY-11
Marking
Package
32 lead LQFP
Count
250 per tray
1000
Temperature
-40°C to 85°C
-40°C to 85°C
ICS85310AY-11
ICS85310AY-11
ICS85310AY-11T
32 lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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ICS85310-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
REVISION HISTORY SHEET
Rev
Table
T5
Page
Description of Change
Date
AC Characterisitics table - tPD row, revised value from 2.25ns Max. to
2.5ns Max.
B
5
9
4/29/02
5/29/02
Added Termination for LVPECL Outputs section.
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REV. B MAY 29, 2002
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Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
IDT
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