ICS85314AMI-01LFT [IDT]
Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, SOIC-20;
| 型号： | ICS85314AMI-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, SOIC-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总15页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS85314I-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS85314I-01 is a low skew, high performance • 5 differential 2.5V/3.3V LVPECL outputs
1-to-5 Differential-to-3.3V LVPECL fanout buffer
and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS.
The ICS85314I-01 has two selectable clock inputs.
• Selectable differential CLK0, nCLK0 or LVCMOS inputs
HiPerClockS™
• CLK0, nCLK0 pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
The CLK0, nCLK0 pair can accept most standard differential
input levels. The single-ended CLK1 can accept LVCMOS or
LVTTL input levels. The clock enable is internally synchronized
to eliminate runt clock pulses on the outputs during asynchro-
nous assertion/deassertion of the clock enable pin.
• CLK1 can accept the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
Guaranteed output and part-to-part skew characteristics make
the ICS85314I-01 ideal for those applications demanding well
defined performance and repeatability.
• Output skew: 50ps (maximum)
• Part-to-part skew: 400ps (maximum)
• Propagation delay: CLK0, nCLK0, 2.1ns (maximum)
CLK1, 2.1ns (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• -40°C to 85°C ambient operating temperature
• Compatible to part number MC100LVEL14
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
nCLK_EN
VCC
D
nCLK_EN
Q
LE
CLK0
nCLK0
nc
0
Q0
nQ0
CLK1
CLK0
nCLK0
nc
1
CLK1
Q1
nQ1
CLK_SEL
VEE
CLK_SEL
nQ4
Q2
nQ2
ICS85314I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Q3
nQ3
Q4
nQ4
Top View
ICS85314I-01
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm Package Body
M Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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1
PRELIMINARY
ICS85314I-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
VEE
Type
Description
Output
Output
Output
Output
Output
Power
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
3, 4
5, 6
7, 8
9, 10
11
Negative supply pin.
Clock select input. When HIGH, selects SCLK input.
12
CLK_SEL
Input
Pulldown When LOW, selects CLK, nCLK inputs.
LVTTL / LVCMOS interface levels.
13, 17
14
nc
Unused
Input
No connect.
nCLK0
CLK0
CLK1
VCC
Pullup
Inverting differential clock input.
15
Input
Pulldown Non-inverting differential clock input.
Pulldown Clock input. LVTTL / LVCMOS interface levels.
Positive supply pins.
16
Input
18, 20
Power
Synchronizing clock enable. When LOW, clock outputs follow clock
Pulldown input. When HIGH, Q outputs are forced low, nQ outputs are forced
high. LVTTL / LVCMOS interface levels.
19
nCLK_EN
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
KΩ
KΩ
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PRELIMINARY
ICS85314I-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
nCLK_EN
CLK_SEL
Selected Source
CLK0, nCLK0
CLK1
Q0:Q4
Enabled
nQ0:nQ4
Enabled
0
0
1
1
0
1
0
1
Enabled
Enabled
CLK0, nCLK0
CLK1
Disabled; LOW
Disabled; LOW
Disabled; HIGH
Disabled; HIGH
After nCLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1 inputs as described
in Table 3B.
Enabled
Disabled
nCLK0
CLK0, CLK1
nCLK_EN
nQ0:nQ4
Q0:Q4
FIGURE 1 - nCLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK0 or CLK1
nCLK0
Q0:Q4
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQ0:nQ4
HIGH
LOW
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
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PRELIMINARY
ICS85314I-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCx
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
73.2°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
TABLE 4A. POWER SUPPLY CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
Power Supply Voltage
Power Supply Current
2.375
3.8
V
IEE
55
mA
TABLE 4B. LVCMOS / LVTTL CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
nCLK_EN, CLK_SEL
CLK1
2
VCC + 0.3
VCC + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
2
nCLK_EN, CLK_SEL
CLK1
-0.3
-0.3
Input Low Voltage
1.3
CLK1,
CLK_SEL, nCLK_EN
CLK1,
IIH
IIL
Input High Current
Input Low Current
VIN = VCC = 3.8V
150
µA
µA
VCC = 3.8V, VIN = 0V
-5
CLK_SEL, nCLK_EN
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VCC = VIN = 3.8V
Minimum Typical Maximum Units
nCLK0
CLK0
5
µA
µA
µA
µA
V
VCC = VIN = 3.8V
150
nCLK0
CLK0
VCC = 3.8V, VIN = 0V
VCC = 3.8V, VIN = 0V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VCC - 0.85
V
NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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PRELIMINARY
ICS85314I-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VCC - 1.4
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 1.0
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VCC - 2.0
VSWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
650
2.1
MHz
ns
CLK0, nCLK0;
NOTE 1
IJ 650MHz
IJ 250MHz
1.0
1.0
Propagation Delay,
Low to High
tpLH
CLK1; NOTE 2
2.1
50
ns
ps
ps
ps
ps
%
tsk(o)
tsk(pp)
tR
Output Skew; NOTE 3, 5
Part-to-Part Skew; NOTE 4, 5
Output Rise Time
400
700
700
55
20% to 80% @ 50MHz
20% to 80% @ 50MHz
IJ 650MHz
200
200
45
tF
Output Fall Time
CLK0, nCLK0
CLK1
odc
Output Duty Cycle
IJ 250MHz
45
55
%
All parameters measured at 250MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Measured from VCC/2 input crossing point to the differential output crossing point.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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REV. B JULY 30, 2002
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PRELIMINARY
ICS85314I-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VCC
SCOPE
Qx
LVPECL
VCC = 2V
nQx
VEE =-1.8V to -0.375V
OUTPUT LOAD TEST CIRCUIT
VCC
nCLK0
VPP
VCMR
Cross Points
CLK0
VEE
DIFFERENTIAL INPUT LEVEL
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PRELIMINARY
ICS85314I-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
nQx
Qx
nQy
Qy
tsk(o)
OUTPUT SKEW
nCLK0
CLK0
nQ0:nQ4
Q0:Q4
tPD
PROPAGATION DELAY (DIFFERENTIAL INPUT)
CLK1
nQ0:nQ4
Q0:Q4
tPD
PROPAGATION DELAY (LVCMOS INPUT)
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REV. B JULY 30, 2002
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PRELIMINARY
ICS85314I-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
INPUT AND OUTPUT RISE AND FALL TIME
nQ0:nQ4
Q0:Q4
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
odc & tPERIOD
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PRELIMINARY
ICS85314I-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 2 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECLcompatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
5
2
5
Zo
Zo
2
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
➤
V
CC - 2V
Zo = 50Ω
RTT
1
3
2
3
2
Zo
RTT =
Zo
Zo
(VOH + VOL / VCC –2) –2
FIGURE 3A - LVPECL OUTPUT TERMINATION
FIGURE 3B - LVPECL OUTPUT TERMINATION
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PRELIMINARY
ICS85314I-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85314I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85314I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 55mA = 209mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power_MAX (3.465V, with all outputs switching) = 209mW + 151mW = 360mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6Abelow.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.360W * 66.6°C/W = 109°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE qJA FOR 20-PIN TSSOP, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B. THERMAL RESISTANCE qJA FOR 20-PIN SOIC, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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PRELIMINARY
ICS85314I-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CC_MAX
)
= 1.0V
OH_MAX
(V
- V
CC_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
/R ] * (V
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
/R ] * (V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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ICS85314I-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOW TABLE FOR TSSOP
q by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B. θJAVS. AIR FLOW TABLE FOR SOIC
q by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
65.7°C/W
39.7°C/W
57.5°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85314I-01 is: 674
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Integrated
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LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX
TABLE 8A. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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Integrated
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LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX
TABLE 8B. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
20
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
12.60
7.40
2.55
0.51
0.32
13.00
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119
85314AGI-01
www.icst.com/products/hiperclocks.html
REV. B JULY 30, 2002
14
PRELIMINARY
ICS85314I-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS85314AGI-01
ICS85314AGI-01T
ICS85314AMI-01
ICS85314AMI-01T
Marking
Package
20 lead TSSOP
Count
72 per tube
2500
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS85314AI01
ICS85314AI01
ICS85314AI-01
ICS85314AI-01
20 lead TSSOP on Tape and Reel
20 lead SOIC
38 per tube
1000
20 lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
85314AGI-01
www.icst.com/products/hiperclocks.html
REV. B JULY 30, 2002
15
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