ICS8533AGI-31T [IDT]
Clock Generator, 650MHz, PDSO20, 6.50 X 4.40 MM, 0.925 MM HEIGHT, MO-153, TSSOP-20;
| 型号： | ICS8533AGI-31T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 650MHz, PDSO20, 6.50 X 4.40 MM, 0.925 MM HEIGHT, MO-153, TSSOP-20 光电二极管 |
| 文件： | 总16页 (文件大小：966K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
ICS8533I-31
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
General Description
Features
The ICS8533I-31 is a low skew, high performance
• Four differential LVPECL output pairs
S
IC
1-to-4 Crystal Oscillator/Differential-to-3.3V
LVPECL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS8533I-31 has selectable
• Selectable differential CLK/nCLK or crystal oscillator interface
• Maximum output frequency: 650MHz
HiPerClockS™
• Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nCLK input
differential clock or crystal inputs. The CLK, nCLK pair can accept
most standard differential input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock enable
pin.
• Additive phase jitter, RMS: TBD
• Output skew: 25ps (typical)
• Part-to-part skew: 150ps (typical)
• Propagation delay: 1.5ns (typical)
• Full 3.3V supply mode
Guaranteed output and part-to-part skew characteristics make the
ICS8533I-31 ideal for those applications demanding well defined
performance and repeatability.
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
Pullup
CLK_EN
D
VEE
CLK_EN
CLK_SEL
CLK
1
2
20 Q0
Q
19
nQ0
LE
3
4
18
17
VCC
Q1
Pulludown
CLK
0
1
Q0
Pullup
nCLK
nCLK
XTAL_IN
XTAL_OUT
5
6
7
8
9
16 nQ1
nQ0
15
14
13
Q2
nQ2
VCC
XTAL_IN
Q1
nc
nc
VCC 10
OSC
nQ1
12 Q3
11
nQ3
XTAL_OUT
CLK_SEL
Q2
Pulludown
nQ2
ICS8533I-31
20-Lead TSSOP
Q3
6.5mm x 4.4mm x 0.925mm
package body
nQ3
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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ICS8533AGI-31 REV. A DECEMBER 13, 2007
ICS8533I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
PRELIMINARY
Table 1. Pin Descriptions
Number
Name
Type
Description
1
VEE
Power
Input
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS /
LVTTL interface levels.
2
CLK_EN
Pullup
Clock select input. When LOW, selects CLK, nCLK input.
When HIGH, selects XTAL input. LVCMOS / LVTTL interface levels.
3
CLK_SEL
Input
Pulldown
4
5
CLK
Input
Input
Pulldown Non-inverting differential clock input.
nCLK
Pullup
Inverting differential clock input.
6,
7
XTAL_IN
XTAL_OUT
Input
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
8, 9
10, 13, 18
11, 12
nc
Unused
Power
No connect.
VCC
Power supply pins.
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Output
Output
Output
Output
Differential clock output pair. LVPECL interface levels.
Differential clock output pair. LVPECL interface levels.
Differential clock output pair. LVPECL interface levels.
Differential clock output pair. LVPECL interface levels.
14, 15
16, 17
19, 20
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
PRELIMINARY
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
CLK, nCLK
Q0:Q3
Disabled; Low
Disabled; Low
Enabled
nQ0:nQ3
Disabled; High
Disabled; High
Enabled
0
0
1
1
0
1
0
1
XTAL_IN, XTAL_OUT
CLK, nCLK
XTAL_IN, XTAL_OUT
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or crystal oscillator edge as
shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and XTAL inputs as described in Table 3B.
Enabled
Disabled
nCLK
CLK
CLK_EN
nQ0:nQ3
Q0:Q3
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
nQ0:nQ3
CLK
nCLK
Q0:Q3
LOW
HIGH
LOW
HIGH
HIGH
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Single-ended to Differential
Single-ended to Differential
Single-ended to Differential
Single-ended to Differential
Polarity
Non inverting
Non inverting
Non inverting
Non inverting
Inverting
0
1
HIGH
LOW
HIGH
LOW
LOW
HIGH
1
0
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
PRELIMINARY
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
91.12°C/W (0 mps)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VEE = 3.3V 5ꢀ, VCC = 0V, TA = -40°C to 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum
Typical
3.3
Maximum
Units
V
Power Supply Voltage
Power Supply Current
3.135
3.465
IEE
40
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VEE = 3.3V 5ꢀ, VCC = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
VIH
VIL
Input High Voltage
2
VCC + 0.3
Input Low Voltage
-0.3
0.8
5
V
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
CC = VIN = 3.465V
VCC = VIN = 3.465V
CC = 3.465V, VIN = 0V
µA
µA
µA
µA
IIH
Input High Current
150
V
-150
-5
IIL
Input Low Current
VCC = 3.465V, VIN = 0V
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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ICS8533AGI-31 REV. A DECEMBER 13, 2007
ICS8533I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
PRELIMINARY
Table 4C. Differential DC Characteristics, VCC = 3.3V 5ꢀ, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
µA
nCLK
CLK
V
CC = VIN = 3.465V
5
IIH
Input High Current
VCC = VIN = 3.465V
150
µA
VCC = 3.465V,
VIN = 0V
nCLK
CLK
-150
-5
µA
µA
IIL
Input Low Current
V
CC = 3.465V,
VIN = 0V
VPP
Peak-to-Peak Voltage; NOTE 1
0.15
1.3
V
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC – 0.85
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVPECL DC Characteristics, VCC = 3.3V 5ꢀ, VEE = 0V, TA = -40°C to 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC – 1.4
VCC – 2.0
0.6
Typical
Maximum
VCC – 0.9
VCC – 1.7
1.0
Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
V
V
V
VOL
VSWING
NOTE 1: Output termination with 50Ω to VCC – 2V.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Frequency
Fundamental
14
25
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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ICS8533AGI-31 REV. A DECEMBER 13, 2007
ICS8533I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
PRELIMINARY
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = 3.3V 5ꢀ, VEE = 0V, TA = -40°C to 85°C
Parameter
fMAX
Symbol
Test Conditions
Minimum
Typical
Maximum
650
Units
MHz
ns
Output Frequency
Propagation Delay; NOTE 1
tPD
IJ 650MHz
1.5
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
650MHz, (Integration Range:
1.875MHz – 20MHz)
tjit
TBD
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 5
Part-to-Part Skew; NOTE 3, 5
Output Rise/Fall Time
Output Duty Cycle
25
ps
ps
ps
ꢀ
150
20ꢀ to 80ꢀ @ 50MHz
300
700
50
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: Measured using CLK. For XTAL input, refer to Application Note.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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ICS8533AGI-31 REV. A DECEMBER 13, 2007
ICS8533I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
PRELIMINARY
Parameter Measurement Information
2V
V
CC
SCOPE
nCLK
V
Qx
CC
VPP
VCMR
Cross Points
CLK
LVPECL
nQx
V
EE
VEE
-1.3V 0.165V
3.3V LVPECL Output Load AC Test Circuit
Differential Input Level
nQx
Qx
nCLK
CLK
nQy
nQ0:nQ3
Qy
Q0:Q3
tPD
tsk(o)
Output Skew
Propagation Delay
nQ0:nQ3
80ꢀ
80ꢀ
Q0:Q3
tPW
VSWING
20ꢀ
tPERIOD
Clock
20ꢀ
Outputs
tF
tR
tPW
tPERIOD
odc =
x 100ꢀ
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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ICS8533AGI-31 REV. A DECEMBER 13, 2007
ICS8533I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
PRELIMINARY
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVPECL OUTPUTS
All control pins have internal pull-ups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to
ground.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how the differential input can be wired to accept
single-ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and
VDD
R1
1K
Single Ended Clock Input
R2/R1 = 0.609.
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
PRELIMINARY
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
HiPerClockS
Input
nCLK
LVPECL
HiPerClockS
LVHSTL
R1
50
R2
50
Input
R1
50
R2
50
IDT
HiPerClockS
LVHSTL Driver
R2
50
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
nCLK
nCLK
Zo = 50Ω
HiPerClockS
Input
LVPECL
Receiver
LVDS
R1
84
R2
84
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
2.5V
3.3V
3.3V
2.5V
R3
R4
120
120
Zo = 50Ω
*R3
*R4
33
33
Zo = 60Ω
Zo = 60Ω
CLK
CLK
Zo = 50Ω
nCLK
nCLK
HiPerClockS
HiPerClockS
Input
SSTL
HCSL
R1
50
R2
50
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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ICS8533AGI-31 REV. A DECEMBER 13, 2007
ICS8533I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
PRELIMINARY
Crystal Input Interface
A crystal can be characterized for either series or parallel mode
operation. The ICS8533I-31 fanout buffer has a built-in crystal
oscillator circuit. This interface can accept either a series or parallel
crystal without additional components as shown in Figure 4. The
physical location of the crystal should be located as close as
possible to the XTAL_IN and XTAL_OUT pins. The experiments
show that using a 19.44MHz crystal results in an output frequency
of 19.4404746MHz and approximately 44ꢀ of duty cycle.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
Figure 4. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 5. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VCC
VCC
R1
0.1µf
50Ω
Ro
Rs
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 5. General Diagram for LVCMOS Driver to XTAL Input Interface
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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PRELIMINARY
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 6A and 6B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
Figure 6A. 3.3V LVPECL Output Termination
Figure 6B. 3.3V LVPECL Output Termination
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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PRELIMINARY
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8533I-31.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8533I-31 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 40mA = 138.6mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.3V, with all outputs switching) = 138.6mW + 60mW = 258.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 91.1°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.259W * 91.1°C/W = 108.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 7. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
91.1°C/W
86.7°C/W
84.6°C/W
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of VCC – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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ICS8533AGI-31 REV. A DECEMBER 13, 2007
ICS8533I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
PRELIMINARY
Reliability Information
Table 8. θJA vs. Air Flow Table for a 20 Lead TSSOP
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
91.1°C/W
86.7°C/W
84.6°C/W
Transistor Count
The transistor count for ICS8533I-31 is: TBD
Package Outline and Package Dimensions
Package Outline - G Suffix for 20-Lead TSSOP
Table 9. Package Dimensions for 20 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
20
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
14
ICS8533AGI-31 REV. A DECEMBER 13, 2007
ICS8533I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
PRELIMINARY
Ordering Information
Table 10. Ordering Information
Part/Order Number
8533AGI-31
8533AGI-31T
8533AGI-31LF
8533AGI-31LFT
Marking
ICS8533AGI31
ICS8533AGI31
TBD
Package
20 Lead TSSOP
20 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
TBD
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
15
ICS8533AGI-31 REV. A DECEMBER 13, 2007
ICS8533I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
PRELIMINARY
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