ICS8535AG-01LF [IDT]
Low Skew Clock Driver, 8535 Series, 4 True Output(s), 4 Inverted Output(s), PDSO20, ROHS COMPLIANT, 4.40 X 6.50 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20;
| 型号： | ICS8535AG-01LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 8535 Series, 4 True Output(s), 4 Inverted Output(s), PDSO20, ROHS COMPLIANT, 4.40 X 6.50 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总17页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-
3.3V LVPECL FANOUT BUFFER
ICS8535-01
GENERAL DESCRIPTION
FEATURES
• Four differential 3.3V LVPECL outputs
The ICS8535-01 is a low skew, high performance
ICS
HiPerClockS™
1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL fanout
• Selectable CLK0 or CLK1 inputs for redundant
and multiple frequency fanout applications
buffer and a member of the HiPerClockS™ family
of High Performance Clock Solutions from IDT. The
ICS8535-01 has two single ended clock inputs. the
single ended clock input accepts LVCMOS or LVTTL input lev-
els and translate them to 3.3V LVPECL levels. The clock en-
able is internally synchronized to eliminate runt clock pulses
on the output during asynchronous assertion/deassertion of
the clock enable pin.
• CLK0 or CLK1 can accept the following input levels: LVCMOS
or LVTTL
• Maximum output frequency: 266MHz
• Translates LVCMOS and LVTTL levels to
3.3V LVPECL levels
• Output skew: 30ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.9ns (maximum)
• Additve phase jitter, RMS: < 0.09ps (typical)
• 3.3V operating supply
Guaranteed output and part-to-part skew characteristics make
the ICS8535-01 ideal for those applications demanding well
defined performance and repeatability.
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VEE
CLK_EN
CLK_SEL
CLK0
nc
Q0
D
CLK_EN
nQ0
VCC
Q1
nQ1
Q2
nQ2
VCC
Q3
Q
LE
CLK0
CLK1
0
1
Q0
nQ0
CLK1
nc
Q1
nQ1
nc
nc
CLK_SEL
VCC
nQ3
Q2
nQ2
ICS8535-01
20-Lead TSSOP
Q3
4.4mm x 6.5mm x 0.92mm body package
G Package
nQ3
Top View
20 19 18 17 16
VCC
1
2
3
4
5
15
14
13
12
11
VCC
Q2
nQ3
Q3
VEE
nQ2
VCC
nc
CLK_EN
6
7
8
9
10
ICS8535-01
20-Lead VFQFN
4mm x 4mm x 0.9mm body package
K Package
Top View
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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TABLE 1. PIN DESCRIPTIONS
Name
Type
Description
VEE
Power
Input
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW,
Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK1 input. When LOW, selects CLK0 input.
LVCMOS / LVTTL interface levels.
CLK_EN
Pullup
Pulldown
CLK_SEL
Input
CLK0
CLK1
Input
Input
Pulldown LVCMOS / LVTTL clock input.
Pulldown LVCMOS / LVTTL clock input.
No connect.
nc
Unused
Power
Output
Output
Output
Output
VCC
Positive supply pins.
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
kΩ
kΩ
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
CLK0
Q0:Q3
Disabled; LOW
Disabled; LOW
Enabled
nQ0:nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
0
0
1
1
0
1
0
1
CLK1
CLK0
CLK1
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as show in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B.
Enabled
Disabled
CLK0, CLK1
CLK_EN
nQ0:nQ3
Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
CLK0 or CLK1
Q0:Q3
LOW
nQ0:nQ3
HIGH
0
1
HIGH
LOW
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
20 Lead TSSOP
20 Lead VFQFN
JA
73.2°C/W (0 lfpm)
60.4°C/W (0 mps)
Storage Temperature, T
-65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
3.135
3.3
3.465
50
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CLK0, CLK1
2
V
CC + 0.3
CC + 0.3
1.3
V
V
VIH
VIL
IIH
Input High Voltage
CLK_EN, CLK_SEL
CLK0, CLK1
2
V
-0.3
-0.3
V
Input Low Voltage
Input High Current
Input Low Current
CLK_EN, CLK_SEL
CLK0, CLK1, CLK_SEL
CLK_EN
0.8
V
V
IN = VCC = 3.465V
IN = VCC = 3.465V
150
µA
µA
µA
µA
V
5
CLK0, CLK1, CLK_SEL
CLK_EN
V
V
IN = 0V, VCC = 3.465V
IN = 0V, VCC = 3.465V
-5
IIL
-150
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 1.4
VCC - 2.0
0.6
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum
266
Units
MHz
ns
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
IJ 266MHz
1.0
1.9
tsk(o)
tsk(pp)
11
30
ps
Part-to-Part Skew; NOTE 3, 4
250
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
tjit
0.09
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ @ 50MHz
300
48
700
52
ps
ꢀ
50
All parameters measured at 266MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the VCC/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Driving only one input clock.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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ADDITIVE PHASE JITTER
band to the power in the fundamental. When the required offset
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications.Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
Input/Output Additive Phase Jitter
at 156.25MHz = 0.09ps (typical)
-50
-60
-70
-80
-90
-100
-110
-120
-130
140
-
-150
160
-
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
PART 1
nQx
SCOPE
VCC
Qx
Qx
PART 2
nQy
LVPECL
nQx
VEE
Qy
tsk(pp)
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW
nQx
Qx
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
Clock
20ꢀ
nQy
Outputs
Qy
tsk(o)
OUTPUT RISE/FALL TIME
OUTPUT SKEW
nQ0:nQ3
Q0:Q3
CLK0,
CLK1
tPW
tPERIOD
nQ0:nQ3
Q0:Q3
tPW
tPD
odc =
x 100ꢀ
tPERIOD
PROPAGATION DELAY
OUTPUT DUTY CYCLE/ PULSE WIDTH/PERIOD
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK INPUT:
LVPECL OUTPUT
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal dis-
tortion. Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board design-
ers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of the ICS8535-01. In this
should be physically located near the power pin. For ICS8535-01,
example, the CLK0 input is selected. The decoupling capacitors
the unused clock outputs can be left floating.
Zo = 50
Zo = 50
+
-
3.3V
R2
50
R1
50
R12
1K
3.3V
U1
R3
50
Q1
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
VEE
Q0
nQ0
VCC
Q1
nQ1
Q2
nQ2
VCC
Q3
CLK_EN
CLK_SEL
CLK0
NC
CLK1
NC
NC
NC
VCC
Ro
~
7
Ohm
3.3V
3.3V
Zo = 50 Ohm
R13 43
R11
1K
LVCMOS
3.3V
C1
10
nQ3
0.1u
ICS8535-01
3.3V
Zo = 50
Zo = 50
+
-
C2
0.1u
C3
0.1u
R8
50
R7
50
R9
50
FIGURE 3. ICS8535-01 LVPECL BUFFER SCHEMATIC EXAMPLE
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8535-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8535-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 50mA = 173.25mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 4 x 30mW = 120mW
Total Power
(3.465V, with all outputs switching) = 173.25mW + 120mW = 293.25mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.293W * 66.6°C/W = 89.5°C. This is well below the limit of 125°C.
This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply
voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE θ FOR 20-LEAD TSSOP, FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B. θ VS. AIR FLOW TABLE FOR 20 LEAD VFQFN
JA
θ by Velocity (Meters per Second)
JA
0
1
3
Multi-Layer PCB, JEDEC Standard Test Boards
60.4°C/W
52.8°C/W
46.0°C/W
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, V = V
= V
– 0.9V
CC_MAX
OUT
OH_MAX
)
= 0.9V
OH_MAX
(V
- V
CC_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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RELIABILITY INFORMATION
TABLE 7A. θ VS. AIR FLOW TABLE FOR 20 LEAD TSSOP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B. θ VS. AIR FLOW TABLE FOR 20 LEAD VFQFN
JA
θ by Velocity (Meters per Second)
JA
0
1
3
Multi-Layer PCB, JEDEC Standard Test Boards
60.4°C/W
52.8°C/W
46.0°C/W
TRANSISTOR COUNT
The transistor count for ICS8535-01 is: 412
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8A. PACKAGE DIMENSIONS FOR TSSOP
Millimeters
SYMBOL
Minimum
Maximum
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153
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PACKAGE OUTLINE - K SUFFIX FOR 20 LEAD VFQFN
TABLE 8B. PACKAGE DIMENSIONS FOR 20 LEAD VFQFN
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
20
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
NE
D
5
5
4.0
D2
E
0.75
2.80
4.0
E2
L
0.75
0.35
2.80
0.75
Reference Document: JEDEC Publication 95, MO-220
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS8535AG-01
Marking
ICS8535AG-01
ICS8535AG-01
ICS8535A01LF
ICS8535A01LF
535A01
Package
Shipping Packaging Temperature
20 lead TSSOP
tube
2500 tape & reel
tube
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS8535AG-01T
ICS8535AG-01LF
ICS8535AG-01LFT
ICS8535AK-01
20 lead TSSOP
20 lead "Lead Free" TSSOP
20 lead "Lead Free" TSSOP
20 lead VFQFN
2500 tape & reel
tube
ICS8535AK-01T
ICS8535AK-01LF
ICS8535AK-01LFT
535A01
20 lead VFQFN
2500 tape & reel
tube
35A01L
20 lead "Lead-Free" VFQFN
20 lead "Lead-Free" VFQFN
35A01L
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
15
ICS8535AG-01 REV. F APRIL 12, 2007
ICS8535-01
LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
B
Table
Page
Description of Change
Updated Figure 1 - CLK_EN Timing Diagram.
Date
3
3
8
10/16/01
10/29/01
5/29/02
B
Updated Figure 1 - CLK_EN Timing Diagram.
Added Termination for LVPECL Outputs section.
B
Output Load Test Circuit - corrected VEE equation to read
"VEE = -0.5V 0.165V" from "VEE = -0.5V 0.135V".
AC Characteristics table - changed tsk(pp) from 150ps max. to 250ps. max.
Update format.
B
C
6
5
10/4/02
T5
12/13/02
8
4
4
8
Added Schematic layout in the Application Section.
LVCMOS Table - changed VIH 3.765V Max. to VCC + 0.3V Max.
LVPECL Table - changed VSWING 0.85V Max. to 1.0V Max.
D
D
1/20/03
4/1/03
Schematic Example, changed sentence to read "In this example, the XTAL
input is selected." to "..., The CLK1 input is selected."
Corrected schematic example.
1
2
Added RMS Jitter to Features section.
T2
T5
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
Revised Absolute Maximum Ratings Output.
AC Characteritsics Table - added RMS Jitter.
Added Additive Phase Jitter Section.
4
E
9/19/03
5
6
8
Revised LVPECL Output Termination diagrams.
Added "Lead Free" Part/Order Number rows.
E
E
14
11/13/03
12/4/03
14
1
Corrected "Lead Free" marking and order/part numbers.
Added Lead Free bullet in the Features section.
E
E
6/17/04
9/17/04
T5
T9
5
AC Characteristics table - added Note 5.
14
1
Corrected Lead Free marking in Ordering Information Table.
Pin Assignment - added 20 Lead VFQFN package information.
Added 20 Lead VFQFN Reliability Information.
T7B
T8B
T9
12
14
15
15
E
10/7/04
Added 20 Lead VFQFN Package Outline and Dimensions.
Ordering Information Table - added 20 Lead VFQFN ordering information.
Ordering Information Table - added "Lead-Free/Annealed" part number.
E
E
T9
10/11/04
11/22/04
T9
15
Ordering Information Table - deleted "Lead-Free/Annealed" part number.
Pin Assignment - corrected letter package for 20 Lead VFQFN from
E
E
1
12/8/04
5/24/05
"G Package" to "K Package".
Ordering Information Table - corrected marking on TSSOP Lead-Free package
and added Lead-Free note.
15
T9
8
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - corrected 20 Lead VFQFN marking and added
Lead-Free 20 Lead VFQFN part number.
E
E
T9
T9
9/16/05
3/21/06
15
15
4
Ordering Information Table - corrected 20 Lead VFQFN Shipping Packaging.
Absolute Maximum Ratings - corrected 20 lead VFQFN Package Thermal
Impedance.
E
F
10/02/06
4/12/07
T6B
10
Corrected 20 lead VFQFN Theta JA.
T7B
T4C
12
4
Corrected 20 lead VFQFN Theta JA.
LVPECL DC Characteristics Table -corrected VOH max. from VCC - 1.0V to
V
CC - 0.9V.
10 - 11 Power Considerations - corrected power dissipation to reflect VOH max in Table
4C.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
16
ICS8535AG-01 REV. F APRIL 12, 2007
ICS8535-01
LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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