ICS854057AGLF [IDT]
Low Skew Clock Driver, 854057 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 4.40 X 6.50 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20;
| 型号： | ICS854057AGLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 854057 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 4.40 X 6.50 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS854057 is a 4:1 or 2:1 LVDS Clock Mul- • High speed differential multiplexer.The device can be
ICS
tiplexer which can operate up to 2GHz and is a
member of the HiPerClockS™family of High Per-
formance Clock Solutions from ICS.The PCLK,
nPCLK pairs can accept most standard differen-
configured as either a 4:1 or 2:1 multiplexer
HiPerClockS™
• Single LVDS output
• 4 selectable PCLK, nPCLK inputs with internal termination
tial input levels. Internal termination is provided on each dif-
ferential input pair.The ICS854057 operates using a 2.5V sup-
ply voltage. The fully differential architecture and low propa-
gation delay make it ideal for use in high speed multiplexing
applications.The select pins have internal pulldown resistors.
Leaving one input unconnected (pulled to logic low by the in-
ternal resistor) will transform the device into a 2:1 multiplexer.
The SEL1 pin is the most significant bit and the binary num-
ber applied to the select pins will select the same numbered
data input (i.e., 00 selects PCLK0, nPCLK0).
• PCLK, nPCLK pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
• Output frequency: >2GHz
• Part-to-part skew: 200ps (maximum)
• Propagation delay: 800ps (maximum)
• Additive phase jitter, RMS: 66fs (typical)
• 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
VT0
20
19
18
17
16
15
14
13
12
11
VDD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
1
2
3
4
5
6
7
8
9
VDD
PCLK3
VT3
nPCLK3
Q
nQ
PCLK2
VT2
nPCLK2
GND
50
PCLK0
50
nPCLK0
VT1
50
50
nPCLK1
PCLK1
nPCLK1
GND 10
00
01
10
11
ICS854057
VT2
Q
nQ
20-LeadTSSOP
4.40mm x 6.50mm x 0.925mm body package
G Package
50
50
50
PCLK2
nPCLK2
TopView
VT3
50
PCLK3
nPCLK3
Pulldown
Pulldown
SEL1
SEL0
854057AG
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REV. A JULY 18, 2005
1
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 20
2
Name
VDD
Type
Description
Power
Input
Positive supply pins.
PCLK0
Non-inverting LVPECL differential clock input. RT = 50Ω termination to VT0.
Termination input. For LVDS input, leave floating.
RT = 50Ω termination to VT0.
3
VT0
Input
4
5
6
7
nPCLK0
SEL1
Input
Input
Input
Input
Inverting LVPECL differential clock input. RT = 50Ω termination to VT0
Pulldown Clock select input. LVCMOS / LVTTL interface levels.
Pulldown Clock select input. LVCMOS / LVTTL interface levels.
Non-inverting LVPECL differential clock input. RT = 50Ω termination to VT1.
SEL0
PCLK1
Termination input. For LVDS input, leave floating.
RT = 50Ω termination to VT1.
8
VT1
Input
9
nPCLK1
GND
Input
Power
Input
Inverting LVPECL differential clock input. RT = 50Ω termination to VT1.
10, 11
12
Power supply ground.
nPCLK2
Inverting LVPECL differential clock input. RT = 50Ω termination to VT2.
Termination input. For LVDS input, leave floating.
RT = 50Ω termination to VT2.
13
VT2
Input
14
15, 16
17
PCLK2
nQ, Q
Input
Output
Input
Non-inverting LVPECL differential clock input. RT = 50Ω termination to VT2.
Differential output pairs. LVDS interface levels.
nPCLK3
Inverting LVPECL differential clock input. RT = 50Ω termination to VT3.
Termination input. For LVDS input, leave floating.
RT = 50Ω termination to VT3.
Non-inverting LVPECL differential clock input. RT = 50Ω termination to VT3.
18
19
VT3
Input
Input
PCLK3
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
CIN
Input Capacitance
1.5
50
50
pF
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
RT
Input Termination Resistor
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs
Clock Out
SEL1
SEL0
PCLKx/nPCLKx
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK2, nPCLK2
PCLK3, nPCLK3
0
0
1
1
0
1
0
1
854057AG
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REV. A JULY 18, 2005
2
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
PackageThermal Impedance, θ
73.2°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
IDD
Positive Supply Voltage
Power Supply Current
2.375
2.5
2.625
60
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
0.7 * VDD
-0.3
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
VDD + 0.3
0.3 * VDD
150
V
V
Input Low Voltage
Input High Current SEL0, SEL1
Input Low Current SEL0, SEL1
VDD = VIN = 2.625V
µA
µA
IIL
VDD = 2.625V, VIN = 0V
-150
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VDD = VIN = 2.625V
VDD = 2.625V, VIN = 0V
Minimum Typical Maximum Units
IIH
Input High Current
150
µA
µA
V
IIL
Input Low Current
-150
0.15
1.2
VPP
VCMR
Peak-to-Peak Voltage
1.2
VDD
Common Mode Input Voltage; NOTE 1, 2
V
NOTE 1: Common mode input voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VDD + 0.3V.
854057AG
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REV. A JULY 18, 2005
3
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
Integrated
Circuit
Systems, Inc.
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions
Minimum
Typical
325
4
Maximum Units
VOD
Differential Output Voltage
225
425
35
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.125
1.25
5
1.375
25
Δ VOS
VOS Magnitude Change
mV
TABLE 5. AC CHARACTERISTICS, VDD = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol
fMAX
Parameter
Test Conditions
Minimum Typical Maximum Units
Output Frequency
Propagation Delay; NOTE 1
>2
GHz
ps
tPD
300
800
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
622.08MHz,
12kHz - 20MHz
tjit
66
fs
tsk(i)
Input Skew
40
200
250
53
ps
ps
tsk(pp)
tR / tF
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
20ꢀ to 80ꢀ
50
47
49
ps
ꢀ
odc
Output Duty Cycle
≤ 700MHz
51
ꢀ
muxISOLATION MUX Isolation
f = 500MHz
-55
dBm
NOTE: All parameters are measured at IJ1.9GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the output is measured
at the differential cross point.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
854057AG
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REV. A JULY 18, 2005
4
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
Integrated
Circuit
Systems, Inc.
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
Additive Phase Jitter @ 622.08MHz
(12kHz to 20MHz)
= 66fs typical
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
500M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
854057AG
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REV. A JULY 18, 2005
5
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
VDD
VDD
nPCLK0:
nPCLK3
SCOPE
Qx
VPP
VCMR
Cross Points
2.5V 5ꢀ
POWER SUPPLY
LVDS
PCLK0:
PCLK3
+
Float GND
-
nQx
GND
2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nPCLKx
PCLKx
nPCLKy
nQ
PART 1
Q
nQ
PCLKy
PART 2
Q
nQ
Q
tsk(pp)
tPD2
tPD1
tsk(i)
tsk(i) = |tPD1 - tPD2
|
INPUT SKEW
PART-TO-PART SKEW
nPCLK0:
nPCLK3
nQ
PCLK0:
PCLK3
Q
tPW
tPERIOD
nQ
Q
tPW
tPERIOD
tPD
odc =
x 100ꢀ
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
854057AG
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REV. A JULY 18, 2005
6
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
Integrated
Circuit
Systems, Inc.
VDD
➤
out
80ꢀ
tF
80ꢀ
tR
LVDS
DC Input
100
V
OD/Δ VOD
VOD
Clock
Outputs
➤
20ꢀ
20ꢀ
out
OUTPUT RISE/FALL TIME
DIFFERENTIAL OUTPUT VOLTAGE SETUP
VDD
out
out
➤
DC Input
LVDS
VOS/Δ VOS
➤
OFFSET VOLTAGE SETUP
854057AG
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REV. A JULY 18, 2005
7
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
2.5V LVDS DRIVER TERMINATION
Figure 1 shows a typical termination for LVDS driver in charac- sion line environment. For buffer with multiple LDVS driver, it is
teristic impedance of 100Ω differential (50Ω single) transmis- recommended to terminate the unused output.
2.5V
2.5V
LVDS_Driv er
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 1. TYPICAL LVDS DRIVER TERMINATION
2.5V DIFFERENTIAL INPUT WITH BUILT-IN 50Ω TERMINATION UNUSED INPUT HANDLING
To prevent oscillation and to reduce noise, it is recommended to
have pull up and pull down connected to true and complement of
the unused input as shown in Figure 2.
2.5V
2.5V
R1
680
PCLK
VT
nPCLK
Receiver
with
Built-In
50 Ohm
R2
680
FIGURE 2. UNUSED INPUT HANDLING
854057AG
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REV. A JULY 18, 2005
8
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
Integrated
Circuit
Systems, Inc.
LVPECL INPUT WITH BUILT-IN 50Ω TERMINATIONS INTERFACE
The PCLK /nPCLK with built-in 50Ω terminations accepts
LVDS, LVPECL, LVHSTL, CML, SSTL and other differential
signals. Both VSWING and VOH must meet the VPP and VCMR
input requirements. Figures 3A to 3E show interface
50Ω terminations driven by the most common driver types.The
input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to
examples for the HiPerClockS PCLK/nPLCK input with built-in confirm the driver termination requirements.
2.5V
2.5V
3.3V or 2.5V
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
nIN
VT
nIN
Receiver
With
Receiver
With
Built-In
50 Ohm
2.5V LVPECL
LVDS
R1
18
Built-In
50 Ohm
FIGURE 3A. HIPERCLOCKS PCLK/nPCLK INPUT WITH
FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN LVDS DRIVER
BUILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER
2.5V
2.5V
2.5V
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
nIN
VT
nIN
Receiver
With
Receiver
With
CML - Built-in 50 Ohm Pull-up
CML - Open Collector
Built-In
50 Ohm
Built-In
50 Ohm
FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN OPEN COLLECTOR
CML DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT WITH
BUILT-IN 50Ω DRIVEN BY A CML DRIVER
WITH BUILT-IN 50Ω PULLUP
2.5V
2.5V
Zo = 50 Ohm
R1
R2
25
25
IN
VT
Zo = 50 Ohm
nIN
Receiver With Built-In 50Ω
SSTL
FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN SSTL DRIVER
854057AG
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REV. A JULY 18, 2005
9
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
Integrated
Circuit
Systems, Inc.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
PCLK/nPCLK INPUT:
OUTPUTS:
LVDS OUTPUT
For applications not requiring the use of a differential input, both All unused LVDS outputs can be left floating.We recommend
the PCLK and nPCLK pins can be left floating. Though not that there is no trace attached. Both sides of the differential
required, but for additional protection, a 1kΩ resistor can be tied output pair should either be left floating or terminated.
from PCLK to ground.
SCHEMATIC EXAMPLE
Figure 4shows a schematic example of the ICS854057. In this
example, the PCLK0/nPCLK0 and PCLK1/nPCLK1 inputs are
used. The decoupling capacitors should be physically located
near the power pin.
VDD
VDD
VDD
LVDS
VDD
VDD
U1
ICS854057
R1
680
R3
680
R1
1K
Zo = 50
Zo = 50
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
VDD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
nPCLK1
GND
VDD
PCLK3
VT3
nPCLK3
Q
nQ
PCLK2
VT2
+
-
Zo = 50
Zo = 50
R5
100
VDD
nPCLK2
GND
10
LVDS
Zo = 50
Zo = 50
R2
680
R4
680
R1
1K
R6
18
VDD
(U1,1)
(U1,20)
C2
LVPECL
C1
0.1u
0.1u
VDD=2.5V
FIGURE 4. EXAMPLE ICS854057 LVDS SCHEMATIC
854057AG
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REV. A JULY 18, 2005
10
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS854057 is: 346
854057AG
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REV. A JULY 18, 2005
11
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
854057AG
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REV. A JULY 18, 2005
12
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS854057AG
ICS854057AGT
ICS854057AGLF
ICS854057AGLFT
ICS854057AG
ICS854057AG
ICS854057AGL
ICS854057AGL
20 lead TSSOP
20 lead TSSOP
2500 tape & reel
tube
20 lead "Lead-Free" TSSOP
20 lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
854057AG
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REV. A JULY 18, 2005
13
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