ICS86953AYILFT [IDT]
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32;
| 型号： | ICS86953AYILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总11页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS86953I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS86953I is a low voltage, low skew 1-to-9 • 9 single ended LVCMOS outputs; (8) clocks, (1) feedback
,&6
Differential-to-LVCMOS clock generator and a
• Selectable differential PCLK, nPCLK or external feedback
member of the HiPerClockS™ family of High Per-
clock inputs
HiPerClockS™
formance Clock Solutions from ICS. The PCLK,
nPCLK pair can accept most standard differential
• FB_CLK can accept the following input levels:
LVCMOS and LVTTL
input levels. With output frequencies up to 110MHz, the
ICS86953I is targeted for high performance clock applications.
Along with a fully integrated PLL, the ICS86953I contains fre-
quency configurable outputs and an external feedback input for
regenerating clocks with “zero delay”.
• PCLK, nPCLK pair can accept the following differential
input levels: LVPECL, CML, SSTL
• Maximum output frequency: PLL Mode, 110MHz
• VCO range: 200MHz to 500MHz
• Output skew: 150ps (maximum)
• Cycle-to-cycle jitter: 100ps (maximum)
• Static phase offset: TBD ± 100ps
• 3.3V supply voltage
PIN ASSIGNMENT
• -40°C to 85°C ambient operating temperature
• Pin compatible to the MPC953
32 31 30 29 28 27 26 25
VDDA
FB_CLK
nc
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q1
VDDO
Q2
nc
GND
Q3
ICS86953I
nc
nc
VDDO
Q4
GND
PCLK
GND
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
BLOCK DIAGRAM
QFB
PCLK
nPCLK
0
1
0
1
7
Q0:Q6
Q7
/
0
1
Phase
Detector
÷4
LPF
VCO
FB_CLK
÷2
VCO_SEL
nBYPASS
MR/nOE
PLL_SEL
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
86953AYI
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REV. A APRIL 26, 2002
1
PRELIMINARY
ICS86953I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDDA
Type
Description
1
2
Power
Input
Analog supply pin.
FB_CLK
nc
Pullup
Feedback clock input.
No connect.
3, 4, 5, 6
Unused
Power
7, 13, 17,
21, 25, 29
GND
Power supply ground.
8
9
PCLK
Input
Input
Pullup
Non-inverting differential clock input.
nPCLK
Pulldown Inverting differential clock input.
Master reset and output enable. Resets dividers. Enables
and disables all outputs. LVCMOS / LVTTL interface levels.
10
MR/nOE
VDDO
Input
Power
Output
Pulldown
11, 15, 19, 23, 27
Output supply pins.
12, 14, 16, 18,
20, 22, 24, 26
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Clock outputs. LVCMOS / LVTTL interface levels.
14Ω typical output impedance.
Feedback clock output. LVCMOS / LVTTL interface levels.
14Ω typical output impedance.
28
QFB
Output
Selects VCO when HIGH. When LOW, selects PCLK,
nPCLK. LVCMOS / LVTTL interface levels.
30
31
32
PLL_SEL
nBYPASS
VCO_SEL
Input
Input
Input
Pullup
Pullup
Pullup
Selects PLL when HIGH. When LOW, in Bypass mode.
Selects VCO ÷2 when HIGH. Selects VCO ÷1 when LOW.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
pF
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
CPD
Power Dissipation Capacitance (per output)
VDDA, VDDO = 3.465V
TBD
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Input
Outputs
QFB, Q0:Q7
HiZ
MR/nOE
1
0
Enabled
TABLE 3B. PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE
Inputs
Outputs
QFB, Q0:Q7
CLK
Operation
Bypass
PLL_SEL VCO_SEL
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Test Mode: PLL and divider bypass
Test Mode: PLL bypass
Test Mode: PLL bypass
PLL Mode
CLK/4
CLK/8
VCO/4
PLL Mode
VCO/8
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REV. A APRIL 26, 2002
2
PRELIMINARY
ICS86953I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx
Inputs, VI
4.6V
-0.5V to VDDA + 0.5V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
47.9°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
VDDA
Parameter
Test Conditions
Minimum Typical Maximum Units
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Output Supply Current
3.135
3.135
3.3
3.3
16
3.465
3.465
V
VDDO
IDDA
V
mA
mA
IDDO
50
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCO_SEL, nBYPASS,
PLL_SEL, MR/nOE
2
VDD + 0.3
V
V
V
Input
VIH
High Voltage
FB_CLK
2
VDD + 0.3
VCO_SEL, nBYPASS,
PLL_SEL, MR/nOE
-0.3
-0.3
0.8
Input
VIL
Low Voltage
FB_CLK
MR/nOE
1.3
V
VDDA = V = 3.465V
150
µA
IN
Input
IIH
FB_CLK, VCO_SEL,
nBYPASS, PLL_SEL
High Current
V
DDA = V = 3.465V
5
µA
µA
µA
IN
MR/nOE
VDDA = 3.465V, V = 0V
-5
IN
Input
IIL
FB_CLK, VCO_SEL,
nBYPASS, PLL_SEL
Low Current
V
DDA = 3.465V, V = 0V
-150
2.6
IN
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
NOTE: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "3.3V Output Load Test Circuit".
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REV. A APRIL 26, 2002
3
PRELIMINARY
ICS86953I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
nPCLK
PCLK
V
DDA = VIN = 3.465V
150
5
µA
µA
µA
µA
V
IIH
Input High Current
VDDA = VIN = 3.465V
nPCLK
PCLK
VDDA = 3.465V, VIN = 0V
VDDA = 3.465V, VIN = 0V
-5
-150
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VDD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
110 MHz
fREF
Input Reference Frequency
TABLE 6. AC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VCO_SEL = 1
VCO_SEL = 0
Minimum Typical Maximum Units
PLL Mode
62.5
110
200
MHz
MHz
MHz
fMAX
Output Frequency
PLL Mode
Bypass Mode
Propagation Delay;
NOTE 1
tPD
PCLK, nPCLK
3
7
ns
ps
Measured on rising edge
at VDD/2
tsk(o)
Output Skew; NOTE 2, 4
150
tjitter(cc) Cycle-to-Cycle Jitter; NOTE 5
100
ps
ps
ns
ns
%
t(Ø)
tR
Static Phase Offset; NOTE 3, 5
Output Rise Time
TBD - 100
TBD
50
TBD + 100
20% to 80%
20% to 80%
0.1
0.1
45
1.0
1.0
55
10
6
tF
Output Fall Time
odc
tLOCK
tEN
Output Duty Cycle
PLL Lock Time
ms
ns
ns
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
tDIS
7
NOTE: Termination of 50Ω to VDD/2.
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A APRIL 26, 2002
4
PRELIMINARY
ICS86953I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
SCOPE
VDDA
VDDO
Qx
LVCMOS
GND
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
VDD
nPCLK
PCLK
VPP
VCMR
Cross Points
GND
DIFFERENTIAL INPUT LEVEL
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REV. A APRIL 26, 2002
5
PRELIMINARY
ICS86953I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
VDDO
2
Qx
Qy
VDDO
2
tsk(o)
OUTPUT SKEW
VDDO
2
VDDO
2
VDDO
2
QFB, Q0:Q7
➤
➤
tcycle n
tcycle n+1
➤
➤
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
Cycle-to-Cycle Jitter
VDDO
2
QFB, Q0:Q7
Pulse Width
tPERIOD
odc & tPERIOD
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REV. A APRIL 26, 2002
6
PRELIMINARY
ICS86953I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
nPCLK
PCLK
VDDO
2
QFB, Q0:Q7
➤
tPD
➤
PROPAGATION DELAY
PCLK
VOH
VOL
nPCLK
VOH
VDDO
2
VOL
FB_CLK
➤
t(Ø)
➤
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
PHASE JITTER AND STATIC PHASE OFFSET
2V
2V
0.8V
0.8V
Clock Inputs
and Outputs
tR
tF
INPUT AND OUTPUT RISE AND FALL TIME
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REV. A APRIL 26, 2002
7
PRELIMINARY
ICS86953I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 1 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
3.3V
vulnerable to random noise. The ICS86953 provides separate
power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDDA and VDDO should be individually
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required. Figure 2
illustrates how a 10Ω resistor along with a 10µF and a .01µF
bypass capacitor should be connected to each VDDA pin.
VDDO
.01µF
.01µF
10Ω
VDDA
10 µF
FIGURE 2 - POWER SUPPLY FILTERING
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REV. A APRIL 26, 2002
8
PRELIMINARY
ICS86953I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS86953I is: 1758
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REV. A APRIL 26, 2002
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PRELIMINARY
ICS86953I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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REV. A APRIL 26, 2002
10
PRELIMINARY
ICS86953I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS86953AYI
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
-40°C to 85°C
-40°C to 85°C
ICS86953AYI
ICS86953AYI
ICS86953AYIT
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. A APRIL 26, 2002
11
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