ICS87002AG-02LFT [IDT]
PLL Based Clock Driver, 87002 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-153, TSS0P20;
| 型号： | ICS87002AG-02LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 87002 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-153, TSS0P20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总16页 (文件大小：709K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1:2, Differential-to-LVCMOS/LVTTL
Zero Delay Clock Generator
ICS87002-02
DATA SHEET
General Description
Features
The ICS87002-02 is a highly versatile 1:2 Differential-to-
• Two LVCMOS/LVTTL outputs, 7Ω typical output impedance
LVCMOS/LVTTL Clock Generator. The ICS87002-02 has a
differential clock input. The CLK, nCLK pair can accept most
standard differential input levels. Internal bias on the nCLK input
allows the CLK input to accept LVCMOS/LVTTL. The ICS87002-02
has a fully integrated PLL and can be configured as zero delay
buffer, multiplier or divider and has an input and output frequency
range of 15.625MHz to 250MHz. The reference divider, feedback
divider and output divider are each programmable, thereby allowing
for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8. The external feedback allows the device to achieve
“zero delay” between the input clock and the output clocks. The
PLL_SEL pin can be used to bypass the PLL for system test and
debug purposes. In bypass mode, the reference clock is routed
around the PLL and into the internal output dividers.
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
• Internal bias on nCLK to support LVCMOS/LVTTL levels on CLK
input
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: 35ps (maximum)
• Static phase offset: -10ps 150ps (3.3V 5ꢀ)
• Full 3.3V or 2.5V operating supply
• 5V tolerant inputs
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
• Industrial temperature information available upon request
Block Diagram
Pin Assignment
Pullup
PLL_SEL
GND
Q0
1
2
20
19
VDDO
Q1
÷2, ÷4, ÷8, ÷16
Q0
VDDO
SEL0
3
4
18
17
GND
VDDO
0
÷32, ÷64, ÷128
SEL1
SEL2
SEL3
VDD
CLK
nCLK 10
5
6
7
8
9
16 nc
Pulldown
Pullup/Pulldown
CLK
nCLK
15
MR
Q1
1
14 FB_IN
13 PLL_SEL
PLL
12
11
VDDA
GND
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Pulldown
FB_IN
ICS87002-02
20-Lead TSSOP
6.50mm x 4.40mm x 0.925mm package body
G Package
Top View
Pulldown
SEL0
SEL1
SEL2
SEL3
MR
Pulldown
Pulldown
Pulldown
Pulldown
ICS87002AG-02 REVISION C AUGUST 9, 2010
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©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 11, 18
GND
Power
Output
Power
Input
Power supply ground.
Single-ended clock outputs. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
2, 19
Q0, Q1
VDDO
3, 17, 20
Output supply pins.
4, 5,
6, 7
SEL0, SEL1,
SEL2, SEL3
Pulldown
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
8
9
VDD
CLK
Power
Input
Core supply pin.
Pulldown
Non-inverting differential clock input.
Pullup/
Pulldown
10
12
nCLK
VDDA
Input
Inverting differential clock input. VDD/2 default when left floating.
Analog supply pin.
Power
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock (PLL Bypass). When HIGH, selects
PLL (PLL enabled). LVCMOS/LVTTL interface levels.
13
14
PLL_SEL
FB_IN
Input
Input
Pullup
Feedback input to phase detector for regenerating clocks with “Zero Delay.”
Connect to one of the outputs. LVCMOS/LVTTL interface levels.
Pulldown
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing
the outputs to go low. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
15
16
MR
nc
Input
Unused
No connect.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
kΩ
pF
RPULLDOWN Input Pulldown Resistor
VDD, VDDA, VDDO = 3.465V
23
17
12
Power Dissipation
CPD
Capacitance (per output)
V
DD, VDDA, VDDO = 2.625V
pF
ROUT
Output Impedance
5
7
Ω
ICS87002AG-02 REVISION C AUGUST 9, 2010
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©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Function Tables
Table 3A. PLL Enable Function Table
Outputs
PLL_SEL = 1
Inputs
SEL0
PLL Enable Mode
SEL3
SEL2
SEL1
Reference Frequency Range (MHz)
Q0, Q1
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
125 - 250
62.5 - 125
31.25 - 62.5
15.625 - 31.25
125 - 250
62.5 - 125
31.25 - 62.5
125 - 250
62.5 - 125
125 - 250
62.5 - 125
31.25 - 62.5
15.625 - 31.25
31.25 - 62.5
15.625 - 31.25
15.625 - 31.25
x2
x2
x4
x4
x8
ICS87002AG-02 REVISION C AUGUST 9, 2010
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©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q0, Q1
÷8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷8
÷8
÷16
÷16
÷16
÷32
÷32
÷64
÷128
÷4
÷4
÷8
÷2
÷4
÷2
ICS87002AG-02 REVISION C AUGUST 9, 2010
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©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C to 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
3.465
3.465
100
Units
V
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDDA
VDDO
IDD
3.135
3.3
V
3.135
3.3
V
mA
mA
mA
IDDA
16
IDDO
6
Table 4B. Power Supply DC Characteristics, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = 0°C to 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
2.625
2.625
96
Units
V
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDDA
VDDO
IDD
2.375
2.5
V
2.375
2.5
V
mA
mA
mA
IDDA
15
IDDO
6
ICS87002AG-02 REVISION C AUGUST 9, 2010
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©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDO = 3.3V 5ꢀ or 2.5V 5ꢀ, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
DD = 3.3V
VDD = 2.5V
DD = 3.3V
Minimum
Typical
Maximum
VDD + 0.3
VDD + 0.3
0.8
Units
V
2
V
V
V
V
VIH
Input High Voltage
1.7
-0.3
-0.3
V
VIL
Input Low Voltage
Input High Current
VDD = 2.5V
0.7
FB_IN,
SEL[0:3], MR
VDD = VIN = 3.465V or 2.625V
VDD = VIN = 3.465V or 2.625V
150
5
µA
µA
µA
IIH
PLL_SEL
FB_IN,
SEL[0:3], MR
V
DD = 3.465V or 2.625V,
-5
VIN = 0V
IIL
Input Low Current
VDD = 3.465V or 2.625V,
VIN = 0V
PLL_SEL
-150
µA
V
DDO = 3.465V
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDDO = 2.625V
VDDO = 3.465V or 2.625V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information Section, see Output Load Test Circuit Diagrams.
Table 4D. Differential DC Characteristics, VDD = VDDA = VDDO = 3.3V 5ꢀ or 2.5V 5ꢀ, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
150
Units
µA
µA
µA
µA
V
CLK
VDD = VIN = 3.465V or 2.625V
VDD = VIN = 3.465V or 2.625V
DD = 3.465V or 2.625V, VIN = 0V
DD = 3.465V or 2.625V, VIN = 0V
IIH
Input High Current
nCLK
CLK
150
V
V
-5
IIL
Input Low Current
nCLK
-150
0.15
VPP
Peak-to-Peak Voltage; NOTE 1
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
ICS87002AG-02 REVISION C AUGUST 9, 2010
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©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
15.625
250
MHz
PLL_SEL = 0V, f ≤ 250MHz,
tPD
Propagation Delay; NOTE 1
4.8
5.8
ns
ps
Qx ÷ 2
PLL_SEL = 3.3V,
t(Ø)
Static Phase Offset; NOTE 2, 4
-160
-10
140
f
REF ≤ 167MHz, Qx ÷ 1
tsk(o)
tjit(cc)
tL
Output Skew; NOTE 3, 4
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
PLL_SEL = 0V
40
45
1
ps
ps
ms
ps
ꢀ
fOUT > 40MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
40
800
60
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and
the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
15.625
250
MHz
PLL_SEL = 0V, f ≤ 250MHz,
tPD
Propagation Delay; NOTE 1
4.9
6.7
ns
ps
Qx ÷ 2
PLL_SEL = 2.5V,
t(Ø)
Static Phase Offset; NOTE 2, 4
-240
-65
110
f
REF ≤ 167MHz, Qx ÷ 1
tsk(o)
tjit(cc)
tL
Output Skew; NOTE 3, 4
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
PLL_SEL = 0V
35
45
1
ps
ps
ms
ps
ꢀ
fOUT > 40MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
44
700
56
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and
the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS87002AG-02 REVISION C AUGUST 9, 2010
7
©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Parameter Measurement Information
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
V
V
DD,
DD,
V
DDA,
V
DDA,
V
V
DDO
Qx
DDO
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V Output Load AC Test Circuit
2.5V Output Load AC Test Circuit
V
DD
VDDO
Qx
Qy
2
nCLK
VPP
VCMR
Cross Points
VDDO
2
CLK
tsk(o)
GND
Differential Input Level
Output Skew
nCLK
CLK
VOH
VOL
VDDO
2
VDDO
VDDO
2
2
Q0, Q1
VOH
VDDO
VO2L
➤
➤
tcycle n
tcycle n+1
➤
➤
FB_IN
➤
tjit(cc) = tcycle n – tcycle n+1
|
|
t(Ø)
➤
1000 Cycles
t(Ø) mean = Static Phase Offset
Where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on the controlled edges.
Cycle-to-Cycle Jitter
Static Phase Offset
ICS87002AG-02 REVISION C AUGUST 9, 2010
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©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Parameter Measurement Information, continued
nCLK
80ꢀ
tF
80ꢀ
tR
CLK
20ꢀ
20ꢀ
Q0, Q1
VDDO
2
Q0, Q1
t
PD
Propagation Delay
Output Rise/Fall Time
VDDO
2
Q0, Q1
tPW
tPERIOD
tPW
x 100ꢀ
odc =
tPERIOD
Output Duty Cycle/Pulse Width/Period
ICS87002AG-02 REVISION C AUGUST 9, 2010
9
©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Applications Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS87002-02 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD, VDDA and VDDO should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the VDDA pin. The 10Ω resistor can also be
replaced by a ferrite bead.
3.3V or 2.5V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VCC are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS87002AG-02 REVISION C AUGUST 9, 2010 10 ©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both differential signals must meet the VPP
and VCMR input requirements. Figures 3A to 3F show interface
examples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 3A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
Zo = 50Ω
nCLK
Differential
Input
nCLK
LVPECL
Differential
Input
R1
50Ω
R2
50Ω
LVHSTL
R1
50Ω
R2
50Ω
IDT
LVHSTL Driver
R2
50Ω
Figure 3A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 3B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
R3
R4
3.3V
125Ω
125Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100Ω
nCLK
nCLK
Differential
Input
Zo = 50Ω
LVPECL
Receiver
R1
84Ω
R2
84Ω
LVDS
Figure 3C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
2.5V
3.3V
3.3V
3.3V
2.5V
R3
R4
120Ω
120Ω
Zo = 50Ω
Zo = 60Ω
Zo = 60Ω
*R3
*R4
33Ω
33Ω
CLK
CLK
Zo = 50Ω
nCLK
nCLK
Differential
Input
SSTL
Differential
Input
HCSL
R1
50Ω
R2
50Ω
R1
120Ω
R2
120Ω
*Optional – R3 and R4 can be 0Ω
Figure 3E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 3F. CLK/nCLK Input Driven by a
2.5V SSTL Driver
ICS87002AG-02 REVISION C AUGUST 9, 2010
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©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Schematic Example
Figure 4 shows an example of ICS87002-02 application schematic.
In this example, the device is operated at VDD = 3.3V. The decoupling
capacitors should be located as close as possible to the power pin.
The input is driven by a 3.3V LVPECL driver.
Figure 4. ICS87002-02 Schematic Example
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVCMOS Outputs
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
All unused LVCMOS output can be left floating. There should be no
trace attached.
ICS87002AG-02 REVISION C AUGUST 9, 2010
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©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Reliability Information
Table 6. θJA vs. Air Flow Table for a 20 Lead TSSOP
θJA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS87002-02 is: 2578
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 7. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
20
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
α
0.45
0°
0.75
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS87002AG-02 REVISION C AUGUST 9, 2010
13
©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Ordering Information
Table 8. Ordering Information
Part/Order Number
87002AG-02
87002AG-02T
87002AG-02LF
87002AG-02LFT
Marking
Package
20 Lead TSSOP
20 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS87002AG02
ICS87002AG02
ICS87002A02L
ICS87002A02L
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
ICS87002AG-02 REVISION C AUGUST 9, 2010
14
©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Revision History Sheet
Rev
Table
Page
Description of Change
Date
T2
2
Pin Characteristics Table - added CPD specs.
Added Recommendations for Unused Input and Output Pins section.
Updated Differential Clock Input Interface section.
Added Schematic Layout
10
11
12
14
B
4/29/08
T8
Ordering Information Table - added Lead-Free marking.
T5A, T5B
T5B
7
7
Added thermal note.
2.5V AC Characteristics Table - due to datasheet conversion on April 29, 2008, corrected
typo for static phase offset spec from -650 to -65.
C
8/9/10
10
14
Updated Wiring the Differential Levels to Accept Single-ended Levels section.
Ordering Information Table - deleted “ICS” prefix from the Part/Order Number column.
Updated header/footer of datasheet.
T8
ICS87002AG-02 REVISION C AUGUST 9, 2010
15
©2010 Integrated Device Technology, Inc.
ICS87002-02 Data Sheet
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
We’ve Got Your Timing Solution
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
San Jose, California 95138
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2010. All rights reserved.
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