ICS87002AG-02 [IDT]
PLL Based Clock Driver, 87002 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, PLASTIC, MO-153, TSSOP-20;
| 型号： | ICS87002AG-02 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 87002 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, PLASTIC, MO-153, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS87002-02
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS87002-02 is a highly versatile 1:2 • Two LVCMOS/LVTTL outputs, 7Ω typical output impedance
ICS
HiPerClockS™
Differential-to-LVCMOS/LVTTL Clock Gen-
erator and a member of the HiPerClockS™
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
family of High Performance Clock Solutions
• Internal bias on nCLK to support LVCMOS/LVTTL levels on
CLK input
from ICS. The ICS87002-02 has a differen-
tial clock input. The CLK, nCLK pair can accept most
standard differential input levels. Internal bias on the
nCLK input allows the CLK input to accept LVCMOS/
LVTTL. The ICS87002-02 has a fully integrated PLL
and can be configured as zero delay buffer, multiplier
or divider and has an input and output frequency range
of 15.625MHz to 250MHz. The reference divider, feed-
back divider and output divider are each programmable,
thereby allowing for the following output-to-input fre-
quency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The exter-
nal feedback allows the device to achieve “zero delay”
between the input clock and the output clocks. The
PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the refer-
ence clock is routed around the PLL and into the
internal output dividers.
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: 35ps (maximum)
• Static phase offset: -10ps 150ps (3.3V 5ꢀ)
• Full 3.3V or 2.5V operating supply
• 5V tolerant inputs
• Industrial temperature information available upon request
• Availabe in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL
GND
Q0
VDDo
SEL0
VDDO
Q1
GND
VDDO
nc
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
÷2, ÷4, ÷8, ÷16
÷32, ÷64, ÷128
Q0
Q1
0
1
CLK
nCLK
SEL1
SEL2
SEL3
VDD
CLK
nCLK
MR
FB_IN
PLL_SEL
VDDA
GND
PLL
9
10
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
FB_IN
ICS87002-02
20-LeadTSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
Top View
SEL0
SEL1
SEL2
SEL3
MR
87002AG-02
www.icst.com/products/hiperclocks.html
REV.A OCTOBER 5, 2005
1
ICS87002-02
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 11, 18
GND
Power
Output
Power
Input
Power supply ground.
Clock outputs. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
2, 19
Q0, Q1
3, 17, 20
VDDO
Output supply pins.
4, 5,
6, 7
SEL0, SEL1,
SEL2, SEL3
Determines output divider values in Table 3.
LVCMOS/LVTTL interface levels.
Pulldown
8
9
VDD
Power
Input
Core supply pin.
CLK
Pulldown Non-inverting differential clock input.
Pullup/
10
12
nCLK
VDDA
Input
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
Power
Analog supply pin.
Selects between the PLL and reference clock as input to the dividers.
13
14
PLL_SEL
FB_IN
Input
Input
Pullup
When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
LVCMOS/LVTTL feedback input to phase detector for regenerating clocks
Pulldown with "zero delay". Connect to one of the outputs.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
Pulldown reset causing the outputs to go low. When logic LOW, the internal dividers
and the outputs are enabled. LVCMOS/LVTTL interface levels.
15
16
MR
nc
Input
Unused
No connect.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
4
Maximum Units
Input Capacitance
Input Pullup Resistor
pF
kΩ
kΩ
pF
pF
RPULLUP
51
RPULLDOWN Input Pulldown Resistor
51
VDD, VDDA, VDDO = 3.465V
VDD, VDDA, VDDO = 2.625V
TBD
TBD
7
Power Dissipation Capacitance
(per output)
CPD
ROUT
Output Impedance
5
12
Ω
87002AG-02
www.icst.com/products/hiperclocks.html
REV.A OCTOBER 5, 2005
2
ICS87002-02
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 3A. PLL ENABLE FUNCTION TABLE
Outputs
Inputs
SEL0
PLL_SEL = 1
PLL Enable Mode
SEL3
SEL2
SEL1
Reference Frequency Range (MHz)
Q0, Q1
÷ 1
÷ 1
÷ 1
÷ 1
÷ 2
÷ 2
÷ 2
÷ 4
÷ 4
÷ 8
x 2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
125 - 250
62.5 - 125
31.25 - 62.5
15.625 -31.25
125 - 250
62.5 - 125
31.25 - 62.5
125 - 250
62.5 - 125
125 - 250
62.5 - 125
31.25 - 62.5
15.625 - 31.25
31.25 - 62.5
15.625 - 31.25
15.625 - 31.25
x 2
x 2
x 4
x 4
x 8
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q0, Q1
÷ 8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷ 8
÷ 8
÷ 16
÷ 16
÷ 16
÷ 32
÷ 32
÷ 64
÷ 128
÷ 4
÷ 4
÷ 8
÷ 2
÷ 4
÷ 2
87002AG-02
www.icst.com/products/hiperclocks.html
REV.A OCTOBER 5, 2005
3
ICS87002-02
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
100
16
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
6
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD =VDDA =VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.375
2.375
2.375
2.5
2.5
2.5
2.625
2.625
2.625
96
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
15
6
87002AG-02
www.icst.com/products/hiperclocks.html
REV.A OCTOBER 5, 2005
4
ICS87002-02
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD = 3.3V
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
Input Low Voltage
V
DD = 2.5V
VDD = 3.3V
DD = 2.5V
DD = VIN = 3.465V,
VDD = VIN = 2.625V
DD = VIN = 3.465V,
DD = VIN = 2.625V
DD = 3.465V, VIN = 0V,
DD = 2.625V, VIN = 0V
DD = 3.465V, VIN = 0V,
DD = 2.625V, VIN = 0V
DDO = 3.465V
VDDO = 2.625V
VDDO = 3.465V or 2.625V
1.7
-0.3
-0.3
V
0.7
V
MR, FB_IN, SEL0:SEL3
150
5
µA
µA
µA
µA
Input
IIH
High Current
V
PLL_SEL
V
V
MR, FB_IN, SEL0:SEL3
PLL_SEL
-5
V
Input
Low Current
IIL
V
-150
V
V
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information Section,
see Output Load Test Circuit Diagrams.
TABLE 4D. DIFFERENTIAL DC CHARACTERISTICS, VDD =VDDA = VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VDD = VIN = 3.465V,
VDD = VIN = 2.625V
Minimum Typical Maximum Units
CLK
150
150
µA
µA
µA
µA
IIH
Input High Current
VDD = VIN = 3.465V,
VDD = VIN = 2.625V
nCLK
CLK
VDD = 3.465V, VIN = 0V,
VDD = 2.625V, VIN = 0V
VDD = 3.465V, VIN = 0V,
VDD = 2.625V, VIN = 0V
-5
IIL
Input Low Current
nCLK
-150
VPP
Peak-to-Peak Input Voltage
0.15
1.3
V
V
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
VDD - 0.85
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
87002AG-02
www.icst.com/products/hiperclocks.html
REV.A OCTOBER 5, 2005
5
ICS87002-02
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
15.625
250
MHz
Propagation Delay,
NOTE 1
PLL_SEL = 0V
f ≤ 250MHz, Qx ÷ 2
PLL_SEL = 3.3V
fREF ≤ 167MHz, Qx ÷ 1
CLK, nCLK
CLK, nCLK
CLK, nCLK
4.8
5.8
ns
Static Phase Offset;
NOTE 2, 4
t(Ø)
-160
-10
140
40
ps
ps
Output Skew;
NOTE 3, 4
tsk(o)
PLL_SEL = 0V
tjit(cc)
tL
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
f
OUT > 40MHz
45
1
ps
ms
ps
ꢀ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
40
800
60
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
15.625
250
MHz
Propagation Delay,
NOTE 1
PLL_SEL = 0V
f ≤ 250MHz, Qx ÷ 2
PLL_SEL = 2.5V
fREF ≤ 167MHz, Qx ÷ 1
CLK, nCLK
CLK, nCLK
CLK, nCLK
4.9
6.7
ns
Static Phase Offset;
NOTE 2, 4
t(Ø)
-240
-65
110
35
ps
ps
Output Skew;
NOTE 3, 4
tsk(o)
PLL_SEL = 0V
tjit(cc)
tL
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
f
OUT > 40MHz
45
1
ps
ms
ps
ꢀ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
44
700
56
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
87002AG-02
www.icst.com/products/hiperclocks.html
REV.A OCTOBER 5, 2005
6
ICS87002-02
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
VDD
,
VDD,
VDDA, VDDO
LVCMOS
GND
VDDA, VDDO
LVCMOS
GND
Qx
Qx
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD
VDDO
Qx
Qy
2
nCLK
VPP
VCMR
Cross Points
VDDO
2
CLK
tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
VDDO
VDDO
2
VDDO
80ꢀ
tF
80ꢀ
tR
2
2
Q0,
Q1
➤
➤
20ꢀ
20ꢀ
tcycle n+1
tcycle n
➤
➤
Clock
Outputs
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
OUTPUT RISE/FALL TIME
87002AG-02
www.icst.com/products/hiperclocks.html
REV.A OCTOBER 5, 2005
7
ICS87002-02
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
VOH
VOL
VOH
nCLK
CLK
nCLK
CLK
VDDO
2
VOL
VDDO
FB_IN
2
t
Q0, Q1
➤
t(Ø)
➤
PD
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
STATIC PHASE OFFSET
PROPAGATION DELAY
VDDO
2
VDDO
2
VDDO
2
Q0, Q1
tPW
tPERIOD
tPW
tPERIOD
odc =
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
87002AG-02
www.icst.com/products/hiperclocks.html
REV.A OCTOBER 5, 2005
8
ICS87002-02
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87002-02 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V or 2.5V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87002AG-02
www.icst.com/products/hiperclocks.html
REV.A OCTOBER 5, 2005
9
ICS87002-02
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals. BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3D show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK/nCLK INPUT:
LVCMOS OUTPUT:
For applications not requiring the use of the differential input, All unused LVCMOS output can be left floating. We
both CLK and nCLK can be left floating. Though not required, recommend that there is no trace attached.
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
87002AG-02
www.icst.com/products/hiperclocks.html
REV.A OCTOBER 5, 2005
10
ICS87002-02
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87002-02 is: 2578
87002AG-02
www.icst.com/products/hiperclocks.html
REV.A OCTOBER 5, 2005
11
ICS87002-02
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
MAX
SYMBOL
MIN
N
A
20
--
1.20
A1
A2
b
0.05
0.80
0.19
0.09
6.40
0.15
1.05
0.30
c
0.20
D
6.60
E
6.40 BASIC
4.50
E1
e
4.30
0.65 BASIC
0.75
L
0.45
0°
α
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
87002AG-02
www.icst.com/products/hiperclocks.html
REV.A OCTOBER 5, 2005
12
ICS87002-02
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS87002AG-02
ICS87002AG-02T
ICS87002AG-02LF
ICS87002AG-02LFT
ICS87002AG02
ICS87002AG02
TBD
20 Lead TSSOP
20 Lead TSSOP
2500 tape & reel
tube
20 Lead "Lead-Free" TSSOP
20 Lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
87002AG-02
www.icst.com/products/hiperclocks.html
REV.A OCTOBER 5, 2005
13
相关型号：
ICS87002AG-02LF
PLL Based Clock Driver, 87002 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-153, TSS0P20
IDT
ICS87002AG-02LFT
PLL Based Clock Driver, 87002 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-153, TSS0P20
IDT
ICS87002AG-02T
PLL Based Clock Driver, 87002 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, PLASTIC, MO-153, TSSOP-20
IDT
ICS87002AG-02T-LF
PLL Based Clock Driver, 87002 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, PLASTIC, MO-153, TSSOP-20
IDT
ICS87004AG-03
Low Skew Clock Driver, 87004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
IDT
ICS87004AG-03LF
Low Skew Clock Driver, 87004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20
IDT
ICS87004AG-03LFT
Low Skew Clock Driver, 87004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20
IDT
ICS87004AG-03T
Low Skew Clock Driver, 87004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
IDT
ICS87004AGI-03
Low Skew Clock Driver, 87004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
IDT
ICS87004AGI-03LFT
Low Skew Clock Driver, 87004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20
IDT
©2020 ICPDF网 联系我们和版权申明