ICS87339AM-01 [IDT]
Low Skew Clock Driver, 87339 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.25 MM HEIGHT, MS-013, SOIC-20;
| 型号： | ICS87339AM-01 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 87339 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.25 MM HEIGHT, MS-013, SOIC-20 光电二极管 |
| 文件： | 总16页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS87339-01
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS87339-01 is a low skew, high performance • Two divide by 2/4 differential 3.3V LVPECL outputs;
Differential-to-3.3V LVPECL / ECL Clock Generator/Divider.
The ICS87339-01 has one differential clock input pair. The
CLK, nCLK pair can accept most standard differential input
levels. The clock enable isinternally synchronized to
eliminate runt pulses on theoutputs during asynchronous
assertion/deassertion of the clock enable pin.
two divide by 4/6 differential 3.3V LVPECL outputs
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum input frequency: 1GHz
Guaranteed output and part-to-part skew characteristics
make the ICS87339-01 ideal for clock distribution applications
demanding well defined performance and repeatability.
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
• Output skew: 35ps (maximum)
• Part-to-part skew: 385ps (maximum)
• Bank skew: Bank A - 30ps (maximum)
Bank B - 25ps (maximum)
• Propagation delay: 2.1ns (maximum)
• LVPECL mode operating voltage supply range:
VCC = 3V to 3.6V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.6V to -3V
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
DIV_SELA
VCC
nCLK_EN
DIV_SELB
CLK
nCLK
RESERVED
MR
VCC
nc
DIV_SELA
VCC
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
QA0
nQA0
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
VEE
D
nCLK_EN
÷2, ÷4
R
QA1
nQA1
Q
LE
CLK
nCLK
9
10
QB0
nQB0
ICS87339-01
20-Lead SOIC, M Package
7.5mm x 12.8mm x 2.25
package body
÷4, ÷6
QB1
nQB1
R
MR
Top View
DIV_SELB
87339AM-01
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1
ICS87339-01
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
1, 8, 20
2
Name
VCC
Type
Description
Power
Input
Positive supply pins.
nCLK_EN
Pulldown Clock enable.
Selects divide value for Bank B outputs as described in Table 3.
3
DIV_SELB
Input
Pulldown
LVCMOS / LVTTL interface levels.
4
5
6
CLK
Input
Input
Pulldown Non-inverting differential clock input.
nCLK
Pullup
Inverting differential clock input.
Reserve pin.
RESERVED Reserve
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs (Qx) to go low, and the inverted outputs
(nQX) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
7
MR
Input
Pulldown
9
nc
Unused
Input
No connect.
Selects divide value for Bank A outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
10
DIV_SELA
Pulldown
11
VEE
Power
Output
Output
Output
Output
Negative supply pin.
12, 13
14, 15
16, 17
18, 19
nQB1, QB1
nQB0, QB0
nQA1, QA1
nQA0, QA0
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
nQA0, nQA1
MR nCLK_EN DIV_SELA
DIV_SELB
QA0, QA1
QB0, QB1
nQB0, nQB1
1
0
0
0
0
0
X
1
0
0
0
0
X
X
0
0
1
1
X
X
0
1
0
1
LOW
HIGH
LOW
HIGH
Not Switching
Not Switching
Not Switching
Not Switching
÷2
÷2
÷4
÷4
÷2
÷2
÷4
÷4
÷4
÷6
÷4
÷6
÷4
÷6
÷4
÷6
NOTE: After nCLK_EN switches, the clock outputs stop switching following a rising and falling input clock edge.
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ICS87339-01
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
CLK
MR
tRR
Q (÷n)
FIGURE 1A. MR TIMING DIAGRAM
Enabled
Disabled
CLK
nCLK
nCLK_EN
QAx, QBx
nQAx, nQBx
FIGURE 1B. NCLK_EN TIMING DIAGRAM
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ICS87339-01
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
-4.6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5 V
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
VBB Sink/Source, IBB
0.5mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG -65°C to 150°C
Package Thermal Impedance, θJA 46.2°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
3.0
3.3
3.6
V
105
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
-0.3
nCLK_EN, MR,
DIV_SELA, DIV_SELB
nCLK_EN, MR,
DIV_SELA, DIV_SELB
IIH
IIL
Input High Current
VIN = VCC = 3.6V
150
µA
µA
Input Low Current
VIN = 0V, VCC = 3.6V
-5
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VCC = 3.6V
Minimum Typical Maximum Units
nCLK
CLK
5
µA
µA
µA
µA
V
VIN = VCC = 3.6V
150
nCLK
CLK
VIN = 0V, VCC = 3.6V
VIN = 0V, VCC = 3.6V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
VEE + 0.5
VCC - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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ICS87339-01
LOW SKEW,
÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum Typical
VCC - 1.4
Maximum Units
VOH
Output High Voltage; NOTE1
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VCC - 2.0
VSWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
fMAX Output Frequency
tPD
Minimum Typical Maximum Units
1
2.1
35
GHz
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
Propagation Delay to Output; NOTE 1
Output Skew; NOTE 2, 5
CLK to Q (Diff)
1.6
tsk(o)
20
20
12
Bank A
Bank Skew; NOTE 3, 5
Bank B
30
tsk(b)
25
tsk(pp)
tS
Part-to-Part Skew; NOTE 4, 5
385
Setup Time
nCLK_EN to CLK
350
100
tH
Hold Time
CLK to nCLK_EN
CLK
tRR
Reset Recovery Time
Minimum Pulse Width
Output Rise/Fall Time
Output Duty Cycle
400
tPW
550
100
48
tR / tF
20% to 80%
600
52
odc
All data taken with outputs ÷4.
All parameters measured up to 1GHz unless noted otherwise.
This device does not add measureable jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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ICS87339-01
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nCLK
VPP
VCMR
Cross Points
LVPECL
VEE
CLK
VEE
nQx
-1.3V 0.3V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
nQx
nQx
Qx
Qx
PART 2
nQy
nQy
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nQAx
QAx
80%
tF
80%
VSWING
Clock
20%
20%
nQBx
Outputs
tR
QBx
tsk(pp)
OUTPUT RISE/FALL TIME
BANK SKEW
nCLK
nQAx, nQBx
QAx, QBx
CLK
tPW
nQAx,
nQBx
tPERIOD
QAx,
QBx
tPW
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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tPD
odc =
x 100%
PROPAGATION DELAY
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ICS87339-01
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF
in the center of the input voltage swing. For example, if the
input clock swing is only 2.5V and VCC = 3.3V, V_REF should be
1.25V and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS:
LVPECL OUTPUT
All control pins have internal pull-ups or pull-downs; additional All unused LVPECL outputs can be left floating. We
resistance is not required but can be added for additional recommend that there is no trace attached. Both sides of the
protection. A 1kΩ resistor can be used.
differential output pair should either be left floating or
terminated.
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ICS87339-01
LOW SKEW,
÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, consult with the vendor of the driver component to confirm
HCSL and other differential signals. Both VSWING and VOH the driver termination requirements. For example in Figure
must meet the VPP and VCMR input requirements. Figures 3A 3A, the input termination applies for LVHSTL drivers. If you
to 3E show interface examples for the CLK/nCLK input are using an LVHSTL driver from another vendor, use their
driven by the most common driver types. The input termination recommendation.
interfaces suggested here are examples only. Please
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. CLK/NCLK INPUT DRIVEN BY
LVHSTL DRIVER
FIGURE 3B. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
C2
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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ICS87339-01
LOW SKEW,
÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 4A and
4B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
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DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS87339-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS87339-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * ICC_MAX = 3.6V * 105mA = 378
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.6V, with all outputs switching) = 378mW + 120mW = 498mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA =Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.498W * 39.7°C/W = 89.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN SOIC, FORCED CONVECTION
θ by Velocity (Linear Feet per Minute)
JA
0
200
65.7°C/W
39.7°C/W
500
57.5°C/W
36.8°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 7. θJA VS. AIR FLOW TABLE FOR 20 LEAD SOIC
θ by Velocity (Linear Feet per Minute)
JA
0
200
65.7°C/W
39.7°C/W
500
57.5°C/W
36.8°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87339-01 is: 1745
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DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
PACKAGE OUTLINE - M SUFFIX FOR 20 LEAD SOIC
TABLE 8 PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
20
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
12.60
7.40
2.55
0.51
0.32
13.00
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119
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DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
87339AM-01
Marking
Package
Shipping Packaging Temperature
ICS87339AM01
ICS87339AM01
ICS87339A01L
ICS87339A01L
20 lead SOIC
Tube
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
87339AM-01T
20 lead SOIC
1000 Tape & Reel
Tube
87339AM-01LF
87339AM-01LFT
20 lead "Lead-Free" SOIC
20 lead "Lead-Free" SOIC
1000 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
87339AM-01
www.idt.com
REV. B AUGUST 2, 2010
14
ICS87339-01
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
Updated datasheet's header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
B
T9
14
16
8/2/10
87339AM-01
www.idt.com
REV. B AUGUST 2, 2010
15
ICS87339-01
LOW SKEW,
÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
We’ve Got Your Timing Solution.
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Printed in USA
87339AM-01
www.idt.com
REV. B AUGUST 2, 2010
16
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