ICS87366AMLFT [IDT]

PLL Based Clock Driver, 87366 Series, 6 True Output(s), 0 Inverted Output(s), PDSO24, 7.50 X 15.33 MM, 2.30 MM HEIGHT, MO-119, MS-013, SOIC-24;


型号：	ICS87366AMLFT
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	PLL Based Clock Driver, 87366 Series, 6 True Output(s), 0 Inverted Output(s), PDSO24, 7.50 X 15.33 MM, 2.30 MM HEIGHT, MO-119, MS-013, SOIC-24 驱动光电二极管逻辑集成电路
文件：	总10页 (文件大小：93K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY

ICS87366

Integrated

Circuit

Systems, Incꢀ

1-TO-6, DIFFERENTIAL TO 3.3V LVPECL

CLOCK

ENERATOR W/FORWARD

RROR

CORRECTION

GENERAL DESCRIPTION

FEATURES

The ICS87366 is a 1-to-6, Differential to 3.3V • 6 differential LVPECL outputs

,&6

LVPECL Clock Generator and a member of the

• 1 differential CLK/nCLK input pair

HiPerClockS™

HiPerClockS™ family of High Performance Clock

Solutions from ICS. The ICS87366 can multiply the

reference clock times 3 or multiply times 3 * 66/64

• CLK/nCLK pair can accept the following differential input

levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

thereby applying an FEC rate to the reference clock. The

ICS87366 is an ideal device in any application requiring x3

multiplication with an 66/64 FEC option while maintaining low

jitter. Common applications may include networking and stor-

age area networks.

• Output frequency: FEC_SEL = 0, 159.375MHz

FEC_SEL = 1, 164.355MHz

• Cycle-to-cycle jitter: FEC_SEL = 0, 15ps (typical)

FEC_SEL = 1, 20ps (typical)

• Full 3.3V or 3.3V core/2.5V output supply voltage

• 0°C to 70°C ambient operating temperature

BLOCK DIAGRAM

PIN ASSIGNMENT

nQ0

nQ1

nQ2

nQ3

V^CCO

FEC_SEL

CLK

nCLK

V^EE

VCCA

VCC

nQ1

PLL_SEL

nQ2

CLK

nCLK

Output

Divider

nQ3

PLL

Input

Divider

nQ4

nQ5

PLL_SEL

V^EE

VCCO

nQ4

Feedback

Divider

nQ5

ICS87366

24-Lead, 300-MIL SOIC

7.5mm x 15.33mm x 2.3mm body package

M Package

FEC_SEL

Top View

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

87366AM

www.icst.com/products/hiperclocks.html

REV. A SEPTEMBER 9, 2003

PRELIMINARY

ICS87366

Integrated

Circuit

Systems, Incꢀ

1-TO-6, DIFFERENTIAL TO 3.3V LVPECL

CLOCK

ENERATOR W/FORWARD

RROR

CORRECTION

TABLE 1. PIN DESCRIPTIONS

Number

1, 2

Name

Q0, nQ0

Q1, nQ1

Q2, nQ2

Q3, nQ3

Q4, nQ4

Q5, nQ5

V_CCO

Type

Description

Output

Power

Differential output pair. LVPECL interface levels.

Output supply pins.

3, 4

5, 6

7, 8

9, 10

11, 12

13, 24

14, 18

V_EE

Negative supply pins.

Selects between the PLL and CLK, nCLK as the input to the dividers.

When HIGH, selects PLL. When LOW, selects CLK, nCLK.

LVCMOS / LVTTL interface levels.

PLL_SEL

Input

Pullup

V_CC

Power

Core supply pin.

V_CCA

Analog supply pin.

Pullup/

Pulldown

nCLK

CLK

Input

Inverting differential clock input. V_CC/2 defaults when left floating.

Pulldown Non-inverting differential clock input.

Active High Master Reset. When logic HIGH, the internal dividers are

reset causing the true outputs Qx to go low and the inverted outputs

nQx to go high. When logic LOW, the internal dividers and the outputs

Input

Pulldown

are enabled. LVCMOS / LVTTL interface levels.

Unused

Input

No connect.

Select pin controls the Feedback Divide value.

Pullup

FEC_SEL

LVCMOS / LVTTL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol

C_IN

Parameter

Test Conditions

Minimum Typical Maximum Units

Input Capacitance

Input Pullup Resistor

R_PULLUP

R_PULLDOWNInput Pulldown Resistor

TABLE 3. FUNCTION TABLE

Inputs

FEC_SEL

Multiplier

Reset: Qx = LOW, nQx = HIGH

3 x 33/32

87366AM

www.icst.com/products/hiperclocks.html

REV. A SEPTEMBER 9, 2003

PRELIMINARY

ICS87366

Integrated

Circuit

Systems, Incꢀ

1-TO-6, DIFFERENTIAL TO 3.3V LVPECL

CLOCK

ENERATOR W/FORWARD

RROR

CORRECTION

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

4.6V

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

Inputs, V

-0.5V to V_CC+ 0.5V

Outputs, I_O

Continuous Current

Surge Current

50mA

100mA

Package Thermal Impedance, θ_JA50°C/W (0 lfpm)

Storage Temperature, T -65°C to 150°C

STG

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_CC= V_CCA= 3.3V±5%, V_CCO= 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

3.135

Typical

3.3

Maximum Units

V_CC

V_CCA

V_CCO

I_EE

Core Supply Voltage

3.465

2.625

Analog Supply Voltage

Output Supply Voltage

Power Supply Current

Analog Supply Current

3.135

3.3

3.135

3.3

2.375

2.5

TBD

I_CCA

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V_CC= V_CCA= 3.3V±5%, V_CCO= 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

PLL_SEL, MR,

FEC_SEL

PLL_SEL, MR,

FEC_SEL

V_IH

V_IL

Input High Voltage

_CC+ 0.3

0.8

Input Low Voltage

Input High Current

-0.3

V_CC= V_IN= 3.465V

150

µA

I_IH

PLL_SEL, FEC_SEL

_CC= V_IN= 3.465V

V_CC= 3.465V, V_IN= 0V

_CC= 3.465V, V_IN= 0V

-5

I_IL

Input Low Current

PLL_SEL, FEC_SEL

-150

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V_CC= V_CCA= 3.3V±5%, V_CCO= 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C

Symbol Parameter

I_IHInput High Current

Test Conditions

V_CC= V_IN= 3.465V

V_CC= 3.465V, V_IN= 0V

Minimum Typical Maximum Units

CLK

150

µA

nCLK

CLK

-5

-150

I_IL

Input Low Current

nCLK

V_PP

Peak-to-Peak Voltage

0.15

1.0

V_CMR

Common Mode Input Voltage; NOTE 1, 2

V_EE+ 0.5

V_CC- 0.85

NOTE 1: Common mode input voltage is defined as V_IH.

NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V_CC+ 0.3V.

87366AM

www.icst.com/products/hiperclocks.html

REV. A SEPTEMBER 9, 2003

PRELIMINARY

ICS87366

Integrated

Circuit

Systems, Incꢀ

1-TO-6, DIFFERENTIAL TO 3.3V LVPECL

CLOCK

ENERATOR W/FORWARD

RROR

CORRECTION

TABLE 4D. LVPECL DC CHARACTERISTICS, V_CC= V_CCA= 3.3V±5%, V_CCO= 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

V_OH

Output High Voltage; NOTE 1

V_CCO- 1.4

V_CCO- 2.0

0.6

V_CCO- 1.0

V_CCO- 1.7

1.0

V_OL

Output Low Voltage; NOTE 1

V_SWING

Peak-to-Peak Output Voltage Swing

µA

NOTE 1: Outputs terminated with 50 to V_CCO- 2V.

TABLE 5A. AC CHARACTERISTICS, V_CC= V_CCA= V_CCO= 3.3V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical Maximum Units

F_OUT

Output Frequency

159.375

164.355

MHz

FEC_SEL = 0

FEC_SEL = 1

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 3

tsk(o)

tsk(pp)

t_R/ t_F

odc

Output Skew; NOTE 1, 3

Part-to-Part Skew, NOTE 2

Output Rise/Fall Time

Output Duty Cycle

TBD

20% to 80%

200

700

t_LOCK

PLL Lock Time

NOTE 1: Defined as skew between outputs on different devices operating at the same supply voltages and with equal

load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at V_CCO/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

TABLE 5B. AC CHARACTERISTICS, V_CC= V_CCA= 3.3V±5%, V_CCO= 2.5V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical Maximum Units

F_OUT

Output Frequency

159.375

164.355

MHz

FEC_SEL = 0

FEC_SEL = 1

TBD

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 3

tsk(o)

tsk(pp)

t_R/ t_F

odc

Output Skew; NOTE 1, 3

Part-to-Part Skew, NOTE 2

Output Rise/Fall Time

Output Duty Cycle

20% to 80%

200

700

t_LOCK

PLL Lock Time

NOTE 1: Defined as skew between outputs on different devices operating at the same supply voltages and with equal

load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at V_CCO/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

87366AM

www.icst.com/products/hiperclocks.html

REV. A SEPTEMBER 9, 2003

PRELIMINARY

ICS87366

Integrated

Circuit

Systems, Incꢀ

1-TO-6, DIFFERENTIAL TO 3.3V LVPECL

CLOCK

ENERATOR W/FORWARD

RROR

CORRECTION

PARAMETER MEASUREMENT INFORMATION

2.8V±0.04V

SCOPE

V_CC

V_CC,

V_CCA, V_CCO

LVPECL

V_EE

nQx

V_EE

-0.5V ± 0.125V

-1.3V ± 0.165V

3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT

3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT

V_CC

nQx

nCLK

V_PP

V_CMR

Cross Points

nQy

CLK

tsk(o)

V_EE

DIFFERENTIAL INPUT LEVEL

OUTPUT SKEW

PART 1

nQx

nQ0:nQ5

Q0:Q5

PART 2

nQy

➤

tcycle n

tcycle n+1

➤

tjit(cc) = tcycle n –tcycle n+1

1000 Cycles

tsk(o)

PART-TO-PART SKEW

CYCLE-TO-CYCLE JITTER

nQ0:nQ5

Q0:Q5

80%

V_SWING

Pulse Width

Clock

20%

t_PERIOD

Outputs

t_F

t_R

t_PW

odc =

t_PERIOD

OUTPUT RISE/FALL TIME

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

87366AM

www.icst.com/products/hiperclocks.html

REV. A SEPTEMBER 9, 2003

PRELIMINARY

ICS87366

Integrated

Circuit

Systems, Incꢀ

1-TO-6, DIFFERENTIAL TO 3.3V LVPECL

CLOCK

ENERATOR W/FORWARD

RROR

CORRECTION

APPLICATION INFORMATION

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS87366 provides sepa-

3.3V

V_CC

rate power supplies to isolate any high switching

and

.01µF

10Ω

noise from the outputs to the internal PLL. V_CC, V_CCA

V_CCO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 1 illustrates how

a 10Ω resistor along with a 10µF and a .01µF bypass

capacitor should be connected to each V_CCApin.

V_CCA

.01µF

10 µF

FIGURE 1. POWER SUPPLY FILTERING

TERMINATION FOR LVPECL OUTPUTS

The clock layout topology shown below is a typical termina- drive 50Ω transmission lines. Matched impedance techniques

tion for LVPECL outputs. The two different layouts mentioned should be used to maximize operating frequency and minimize

are recommended only as guidelines.

signal distortion. Figures 2A and 2B show two different layouts

which are recommended only as guidelines. Other suitable clock

layouts may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminat-

ing resistors (DC current path to ground) or current sources

must be used for functionality. These outputs are designed to

3.3V

Z_o= 50Ω

125Ω

FOUT

FIN

Z_o= 50Ω

FOUT

FIN

50Ω

V_CC- 2V

RTT =

Z_o

RTT

(V_OH+ V_OL/ V_CC– 2) – 2

84Ω

FIGURE 2A. LVPECL OUTPUT TERMINATION

FIGURE 2B. LVPECL OUTPUT TERMINATION

87366AM

www.icst.com/products/hiperclocks.html

REV. A SEPTEMBER 9, 2003

PRELIMINARY

ICS87366

Integrated

Circuit

Systems, Incꢀ

1-TO-6, DIFFERENTIAL TO 3.3V LVPECL

CLOCK

ENERATOR W/FORWARD

RROR

CORRECTION

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the

and other differential signals. Both V_SWINGand V_OHmust meet the driver component to confirm the driver termination requirements.

V_PPand V_CMRinput requirements. Figures 3A to 3D show inter- For example in Figure 3A, the input termination applies for ICS

face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTLdrivers. If you are using an LVHSTL driver

the most common driver types. The input interfaces suggested from another vendor, use their termination recommendation.

3.3V

1.8V

Zo = 50 Ohm

CLK

Zo = 50 Ohm

CLK

Zo = 50 Ohm

nCLK

Zo = 50 Ohm

HiPerClockS

Input

LVPECL

nCLK

HiPerClockS

Input

LVHSTL

ICS

HiPerClockS

LVHSTL Driver

FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

ICS HIPERCLOCKS LVHSTL DRIVER

FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

3.3V

Zo = 50 Ohm

3.3V

125

LVDS_Driver

Zo = 50 Ohm

CLK

100

nCLK

Receiv er

nCLK

HiPerClockS

Input

Zo = 50 Ohm

LVPECL

FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

87366AM

www.icst.com/products/hiperclocks.html

REV. A SEPTEMBER 9, 2003

PRELIMINARY

ICS87366

Integrated

Circuit

Systems, Incꢀ

1-TO-6, DIFFERENTIAL TO 3.3V LVPECL

CLOCK

ENERATOR W/FORWARD

RROR

CORRECTION

RELIABILITY INFORMATION

TABLE 6. θ_JAVS. AIR FLOW TABLE

θ_JAby Velocity (Linear Feet per Minute)

200

43°C/W

500

38°C/W

Multi-Layer PCB, JEDEC Standard Test Boards

50°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TRANSISTOR COUNT

The transistor count for ICS87366 is: 3069

87366AM

www.icst.com/products/hiperclocks.html

REV. A SEPTEMBER 9, 2003

PRELIMINARY

ICS87366

Integrated

Circuit

Systems, Incꢀ

1-TO-6, DIFFERENTIAL TO 3.3V LVPECL

CLOCK

ENERATOR W/FORWARD

RROR

CORRECTION

PACKAGE OUTLINE - M SUFFIX

TABLE 7. PACKAGE DIMENSIONS

Millimeters

SYMBOL

Minimum

Maximum

2.65

0.10

2.05

0.33

0.18

15.20

7.40

2.55

0.51

0.32

15.85

7.60

1.27 BASIC

10.00

0.25

0.40

0°

10.65

0.75

1.27

8°

Reference Document: JEDEC Publication 95, MS-013, MO-119

87366AM

www.icst.com/products/hiperclocks.html

REV. A SEPTEMBER 9, 2003

PRELIMINARY

ICS87366

Integrated

Circuit

Systems, Incꢀ

1-TO-6, DIFFERENTIAL TO 3.3V LVPECL

CLOCK

ENERATOR W/FORWARD

RROR

CORRECTION

TABLE 8. ORDERING INFORMATION

Part/Order Number

ICS87366AM

Marking

Package

Count

30 per tube

1000

Temperature

0°C to 70°C

ICS87366AM

24 Lead SOIC

ICS87366AMT

24 Lead SOIC on Tape and Reel

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are

not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS

product for use in life support devices or critical medical instruments.

87366AM

www.icst.com/products/hiperclocks.html

REV. A SEPTEMBER 9, 2003

ICS87366AMLFT [IDT]

相关型号：

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ICS8737AG-11LF

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ICS8737AGI-11

ICS8737AGI-11LF

ICS8737AGI-11LFT

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