ICS87946AY-01LFT [IDT]
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32;
| 型号： | ICS87946AY-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总13页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS87946-01
Integrated
Circuit
Systems, Inc.
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTLCLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS87946-01 is a low skew, ÷1, ÷2 Clock • 10 single ended LVCMOS outputs, 7Ω typical output
Generator and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS87946-01 has one LVPECL clock
input pair. The PCLK, nPCLK pair can accept
impedance
HiPerClockS™
• LVPECLclock input pair
• PCLK, nPCLK supports the following input levels:
LVPECL, CML, SSTL
LVPECL, CML, or SSTL input levels. The low impedance
LVCMOS outputs are designed to drive 50Ω series or parallel
terminated transmission lines. The effective fanout can be in-
creased from 10 to 20 by utilizing the ability of the outputs to
drive two series terminated lines.
• Maximum input frequency: 250MHz
• Output skew: 200ps (maximum)
• Part-to-part skew: 500ps (typical)
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
• Multiple frequency skew: 350ps (maximum)
• 3.3V input, outputs may be either 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
The ICS87946-01 is characterized at 3.3V core/3.3V output
and 3.3V core/2.5V output. Guaranteed bank, output and part-
to-part skew characteristics make the ICS87946-01 ideal for
those clock distribution applications demanding well defined
performance and repeatability.
BLOCK DIAGRAM
PIN ASSIGNMENT
0
÷1
÷2
PCLK
nPCLK
QA0 - QA2
QB0 - QB2
QC0 - QC3
1
32 31 30 29 28 27 26 25
nc
VDD
1
2
3
4
5
6
7
8
DIV_SELA
DIV_SELB
24
23
22
21
20
19
18
17
GND
QB0
VDDB
QB1
GND
QB2
VDDB
VDDC
0
1
PCLK
nPCLK
ICS87946-01
DIV_SELA
DIV_SELB
DIV_SELC
0
1
GND
DIV_SELC
MR/nOE
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87946AY-01
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REV. A JANUARY 2, 2002
1
PRELIMINARY
ICS87946-01
Integrated
Circuit
Systems, Inc.
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTLCLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
nc
Type
Unused
Description
1
2
3
4
No connect.
VDD
Power
Input
Input
Positive supply pins. Connect to 3.3V.
Pulldown Non-inverting differential LVPECL clock input.
PCLK
nPCLK
Pullup
Inverting differential LVPECL clock input.
Controls frequency division for Bank A outputs.
LVCMOS interface levels.
Controls frequency division for Bank B outputs.
LVCMOS interface levels.
Controls frequency division for Bank C outputs.
LVCMOS interface levels.
5
6
7
DIV_SELA
DIV_SELB
DIV_SELC
Input
Input
Input
Pulldown
Pulldown
Pulldown
8, 11, 15,
20, 24, 27,
31
GND
VDDC
Power
Power supply ground. Connect to ground.
9, 13, 17
Power
Output
Power
Output
Power
Output
Positive supply pins for Bank C outputs. Connect to 3.3V or 2.5V.
10, 12,
14, 16
QC0, QC1,
QC2, QC3
Bank C outputs. LVCMOS interface levels.
7Ω typical output impedance.
Positive supply pins for Bank B outputs. Connect to 3.3V or 2.5V.
18, 22
19, 21, 23
25, 29
VDDB
QB2, QB1,
QB0
Bank B outputs. LVCMOS interface levels.
7Ω typical output impedance.
Positive supply pins for Bank A outputs. Connect to 3.3V or 2.5V.
VDDA
26, 28,
30
QA2, QA1,
QA02,
Bank A outputs. LVCMOS interface levels.
7Ω typical output impedance.
Master reset and output enable. Resets outputs to tristate.
Enables and disables all outputs. LVCMOS interface levels.
32
MR/nOE
Input
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
pF
Ω
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
CPD
Power Dissipation Capacitance (per output)
Output Impedance
VDD, *VDDx = 3.465V
TBD
7
ROUT
*NOTE: VDDx denotes VDDA, VDDB, VDDC
.
TABLE 3. FUNCTION TABLE
Inputs
Outputs
MR/nOE
DIV_SELA
DIV_SELB
DIV_SELC
QA0 - QA2
Hi Z
QB0 - QB2
Hi Z
QC0 - QC3
Hi Z
1
0
0
0
0
0
0
X
0
X
X
X
0
X
X
X
X
X
0
fIN/1
Active
Active
fIN/1
Active
Active
Active
Active
fIN/1
1
fIN/2
X
X
X
X
Active
Active
Active
Active
1
fIN/2
X
X
Active
Active
1
fIN/2
87946AY-01
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REV. A JANUARY 2, 2002
2
PRELIMINARY
ICS87946-01
Integrated
Circuit
Systems, Inc.
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTLCLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDx + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
47.9°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDX = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum Typical Maximum Units
Positive Supply Voltage
Output Supply Voltage
Core Supply Current
Output Supply Current
3.135
3.135
3.3
3.3
41
8
3.465
3.465
V
*VDDx
IDD
V
mA
mA
**IDDx
*VDDx denotes VDDA, VDDB, VDDC
**IDDx denotes IDDA, IDDB, IDDC
.
.
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDX = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
2
VDD + 0.3
0.8
V
V
-0.3
Input
High Current
Input
Low Current
DIV_SELA, DIV_SELB,
IIH
IIL
VDD = V = 3.465V
150
µA
µA
IN
DIV_SELC, MR/nOE
DIV_SELA, DIV_SELB,
DIV_SELC, MR/nOE
VDD = 3.465V, V = 0V
-5
IN
VOH
VOL
IOZL
IOZH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Tristate Current Low
Output Tristate Current High
2.6
V
V
V
V
0.5
TBD
TBD
NOTE 1: Outputs terminated with 50Ω to VDDx/2. See page 7, Figure 1A, 3.3V Output Load Test Circuit.
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = VDDX = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum Typical Maximum Units
PCLK
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
V
nPCLK
PCLK
V
-5
-150
IIL
Input Low Current
nPCLK
VDD = 3.465V, VIN = 0V
VPP
Peak-to-Peak Input Voltage
0.3
1
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 1.5
VDD
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
87946AY-01
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REV. A JANUARY 2, 2002
3
PRELIMINARY
ICS87946-01
Integrated
Circuit
Systems, Inc.
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTLCLOCK GENERATOR
TABLE 5A. AC CHARACTERISTICS, VDD = VDDX = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Input Frequency
250
MHz
Propagation Delay,
Low to High; NOTE 1
Propagation Delay,
High to Low; NOTE 1
tpLH
f ≤ 250MHz
f ≤ 250MHz
3.2
3.2
ns
tpHL
ns
tsk(b)
tsk(o)
Bank Skew; NOTE 2, 7
Output Skew; NOTE 3, 7
Measured on rising edge at VDDx/2
Measured on rising edge at VDDx/2
100
200
ps
ps
Multiple Frequency Skew;
NOTE 4, 7
tsk(w)
Measured on rising edge at VDDx/2
350
ps
tsk(pp)
Part-to-Part Skew; NOTE 5, 7 Measured on rising edge at VDDx/2
500
700
700
50
ps
ps
ps
ꢀ
tR
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
Output Duty Cycle
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
tF
odc
Output Enable Time;
NOTE 6
Output Disable Time;
NOTE 6
tEN
f = 10MHz
f = 10MHz
ns
ns
tDIS
All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
Measured at VDDx/2.
NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages
and equal load conditions.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
87946AY-01
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REV. A JANUARY 2, 2002
4
PRELIMINARY
ICS87946-01
Integrated
Circuit
Systems, Inc.
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTLCLOCK GENERATOR
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDX = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum Typical Maximum Units
Positive Supply Voltage
Output Supply Voltage
Core Supply Current
Output Supply Current
3.135
2.375
3.3
2.5
41
8
3.465
2.625
V
*VDDx
IDD
V
mA
mA
**IDDx
*VDDx denotes VDDA, VDDB, VDDC
**IDDx denotes IDDA, IDDB, IDDC
.
.
TABLE 4E. LVCMOS DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDX = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
2
VDD + 0.3
0.8
V
V
-0.3
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
nMR/OE
Input
High Current
IIH
VDD = V = 3.465V
150
µA
µA
IN
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
nMR/OE
Input
Low Current
IIL
VDD = 3.465V, V = 0V
-5
IN
VOH
VOL
IOZL
IOZH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Tristate Current Low
Output Tristate Current High
1.8
V
V
V
V
0.5
TBD
TBD
NOTE 1: Outputs terminated with 50Ω to VDDx/2. See page 7, Figure 1B, 3.3V/2.5V Output Load Test Circuit.
TABLE 4F. LVPECL DC CHARACTERISTICS, VDD = VDDX = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum Typical Maximum Units
PCLK
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
V
nPCLK
PCLK
V
-5
-150
IIL
Input Low Current
nPCLK
VDD = 3.465V, VIN = 0V
VPP
Peak-to-Peak Input Voltage
0.3
1
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 1.5
VDD
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
87946AY-01
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REV. A JANUARY 2, 2002
5
PRELIMINARY
ICS87946-01
Integrated
Circuit
Systems, Inc.
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTLCLOCK GENERATOR
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDX = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Input Frequency
250
MHz
Propagation Delay,
Low to High; NOTE 1
Propagation Delay,
High to Low; NOTE 1
tpLH
f ≤ 250MHz
f ≤ 250MHz
3.2
3.2
ns
tpHL
ns
tsk(b)
tsk(o)
Bank Skew; NOTE 2, 7
Output Skew; NOTE 3, 7
Measured on rising edge at VDDx/2
Measured on rising edge at VDDx/2
100
200
ps
ps
Multiple Frequency Skew;
NOTE 4, 7
tsk(w)
Measured on rising edge at VDDx/2
350
ps
tsk(pp)
Part-to-Part Skew; NOTE 5, 7 Measured on rising edge at VDDx/2
500
600
600
50
ps
ps
ps
ꢀ
tR
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
Output Duty Cycle
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
tF
odc
Output Enable Time;
NOTE 6
Output Disable Time;
NOTE 6
tEN
f = 10MHz
f = 10MHz
ns
ns
tDIS
All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
Measured at VDDx/2.
NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages
and equal load conditions.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
87946AY-01
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REV. A JANUARY 2, 2002
6
PRELIMINARY
ICS87946-01
Integrated
Circuit
Systems, Inc.
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTLCLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
SCOPE
VDD
VDDx
Qx
LVCMOS
GND
-1.65V 5ꢀ
FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT
1.25V 5ꢀ
2.05V 5ꢀ
SCOPE
VDD
VDDx
Qx
LVCMOS
GND
-1.25V 5ꢀ
FIGURE 1B - 3.3V/2.5V OUTPUT LOAD TEST CIRCUIT
87946AY-01
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REV. A JANUARY 2, 2002
7
PRELIMINARY
ICS87946-01
Integrated
Circuit
Systems, Inc.
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTLCLOCK GENERATOR
VDD
nPCLK
PCLK
VPP
VCMR
Cross Points
GND
FIGURE 2 - DIFFERENTIAL INPUT LEVEL
VDD
2
x
Qx
Qy
VDD
x
2
tsk(o)
FIGURE 3 - OUTPUT SKEW
VDD
2
PART1
x
Qx
VDD
2
x
PART2
Qy
tsk(pp)
FIGURE 4 - PART-TO-PART SKEW
87946AY-01
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REV. A JANUARY 2, 2002
8
PRELIMINARY
ICS87946-01
Integrated
Circuit
Systems, Inc.
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTLCLOCK GENERATOR
80ꢀ
80ꢀ
VSWING
20ꢀ
20ꢀ
Clock Inputs
and Outputs
tR
tF
FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME
nPCLK
PCLK
VDD
x
2
QAx, QBx, QCx
tPD
FIGURE 6 - PROPAGATION DELAY
VDD
x
2
QAx, QBx, QCx
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
FIGURE 7 - odc & tPERIOD
87946AY-01
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REV. A JANUARY 2, 2002
9
PRELIMINARY
ICS87946-01
Integrated
Circuit
Systems, Inc.
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTLCLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87946AY-01
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REV. A JANUARY 2, 2002
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PRELIMINARY
ICS87946-01
Integrated
Circuit
Systems, Inc.
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTLCLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87946-01 is: 1204
87946AY-01
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REV. A JANUARY 2, 2002
11
PRELIMINARY
ICS87946-01
Integrated
Circuit
Systems, Inc.
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTLCLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
87946AY-01
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REV. A JANUARY 2, 2002
12
PRELIMINARY
ICS87946-01
Integrated
Circuit
Systems, Inc.
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTLCLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS87946AY-01
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS87946AY-01
ICS87946AY-01
ICS87946AY-01T
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
87946AY-01
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REV. A JANUARY 2, 2002
13
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IDT
ICS87949AY-01
Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
IDT
ICS87949AY-01LF
Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
IDT
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