ICS8MG3-311.040AJI [IDT]

Oscillator;
ICS8MG3-311.040AJI
型号: ICS8MG3-311.040AJI
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

Oscillator

文件: 总4页 (文件大小:245K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
PRELIMINARY  
Integrated  
Circuit  
Systems, Inc.  
ICS8Mx3  
Crystal Oscillator: LVPECL CLOCK OUTPUT  
I C S 8 M x 3  
LOW JITTER, HIGH FREQUENCY XTAL OSCILLATOR  
Stable, ultra low jitter, LVPECL clock generation  
For Gigabit Ethernet, Fibre Channel, PCI-Express, other applications  
Clock output frequencies from 75 to 750 MHz  
One differential LVPECL clock output  
Output Enable (OE) pin (tri-state – with ultra low current – when low)  
Small 6-pin 5 x 7 x 1.5mm SMT ceramic package  
Low profile package allows back-side PCB mounting  
Pb-free RoHS compliant (by default; no additional code required)  
2.5V or 3.3V device power supply options  
8Mx3  
( T o p V ie w )  
Commercial (0 to +70 OC) and Industrial (-40 to +85 OC) temperatures  
Frequency stability of 50 or 100 ppm  
(including initial accuracy, operating temperature variation,  
supply voltage variation, load variation, reflow drift, and aging for 10 years)  
6-pin CERHERMETIC 5 x 7 x 1.5mm SMT  
Low phase jitter < 1 ps rms maximum (12kHz to 20MHz)  
ELECTRICAL SPECIFICATIONS  
Unless stated otherwise, VCC = 2.5 Volts + 5% or 3.3 Volts + 5%, TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial)  
Parameter  
Min  
Typ  
Max  
Unit  
Conditions  
DC CHARACTERISTICS  
Power Supply Voltage  
VCC  
3.135  
2.375  
3.3  
2.5  
75  
3.465  
2.625  
V
3.3V operation  
2.5V operation  
Power Supply  
(VCC , VEE pins)  
V
in 8MJ3 and 8MK3 only  
Power Supply Current  
IEE  
mA  
mA  
pF  
V
OE = VCC  
OE = GND  
Current with Output Disable IOED  
<0.6  
Input Capacitance  
Input High Voltage  
CIN  
VIH  
4
0.7 x VCC  
-150  
Output Enable  
(OE pin)  
LVCMOS/LVTTL  
V
Input Low Voltage  
VIL  
0.3 x VCC  
Input High Current  
Input Low Current  
IIH  
5
µA  
µA  
kΩ  
VCC = VIN = 2.625 or 3.465V  
IIL  
VCC = 2.625 or 3.465V, VIN = 0V  
Internal Pull-up Resistor  
RPULLUP  
51  
Output High Voltage1  
Output Low Voltage1  
Outputs terminated with 50to VCC - 2V.  
VOH  
VOL  
VCC - 1.4  
VCC - 2.0  
VCC - 0.9  
VCC - 1.7  
V
Clock Output  
Level  
(OUT, nOUT)  
LVPECL  
See PARAMETER MEASUREMENT INFORMATION, Output  
Load AC Test Circuit diagrams.  
V
Peak-to-Peak Output Voltage  
Swing  
See PARAMETER MEASUREMENT INFORMATION,  
Output Rise and Fall Time diagram.  
VSWING  
0.6  
75  
1.0  
V
AC CHARACTERISTICS  
Output Frequency Range  
750  
±100  
±50  
MHz  
All conditions  
Output  
(OUT, nOUT)  
Frequency Stability error  
f/fO  
Includes frequency set,  
ppm p-p  
in 8MH3 and 8MK3  
VCC, TA & load variation,  
ppm p-p  
%
in 8MG3 and 8MJ3  
reflow drift, 10 yr. aging  
Output Duty Cycle  
Output Rise Time  
Output Fall Time  
odc  
tR  
50  
See Output Duty Cycle diagram  
and Rise and Fall Time diagram  
in PARAMETER MEASUREMENT  
INFORMATION.  
600  
600  
10  
ps  
20% to 80% of VOH - VOL  
20% to 80% of VOH - VOL  
tF  
ps  
tOSC  
ms  
Time at Min. VCC (3.135V or 2.375V) to be 0s  
(design target  
Oscillator Start-up Time  
RMS Phase Jitter, (Random) 2  
< 1  
design target  
ps rms  
)
t jit(Ø)  
2
0.2  
3
ps  
ps  
ps  
ps  
ps  
Deterministic  
tDS  
Jitter  
3
Random  
σ
σ
of Random jitter  
tRS  
3
3
Root Mean Square  
Peak to Peak  
Accumulated Jitter  
of Total jitter distribution  
tRMS  
3
25  
4
tP-P  
3
n = 2 to 50,000 cycles  
tacc  
Note 1: Outputs terminated with 50to V - 2V. See PARAMETER MEASUREMENT INFORMATION, Output Load AC Test Circuit diagrams.  
CC  
Note 2: Measured using an Aeroflex PN9500 with a 12 kHz to 20MHz integration range.  
Note 3: Measured using a Wavecrest SIA-3000.  
SUPPLY VOLTAGE & FREQUENCY ACCURACY  
G
H
J
=
=
=
=
3.3V  
±50 ppm  
± 100 ppm  
± 50 ppm  
± 100 ppm  
3.3V  
2.5V / 3.3V  
2.5V / 3.3V  
K
ICS8Mx3 Datasheet Rev A  
Revised 30Nov2004  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  
ICS8M 3  
X
Integrated  
Circuit  
Systems, Inc.  
Crystal Oscillator: LVPECL CLOCK  
O
UTPUT  
PRELIMINARY  
PIN DESCRIPTIONS  
Output enable pin. Tri-state – with  
ABSOLUTE MAXIMUM RATINGS  
Inputs  
VI  
V
V
-0.5 to VCC +0.5  
1
OE  
Input  
Internal pull-up resistor  
ultra low current – when low.  
LVCMOS/LVTTL interface levels.  
Outputs  
VO  
VCC  
-0.5 to VCC +0.5  
2
3
NC  
VEE  
Unused  
Power  
No connect.  
4.6  
Positive Supply Voltage  
Package Thermal Impedence  
Storage Temperature  
V
Negative supply pin.  
TBD  
°C/W (0 lfpm)  
4
5
OUT  
nOUT  
Differential clock output connections.  
LVPECL interface levels.  
Output No internal terminator  
Power  
-40 to +100  
oC  
TS  
VCC  
6
Power supply pin.  
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent  
damage to the device. These ratings are stress specifications only. Functional operation of  
product at these conditions or any conditions beyond those listed in DC Characteristics, or  
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  
For typical value of internal pull-up resistor, see DC Characteristics.  
extended periods may affect product reliability  
.
PARAMETER MEASUREMENT INFORMATION  
2V  
2V  
SCOPE  
SCOPE  
VCC  
VCC  
Qx  
Qx  
LVPECL  
VEE  
LVPECL  
nQx  
nQx  
VEE  
-0.5V 0.125V  
-1.3V 0.165V  
2.5V Output Load AC Test Circuit  
3.3V Output Load AC Test Circuit  
nOUT  
OUT  
Phase Noise Plot  
tPW  
(Output Pulse Width)  
t
PW  
odc =  
t
PERIOD  
tPERIOD  
Output Duty Cycle / Pulse WIdth / Period  
80%  
80%  
VSWING  
Offset Frequency  
f1  
f2  
20%  
20%  
Clock  
Outputs  
t
t
F
R
RMS Jitter = Area Under Offset Frequency Markers  
RMS Phase Jitter  
Output Rise and Fall Time  
ICS8Mx3 Datasheet Rev A  
2 of 4  
Revised 30Nov2004  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  
ICS8M 3  
X
Integrated  
Circuit  
Systems, Inc.  
Crystal Oscillator: LVPECL CLOCK  
O
UTPUT  
PRELIMINARY  
APPLICATION INFORMATION  
TERMINATION FOR 3.3V LVPECL OUTPUT  
TERMINATION FOR 2.5V LVPECL OUTPUT  
The clock layout topology shown below is a typical termination for 3.3V LVPECL  
outputs. The two different layouts mentioned are recommended only as guide-  
lines.  
Figure 2A and Figure 2B show examples of termination for 2.5V LVPECL driver.  
These terminations are equivalent to terminating 50to V - 2V.  
CC CC  
can be eliminated and the termination is shown in Figure 2C.  
CC  
For V = 2.5V, the V - 2V is very close to ground level. The R3 in Figure 2B  
OUT and nOUT are low impedance follower outputs that generate ECL/LVPECL  
compatible outputs. Therefore, terminating resistors (DC current path to ground)  
or current sources must be used for functionality. These outputs are designed to  
drive 50W transmission lines. Matched impedance techniques should be used  
to maximize operating frequency and minimize signal distortion. Figures 1A and  
1B show two different layouts which are recommended only as guidelines. Other  
suitable clock layouts may exist and it would be recommended that the board  
designers simulate to guarantee compatibility across all printed circuit and clock  
component process variations.  
2.5V  
2.5V  
VCC=2.5V  
R1  
R3  
250  
250  
Zo = 50 Ohm  
Zo = 50 Ohm  
+
-
2.5V LVPECL  
2,5V LVPECL  
Zo = 50  
Driver  
R2  
62.5  
R4  
62.5  
OUT  
FIN  
Figure 2A: 2.5V LVPECL Driver Termination Example  
Zo = 50Ω  
50Ω  
50Ω  
2.5V  
VCC=2.5V  
VCC - 2V  
1
Zo = 50 Ohm  
Zo = 50 Ohm  
RTT =  
Zo  
RTT  
((VOH + VOL) / (VCC – 2)) – 2  
+
-
Figure 1A: 3.3V LVPECL Output Termination  
2.5V LVPECL  
2,5V LVPECL  
Driver  
3.3V  
R1  
50  
R2  
50  
125Ω  
125Ω  
R3  
18  
Z
o = 50Ω  
o = 50Ω  
OUT  
FIN  
Figure 2B: 2.5V LVPECL Driver Termination Example  
Z
2.5V  
VCC=2.5V  
84Ω  
84Ω  
Zo = 50 Ohm  
Zo = 50 Ohm  
+
-
Figure 1B: 3.3V LVPECL Output Termination  
2.5V LVPECL  
Driver  
Di
2,5V LVPECL  
R1  
50  
R2  
50  
Figure 2C: 2.5V LVPECL Termination Example  
ICS8Mx3 Datasheet Rev A  
3 of 4  
Revised 30Nov2004  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  
ICS8M 3  
X
Integrated  
Circuit  
Systems, Inc.  
Crystal Oscillator: LVPECL CLOCK  
O
UTPUT  
PRELIMINARY  
DEVICE PACKAGE OUTLINE - 6-pin, 5 x 7 x 1.5mm SMT CERHERMETIC  
DIMENSION IN MM  
NOMINAL TOLERANCE  
SYMBOL  
A
B
C
D1  
D2  
5
7
1.5  
2.54  
5.08  
2.6  
0.6  
1.4  
0.15  
0.15  
0.15  
0.13  
0.13  
0.13  
0.13  
E
F
G
H
J
0.13  
_
0.15 Ref.  
0.65 Ref.  
_
Device Package Outline  
ORDERING INFORMATION  
EXAMPLE OUTPUT FREQUENCIES  
Part Number:  
ICS8M x 3 -fff.fff r p t u  
75.000  
100.000  
150.000  
187.500  
250.000  
500.000  
625.000  
106.250  
155.520  
125.000  
156.250  
212.500  
312.500  
622.080  
Device  
200.000  
311.040  
600.000  
750.000  
Supply Voltage & Frequency Accuracy  
G = 3.3V  
H = 3.3V  
± 50 ppm  
±100 ppm  
J = 2.5/3.3V ± 50 ppm  
Consult ICS for the availability of other frequencies  
K = 2.5/3.3V ±100 ppm  
Output Type  
EXAMPLE PART NUMBERS  
3 = LVPECL  
Part/Order Number  
For option ...  
Marking  
Output Frequency (MHz)  
Leading zeroes dropped. Fourth decimal place added if  
necessary. See Standard Output Frequencies on right.  
Consult ICS for other frequencies.  
3.3 V  
50 ppm  
106.25 MHz  
(blank) Commercial  
Revision of Product  
A = Initial Release  
ICS8MG3-106.250AJ  
(blank) Tube (60 per tube)  
8MG3-106.250  
Package Type (individual devices)  
J = 5x7mm ceramic SMT  
2.5/3.3 V  
100 ppm  
625.00 MHz  
Industrial  
Ambient Temperature Range  
none = commercial = 0 to +70 o  
C
I = industrial = -40 to +85 o  
C
ICS8MK3-625.000AJIT  
Tape & Reel  
(1000)  
8MK3-625.000  
Bulk Packaging option  
none = tube (60 devices per tube)  
T = tape and reel (1000 devices)  
Note: Lead-free by default (no additional “LF” code needed)  
(Pb-free and RoHS compliant)  
ICS8Mx3 Datasheet Rev A  
4 of 4  
Revised 30Nov2004  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  

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