ICS9112AG-27-T [IDT]
9112 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.173 INCH, MO-153, LEAD FREE, TSSOP-8;
| 型号： | ICS9112AG-27-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 9112 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.173 INCH, MO-153, LEAD FREE, TSSOP-8 驱动 光电二极管 输出元件 |
| 文件： | 总12页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9112-27
Integrated
Circuit
Systems, Inc.
Low Skew PCI / PCI-X Buffer
General Description
The ICS9112-27 isahighperformance, lowskew, lowjitter
PCI / PCI-X clock driver. It is designed to distribute high
speed signals in PCI / PCI-X applications operating at
speeds from 0 to 140 MHz.
Features
•
•
•
•
Frequency range 0 - 140 MHz (3.3V)
Less than 200 ps Jitter between outputs
Skew controlled outputs < 100 ps
Distribute one clock input to one bank of four
outputs
•
•
3.3V 10ꢀ operation
Available in 8 pin TSSOP, and SOIC packages.
The ICS9112-27 ischaracterizedforoperationfrom-40°C
to 85°C for automotive and industrial applications.
Block Diagram
Pin Configuration
LOGIC
CONTROL
CLK_IN
OE
1
2
3
4
8
7
6
5
CLK3
CLK2
VDD
OE
CLK0
CLK1
CLK2
CLK3
CLK0
GND
CLK1
8 pin TSSOP & SOIC
Functionality Table
CLK_IN
INPUTS
OUTPUTS
CLK(3:0)
Tristate
0
CLK_IN
OE
0
0
0
1
1
1
0
Tristate
1
1
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
CLK_IN
OE
IN
Input reference frequency.
Output enable. When OE is low, it tristates the clock outputs
2
IN
3
4
5
6
7
8
CLK0
GND
CLK1
VDD
OUT
PWR
OUT
PWR
OUT
OUT
Buffered clock output
Ground
Buffered clock output
Power supply for 3.3V
Buffered clock output
Buffered clock output
CLK2
CLK3
0055G—04/26/05
ICS9112-27
Absolute Maximum Ratings
Supply voltage range VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.3 V
Input voltage rangeVI (see notes 1 & 2). . . . . . . . -0.5V to VDD + 0.5V
Output voltage range VO (see notes 1 & 2) . . . . . -0.5V to VDD + 0.5V
Input clamp current IIK (VI< 0 or VI >VDD) . . . . . . . . . . . . . . . . 50 mA
Output clamp current IOK (VO< 0 or VO) . . . . . . . . . . . . . . . . . 50 mA
Continuous total output current, IO (VO = 0 to VDD) . . . . . . . . . 50 mA
Package thermal impedance ØJA (see note 3): PW package230.5°C/W
Storage temperature rante, Tstg . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Notes:
1.The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings
areobserved.
2. This value is limited to 4.6 V maximum.
3.The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions
Min
Nom
Max
Unit
V
Supply voltage, V
3
3.3
3.6
DD
High-level input voltage, V
0.7 V
V
IH
X
DD
Low-level input voltage, V
0.3 V
V
IL
X
DD
Input voltage, V
0
V
DD
V
I
High-level output current, I
-24
24
85
mA
mA
°C
OH
Low-level output current, I
OL
Operating free-air temperature, T
-40
A
Timing requirements over recommended ranges of supply voltage and
operating free-air temperature
Min
Nom
Max
Unit
Clock frequency f
0
140
MHz
CLK
0055G—04/26/05
2
ICS9112-27
Electrical Characteristics at 3.3V
TA = -40° to 85°C; Supply Voltage VDD = 3.3 V +/-10ꢀ (unless otherwise stated)
PARAMETER
Input voltage
SYMBOL
VIK
CONDITIONS
VDD = 3.3V, II = -18 mA
VDD = min to max, IOH = -1 mA
VDD = 3V, IOH = -24 mA
VDD = 3V, IOH = 12 mA
VDD = min to max, IOH = 1 mA
VDD = 3V, IOH = 24 mA
VDD = 3V, IOH = 12 mA
VDD = 3V, VO = 1V
MIN
TYP
MAX UNITS
-1.2
V
VDD - 0.2 3.3
High-level Output Voltage
Low-level Output Voltage
VOH
2
2.3
2.7
V
2.4
0.022
0.61
0.31
-53
0.2
0.8
VOL
V
0.55
-40
High-level Input Current
Low-level Input Current
IOH
mA
mA
VDD = 3.3V, VO = 1.65V
VDD = 3V, VO = 2V
-54
40
-5
53
IOL
VDD = 3.3V, VO = 1.65V
V = VO or VDD
57
Input Current
II
5
mA
mA
pF
Dynamic Supply Current
Input Capacitance1
Output Capacitance1
IDD
CI
Unloaded outputs at 66.67 MHz
VDD = 3.3V, VI = 0V or 3.3V
VDD = 3.3V, VI = 0V or 3.3V
13
3
37
CO
3.2
pF
1. Guaranteed by design, not 100ꢀ tested in production.
Switching Characteristics at 3.3V
TA = -40° to 0 85°C; Supply Voltage VDD = 3.3 V +/-10ꢀ (For loading, see figures 1 and 2)
PARAMETER
SYMBOL
tPLH
CONDITIONS
VO = VDD/2
VO = VDD/2
VO = VDD/2
VO = VDD/2
VO = VDD/2
66 MHz
MIN
1.8
TYP
3.1
2.9
50
MAX UNITS
High-to-low Propagation Delay1
Low-to-high Propagation Delay1
3.8
3.8
ns
ns
ps
ps
ps
tPHL
1.8
Output Skew Window1
Tsk(o)
Tsk(p)
Tsk(pr)
100
300
500
1
Pulse Skew = | tPLH - tPHL
Process Skew1
|
6
3
6
3
CLKIN High Time1
CLKIN Low Time1
Thigh
ns
ns
140 MHz
66 MHz
Tlow
140 MHz
Output Rise Slew Rate1
Output Rise Slew Rate1
Tr
Tf
0.3 to 0.6 VDD
0.6 to 0.3 VDD
1.5
1.5
2.1
2.4
4
4
V/ns
V/ns
1. Guaranteed by design, not 100ꢀ tested in production.
0055G—04/26/05
3
ICS9112-27
Parameter Measurement Information
VDD
140W
CLKn
140W
10 pF
Figure 1. Test Load Circuit
VDD
50ꢀ VDD
0 V
CLKIN
tPLH
TPHL
VOH
0.6 VDD
0.6 VDD
50ꢀ VDD
0.2 VDD
50ꢀ VDD
0.2 VDD
VOL
CLK0-CLK3
tR
tf
Figure 2. Voltage Thresholds for Propagation Delay (tpd) Measurements
50ꢀ VDD
Any CLK
Any CLK
50ꢀ VDD
Figure 3. Output Skew
Tsk(0)
tcyc
Paramameter
Value
Unit
V
VIH(Min)
VIL(Max)
Vtest
0.5 VDD
0.35 VDD
0.4 VDD
thigh
V
0.6 VDD
VIH(Min)
Vtest
VIL(Max)
V
tlow
0.2 VDD
0.4 VDD
Peak to Peak (Minimum)
Figure 4. Clock Waveform
Note: All parameters in Figure 4 are according to PCI-X 1.0 specifications.
0055G—04/26/05
4
ICS9112-27
ICS9112AG-27
SUPPLY CURRENT
vs.
FREQUENCY
V
DD = 3.63 V, TA = 85oC
35
30
25
20
15
10
5
0
0
20
40
60
80
100
120
140
160
Frequency (MHz)
ICS9112AG-27
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VDD = 3.3V, TA = 25oC
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
-80
-70
-60
-50
-40
-30
-20
-10
IOH - High-Level Output Current (mA)
0055G—04/26/05
5
ICS9112-27
ICS9112AG-27
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VDD = 3.3V, TA = 25oC
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
10
20
30
40
50
60
70
IOL - Low-Level Output Current (mA)
0055G—04/26/05
6
ICS9112-27
4.40 mm. Body, 0.65 mm. Pitch TSSOP
(173 mil)
In Millimeters
(25.6 mil)
In Inches
c
N
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.19
0.09
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.012
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
1
2
E1
e
4.30
4.50
.169
0.0256 BASIC
.177
α
D
0.65 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
α
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
A1
VARIATIONS
- C -
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
2.90
MAX
3.10
MIN
.114
MAX
.122
b
8
aaa
C
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
4.40 mm. Body, 0.65 mm. pitch TSSOP
(0.0256Inch)
(173 mil)
Ordering Information
ICS9112yG-27LF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0055G—04/26/05
7
ICS9112-27
150 mil (Narrow Body) SOIC
C
In Millimeters
In Inches
N
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
1.35
0.10
0.33
0.19
MAX
1.75
0.25
0.51
0.25
MIN
MAX
.0688
.0098
.020
L
A
A1
B
C
D
E
e
H
h
L
.0532
.0040
.013
.0075
SEE VARIATIONS
.1497
0.050 BASIC
.2284
.010
.016
INDEX
AREA
H
E
.0098
SEE VARIATIONS
3.80
4.00
.1574
1.27 BASIC
h x 45°
1
2
5.80
0.25
0.40
6.20
0.50
1.27
.2440
.020
.050
D
α
A
N
α
SEE VARIATIONS
SEE VARIATIONS
A1
0°
8°
0°
8°
SEATING
PLANE
VARIATIONS
e
B
D mm.
D (inch)
N
.10 (.004)
MIN
4.80
MAX
5.00
MIN
MAX
8
.1890
.1968
Reference Doc.: JEDEC Publication 95, MS-012
10- 0 03 0
150 mil (Narrow Body) SOIC
Ordering Information
ICS9112yM-27LF-T
Example:
ICS XXXX y M LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
M = SOIC
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0055G—04/26/05
8
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Home > Products > Timing Solutions > PC-Notebook-Server Clocks > Single-ended I/O Fan-out and Zero Delay Buffers > 9112-27
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9112-27 (Single-ended I/O Fan-out and Zero Delay Buffers)
Description
Clock Buffer
Market Group
PC CLOCK
Additional Info
The ICS9112-27 is a high performance, low skew, low jitter PCI / PCI-X clock driver. It is designed to distribute high speed signals in PCI / PCI-X
applications operating at speeds from 0 to 140 MHz.
Related Orderable Parts
1 2
Attributes
Voltage
9112AG-27
3.3 V (PG8)
TSSOP 8
NA
9112AG-27LF
3.3 V (PGG8)
TSSOP 8
NA
9112AG-27LFT
9112AG-27T
3.3 V (PG8)
TSSOP 8
NA
9112AM-27
3.3 V (DC8)
SOIC 8
NA
9112AM-27LF
3.3 V (PGG8)
3.3 V (DCG8)
TSSOP 8
NA
SOIC 8
NA
Package
Speed
C
C
C
C
C
C
Temperature
Status
Active
Active
Active
No
Active
Active
No
Active
No
Yes
Yes
No
Sample
Minimum Order
Quantity
192
96
192
96
2500
2500
2500
2500
194
97
194
97
Factory Order
Increment
1 2
Related Documents
Type
Title
Size
Revision Date
Datasheet
9112-27 Datasheet
105 KB
03/22/2006
Home | Site Map | About IDT | Press Room | Investor Relations | Trademark | Privacy Policy | Careers | Register | Contact Us
Use of this website signifies your agreement to the acceptable use and privacy policy. Copyright 1997-2007 Integrated Device Technology, Inc. All Rights Reserved.
Node: www.idt.com
Global Sites
Search Entire Site
Contact IDT | Investors | Press
Email | Print
Document Search | Package Search | Parametric Search | Cross Reference Search | Green & RoHS | Calculators | Thermal Data | Reliability & Quality | Military
Home > Products > Timing Solutions > PC-Notebook-Server Clocks > Single-ended I/O Fan-out and Zero Delay Buffers > 9112-27
You may also like...
Add to myIDT [?]
9112-27 (Single-ended I/O Fan-out and Zero Delay Buffers)
Description
Clock Buffer
Market Group
PC CLOCK
Additional Info
The ICS9112-27 is a high performance, low skew, low jitter PCI / PCI-X clock driver. It is designed to distribute high speed signals in PCI / PCI-X
applications operating at speeds from 0 to 140 MHz.
Related Orderable Parts
1 2
Attributes
Voltage
9112AG-27
3.3 V (PG8)
TSSOP 8
NA
9112AG-27LF
3.3 V (PGG8)
TSSOP 8
NA
9112AG-27LFT
9112AG-27T
3.3 V (PG8)
TSSOP 8
NA
9112AM-27
3.3 V (DC8)
SOIC 8
NA
9112AM-27LF
3.3 V (PGG8)
3.3 V (DCG8)
TSSOP 8
NA
SOIC 8
NA
Package
Speed
C
C
C
C
C
C
Temperature
Status
Active
Active
Active
No
Active
Active
No
Active
No
Yes
Yes
No
Sample
Minimum Order
Quantity
192
96
192
96
2500
2500
2500
2500
194
97
194
97
Factory Order
Increment
1 2
Related Documents
Type
Title
Size
Revision Date
Datasheet
9112-27 Datasheet
105 KB
03/22/2006
Home | Site Map | About IDT | Press Room | Investor Relations | Trademark | Privacy Policy | Careers | Register | Contact Us
Use of this website signifies your agreement to the acceptable use and privacy policy. Copyright 1997-2007 Integrated Device Technology, Inc. All Rights Reserved.
Node: www.idt.com
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