ICS9112F-17-T [IDT]
PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SSOP-16;
| 型号： | ICS9112F-17-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SSOP-16 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9112-17
Integrated
Circuit
Systems,Inc.
Low Skew Output Buffer
General Description
Features
TheICS9112-17 isahighperformance, lowskew, lowjitter
zero delay buffer. It uses a phase lock loop (PLL)
technologytoalign, inbothphaseandfrequency, theREF
input with the CLKOUT signal. It is designed to distribute
high speed clocks in PC systems operating at speeds
from 25 to 133 MHz.
•
•
•
Zero input - output delay
Frequency range 25 - 133 MHz (3.3V)
High loop filter bandwidth ideal for Spread Spectrum
applications.
Less than 200 ps cycle to cycle Jitter
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 16 pin, 150 mil SSOP & SOIC package
•
•
•
•
ICS9112-17 is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to
theinputofthePLL. Sincetheskewbetweentheinputand
outputislessthan+/-350pS, thepartactsasazerodelay
buffer.
The ICS9112-17 hastwobanksoffouroutputscontrolled
bytwoaddresslines. Dependingontheselectedaddress
line, bank B or both banks can be put in a tri-state mode.
In this mode, the PLL is still running and only the output
buffers are put in a high impedance mode. The test mode
shuts off the PLL and connects the input directly to the
output buffers (see table below for functionality).
Pin Configuration
The ICS9112-17 comes in a sixteen pin 150 mil SOIC or
16 pin SSOP package. In the absence of REF input, will
beinthepowerdownmode. Inthismode, thePLListurned
offandtheoutputbuffersarepulledlow. Powerdownmode
provides the lowest power consumption for a standby
condition.
16 pin SSOP & SOIC
Block Diagram
Functionality
CLKA
(1, 4)
CLKB
(1, 4)
Output
Source Shutdown
PLL
FS2 FS1
CLKOUT
0
0
0
1
Tristate Tristate
Driven Tristate
Driven
Driven
PLL
PLL
PLL
N
N
PLL
PLL
1
1
0
1
Bypass Bypass Bypass
REF
PLL
Y
N
Mode
Mode
Mode
Driven Driven
Driven
0051J—02/05/04
ICS9112-17
Pin Descriptions
PIN NUMBER
PIN NAME
REF2
CLKA13
CLKA23
VDD
TYPE
IN
DESCRIPTION
Input reference frequency.
1
2
OUT
OUT
PWR
PWR
OUT
OUT
IN
Buffered clock output, Bank A
Buffered clock output, Bank A
Power Supply (3.3V)
3
4, 13
5, 12
6
GND
Ground
CLKB13
CLKB23
FS24
Buffered clock output. Bank B
Buffered clock output. Bank B
Select input, bit 2
7
8
9
FS14
IN
Select input, bit 1
10
11
14
15
16
CLKB33
CLKB43
CLKA33
CLKA43
CLKOUT3
OUT
OUT
OUT
OUT
OUT
Buffered clock output. Bank B
Buffered clock output. Bank B
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered clock output, internal feedback on this pin
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. Weakpull-down
3. Weak pull-down on all outputs
4. Weak pull-ups on these inputs
0051J—02/05/04
2
ICS9112-17
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input & Supply
TA = 0 - 70C; Supply Voltage VDD = 5.0 V +/-10% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating current
Input frequency
SYMBOL
VIH
CONDITIONS
MIN
2.0
TYP
MAX UNITS
2.5 VDD +0.5
0.8
V
V
VIL
GND -0.5
IIH
VIN = VDD
VIN = 0 V;
0.1
19
45
100
50
65
133
5
uA
uA
mA
MHz
pF
IIL
IDD1
Fi1
CL = 0 pF; FIN @ 66M
VDD = 3.3 V; All Outputs Loaded
Logic Inputs
25
1
CIN
Input Capacitance
1 Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input & Supply
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-10% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating current
Input frequency
SYMBOL
VIH
CONDITIONS
MIN
2.0
TYP
MAX UNITS
2.0 VDD+0.3
0.8
V
V
VIL
GND-0.3
IIH
VIN = VDD
VIN = 0 V;
0.1
19
30
100
50
uA
uA
mA
MHz
pF
IIL
IDD1
Fi1
CL = 0 pF; FIN @ 66M
VDD = 3.3 V; All Outputs Loaded
Logic Inputs
45
25
133
5.0
1
CIN
Input Capacitance
1Guarenteed by design, not 100% tested in production.
0051J—02/05/04
3
ICS9112-17
Electrical Characteristics - OUTPUT
TA = 0 - 70°C; VDD = VDDL = 5.0 V +/-10%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Rise Time1
SYMBOL
RDSP
CONDITIONS
VO = VDD*(0.5)
MIN TYP MAX UNITS
10
10
24
24
Ω
Ω
RDSN
VO = VDD*(0.5)
IOH = -8 mA
VOH
2.4
2.9
0.25
0.8
5.0
0.4
1.5
1.5
V
VOL
IOL = 8 mA
V
Tr
Tf
VOL = 0.8 V, VOH = 2.0 V
ns
ns
Fall Time1
VOH = 2.0 V, VOL = 0.8 V
Stable power supply, valid clock
presented on REF pin
1.0
PLL Lock Time1
Duty Cycle1
tLOCK
1.0
ms
Dt
VT = 1.4V;Cl=30pF
40
50
60
%
ps
ps
Tcyc-cyc at 66MHz , Loaded Outputs
Tcyc-cyc >66MHz , Loaded Outputs
250
200
Cycle to Cycle jitter1
Absolute Jitter1
Jitter; 1-Sigma1
Skew1
Tjabs
Tj1s
Tsk
10000 cycles; Cl=30pF
-100
60
14
100
30
ps
ps
ps
10000 cycles; Cl=30pF
VT = 1.4 V (Window) Output to Output
Measured at VDD/2 on the CLKOUT
pins of devices
250
Device to Device
Tdsk-Tdsk
0
0
700
700
ps
ps
Skew1
Delay Input-Output1
DR1
VT = 1.4 V
1 Guaranteed by design, not 100% tested in production.
Electrical Characteristics - OUTPUT
TA = 0 - 70°C; VDD = VDDL = 3.3 V +/-10%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Rise Time1
SYMBOL
RDSP
CONDITIONS
VO = VDD*(0.5)
MIN TYP MAX UNITS
10
10
24
24
Ω
Ω
RDSN
VO = VDD*(0.5)
IOH = -8 mA
VOH
2.4
2.9
0.25
1.2
3.3
0.4
2.0
2.0
V
VOL
IOL = 8 mA
V
Tr
Tf
VOL = 0.8 V, VOH = 2.0 V
ns
ns
Fall Time1
VOH = 2.0 V, VOL = 0.8 V
Stable power supply, valid clock
presented on REF pin
1.2
PLL Lock Time1
tLOCK
1.0
ms
Dt
Dt
VT = 1.4V;Cl=30pF
40
45
50
50
60
%
Duty Cycle1
VT = Vdd/2; Fout <66.6MHz
55
%
ps
ps
Tcyc-cyc at 66MHz , Loaded Outputs
Tcyc-cyc >66MHz , Loaded Outputs
250
200
Cycle to Cycle jitter1
Absolute Jitter1
Jitter; 1-Sigma1
Skew1
Tjabs
Tj1s
Tsk
10000 cycles; Cl=30pF
10000 cycles; Cl=30pF
-100
70
14
100
30
ps
ps
ps
VT = 1.4 V (Window) Output to Output
Measured at VDD/2 on the CLKOUT
pins of devices
250
1 Tdsk-Tdsk
0
0
700
700
ps
ps
Device to Device Skew
Delay Input-Output1
DR1
VT = 1.4 V
1 Guaranteed by design, not 100% tested in production.
0051J—02/05/04
4
ICS9112-17
Output to Output Skew
The skew between CLKOUT and the CLKA/B outputs is not dynamically adjusted by the PLL.Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLKA/B outputs are less loaded than CLKOUT, CLKA/B outputs will lead it; and if the CLKA/B is more loaded
than CLKOUT, CLKA/B will lag the CLKOUT.
SincetheCLKOUTandtheCLKA/Boutputsareidentical, theyallstartatthesametime, butdifferentloadscausethem
to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loadedEqually
REF input and CLKA/B
outputsloadedequally,with
CLKOUT loaded More.
REF input and CLKA/B
outputsloadedequally,with
CLKOUT loaded Less.
Timing diagrams with different loading configurations
0051J—02/05/04
5
ICS9112-17
Application Suggestion:
ICS9112-17 is a mixed analog/digital product. The analog portion of the PLL is very sensitive to any random noise
generated by charging or discharging of internal or external capacitor on the power supply pins. This type of noise will
cause excess jitter to the outputs of ICS9112-17. Below is a recommended lay out to alleviate any addition noise. For
additional information on FT.layout, please refer to our AN07.The 0.1 uF capacitors should be connected as close as
possible to power pins (4 & 13). An Isolated power plane with a 2.2 uF capacitor to ground will enhance the power line
stability.
33Ω
1 REF
CLKOUT 16
CLKA4 15
CLKA3 14
VDD 13
33Ω
33Ω
33Ω
33Ω
2 CLKA1
3 CLKA2
4 VDD
0.1µF
0.1µF
5 GND
GND 12
33Ω
33Ω
33Ω
33Ω
6 CLKB1
7 CLKB2
8 FS2
CLKB4 11
CLKB3 10
FS1
9
10KΩ
10KΩ
GND
VDD
GND
VDD
0051J—02/05/04
6
ICS9112-17
150 mil SSOP (QSOP)
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
In Inches
SYMBOL
MIN
1.35
0.10
--
0.20
0.18
MAX
1.75
0.25
1.50
0.30
0.25
MIN
.053
.004
--
.008
.007
MAX
.069
.010
.059
.012
.010
A
A1
A2
b
c
D
SEE VARIATIONS
SEE VARIATIONS
E
E1
e
5.80
3.80
0.635 BASIC
6.20
4.00
.228
.150
0.025 BASIC
.244
.157
L
0.40
1.27
.016
.050
N
SEE VARIATIONS
0° 8°
SEE VARIATIONS
SEE VARIATIONS
0° 8°
SEE VARIATIONS
α
ZD
VARIATIONS
D mm.
ZD
(Ref)
0.23
D (inch)
ZD
(Ref)
.009
N
MIN
4.80
MAX
5.00
MIN
.189
MAX
.197
16
Reference Doc.: JEDEC Publication 95, MO-137
10-0032
Ordering Information
ICS9112yF-17LF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0051J—02/05/04
7
ICS9112-17
150 mil (Narrow Body) SOIC
C
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
1.35
0.10
0.33
0.19
MAX
1.75
0.25
0.51
0.25
MIN
MAX
.0688
.0098
.020
L
A
A1
B
C
D
E
e
H
h
L
.0532
.0040
.013
.0075
SEE VARIATIONS
.1497
0.050 BASIC
.2284
.010
.016
INDEX
AREA
H
E
.0098
SEE VARIATIONS
3.80
4.00
.1574
1.27 BASIC
h xx 4455°°
1
2
5.80
0.25
0.40
6.20
0.50
1.27
.2440
.020
.050
D
α
A
N
α
SEE VARIATIONS
SEE VARIATIONS
A1
0°
8°
0°
8°
SEATING
PLANE
e
VARIATIONS
B
D mm.
D (inch)
N
.10 ((..000044))
MIN
9.80
MAX
10.00
MIN
MAX
16
.3859
.3937
Reference Doc.: JEDEC Publication 95, MS-012
10-0030
Ordering Information
ICS9112yM-17LF-T
Example:
ICS XXXX y M LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
M = SOIC
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0051J—02/05/04
8
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明