ICS9148YF-12-T [IDT]
Processor Specific Clock Generator, 66.6MHz, PDSO48, 0.300 INCH, SSOP-48;
| 型号： | ICS9148YF-12-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 66.6MHz, PDSO48, 0.300 INCH, SSOP-48 光电二极管 |
| 文件： | 总18页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9148-12
Integrated
Circuit
Systems, Inc.
TM
TM
TM
Frequency Timing Generator for Pentium/Pro or Transmeta Efficeon
General Description
ICS9148-12 is a Clock Synthesizer chip for Pentium/Pro-
basedDesktop/NotebooksystemsorTransmetaEfficeon
Mobile systems.
Features
•
CPU outputs are stronger drive for multiple loads
per pin (ie CPU and NB on one pin)
Generates system clocks for CPU, IOAPIC,
SDRAM, PCI, plus 14.314 MHz REF(0:1), USB,
Plus Super I/O
Supports single or dual processor systems
I2C serial configuration interface provides output
clock disabling and other functions
•
Features include four strong CPU, seven PCI and eight
SDRAM clocks. Two reference outputs are available
equal to the crystal frequency. Stronger drive CPUCLK
outputstypicallyprovidegreaterthan1V/nsslewrateinto
20pF loads.This device meets rise and fall requirements
with 2 loads per CPU output (ie, one clock to CPU and NB
chipset, one clock to two L2 cache inputs).
•
•
•
•
MODE input pin selects optional power
management input control pins
Two fixed outputs separately selectable as 24 or
48MHz
PWR_DWN# pin allows low power mode by stopping
crystal OSC and PLL stages. For optional power
management, CPU_STOP# can stop CPU (0:3) clocks
and PCI_STOP# will stop PCICLK (0:5) clocks.CPU and
IOAPICoutputbufferstrengthcontrolledbyCPU3.3_2.5#
pin to match VDDL voltage.
•
•
•
•
•
•
•
•
Separate 2.5V and 3.3V supply pins
2.5V or 3.3V outputs: CPU, IOAPIC
3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
CPU 3.3_2.5# logic pin to adjust output strength
No power supply sequence requirements
Uses external 14.318MHz crystal
48 pin 300 mil SSOP and 240 mil TSSOP
Outputenableregister
PCICLK outputs typically provide better than 1V/ns slew
rate into 30pF loads while maintaining 50 5% duty cycle.
The REF clock outputs typically provide better than 0.5V/
ns slew rates.
for serial port control:
1 = enable
0 = disable
The ICS9148-12 accepts a 14.318MHz reference crystal
or clock as its input and runs on a 3.3V core supply.
Pin Configuration
Block Diagram
48-Pin SSOP & TSSOP
Functionality
VDD (1:4) 3.3V 10%, VDDL1, 2 2.5 5% or 3.3 10% 0-70°C
Crystal (X1, X2) = 14.31818 MHz
CPUCLK, SDRAM PCICLK
SEL
(MHz)
(MHz)
0
1
60
30
66.6
33.3
0123I—07/18/05
Transmeta and Efficeon are trademarks of Transmeta Corporation.
Pentium/Pro is a trademark of Intel Corporation.
ICS9148-12
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
2, 1
REF (0:1)
OUT
Reference clock Output
3, 10, 17, 24,
31, 37, 43
GND
X1
PWR
IN
Ground (common)
4
Crystal or reference input, has internal crystal load cap
Crystal output, has internal load cap and feedback
resistor to X1
5
X2
OUT
6
MODE
VDD2
IN
PWR
OUT
OUT
IN
Input function selection
7, 15
Supply for PCICLK_F, PCICLK (0:5), nominal 3.3V
Free running PCI clock, not affected by PCI_STOP#
PCI clocks
8
PCICLK_F
PCICLK (0:5)
SEL66/60#
SDATA
9, 11, 12, 13, 14, 16
18
19
20
21
22
23
25
Selects 60MHz or 66.6MHz for SDRAM and CPU
I2C data input
IN
SCLK
IN
I2C clock input
VDD4
PWR
OUT
OUT
PWR
OUT
IN
Supply for 48/24MHzA, 48/24MHzB, nominal 3.3V
48/24MHz driver output for USB or Super I/O
48/24MHz driver output for USB or Super I/O
Supply for PLL core, nominal 3.3V
SDRAM clock 60/66.6MHz (selected)
Halts PCI Bus (0:5) at logic "0" level when low
SDRAM clock 60/66.6MHz (selected)
Halts CPU clocks at logic "0" level when low
48/24MHzA
48/24MHzB
VDD
SDRAM7
PCI_STOP#
SDRAM6
CPU_STOP#
26
OUT
IN
27
Supply for SDRAM (0:5), SDRAM6/CPU_STOP#,
SDRAM7/PCI_STOP#, nominal 3.3V
28, 34
VDD3
PWR
40
VDDL2
CPUCLK (0:3)
SDRAM (0:5)
PWR_DWN#
IOAPIC
PWR
OUT
OUT
IN
Supply for CPUCLK (0:3), either 2.5 or 3.3V nominal
CPUCLK clock output, powered by VDDL2
SDRAMs clock at 60 or 66.6MHz (selected)
Powers down chip, active low
42, 41, 39, 38
36, 35, 33, 32, 30, 29
44
45
46
OUT
PWR
IOAPIC clock output, (14.318MHz) powered by VDDL1
VDDL1
Supply for IOAPIC, either 2.5 or 3.3V nominal
3.3 or 2.5 VDD buffer strength selection, has pullup to
VDD, nominal 30K resistor.
47
CPU3.3-2.5#
VDD1
IN
48
PWR
Supply for REF (0:1), X1, X2, nominal 3.3V
Power Groups
VDD = Supply for PLL core
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#
VDD4 = 48/24MHzA, 48/24MHzB
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:3)
0123I—07/18/05
2
ICS9148-12
Power-On Conditions
SEL 66/60#
MODE
PIN #
DESCRIPTION
CPUCLKs
FUNCTION
66.6 MHz - w/serial config enable/disable
38, 39, 41, 42
36, 35, 33, 32,
30, 29, 27, 26
SDRAM
66.6 MHz - All SDRAM outputs
1
1
16, 14, 13, 12,
11, 9, 8
38, 39, 41, 42
36, 35, 33, 32,
30, 29, 27, 26
PCICLKs
CPUCLKs
SDRAM
33.3 MHz - w/serial config enable/disable
60 MHz - w/serial config enable/disable
60 MHz - w/serial config enable/disable
0
1
16, 14, 13, 12,
11, 9, 8
PCICLKs
PCI_STOP#
CPU_STOP#
PCICLK_F
CPUCLKs
SDRAM
30 MHz - w/serial config enable/disable
Power Management, PCI (0:5) Clocks
Stopped when low
Power Management, CPU (0:5) Clocks
Stopped when low
33.3 MHz - 33.3 MHz - PCI Clock Free running for
Power Management
66.6 MHz - CPU Clocks w/external Stop Control
and serial config individual enable/disable.
26
27
8
1
0
38, 39, 41, 42
36, 35, 33, 32,
30, 29
66.6 MHz - SDRAM Clocks w/serial config
individual enable/disable.
16, 14, 13, 12,
11, 9
33.3 MHz - PCI Clocks w/external Stop control and
serial config individual enable/disable.
PCICLKs
Power Management, PCI (0:5) Clocks
Stopped when low
Power Management, CPU (0:5) Clocks
Stopped when low
30 MHz - PCI Clock Free running for Power
Management
60 MHz - CPU Clocks w/external Stop control and
serial config individual enable/disable.
26
PCI_STOP#
CPU_STOP#
PCICLK_F
CPUCLKs
SDRAM
27
8
0
0
38, 39, 41, 42
36, 35, 33, 32,
30, 29
60 MHz - SDRAM Clocks w/serial config individual
enable/disable.
16, 14, 13, 12,
11, 9
30 MHz - PCI Clocks w/external Stop control and
serial config individual enable/disable.
PCICLKs
Example:
a) if MODE = 1, pins 26 and 27 are configured as SDRAM7 and SDRAM6 respectively.
b) if MODE = 0, pins 26 and 27 are configured as PCI_STOP# and CPU_STOP# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and “on” condition. The frequencies that are then
produced are on the MODE pin as shown in the table below.
CLOCK
REF (0:1)
IOAPIC 0
48/24 MHz
DEFAULT CONDITION AT POWER-UP
14.31818 MHz
14.31818 MHz
48 MHz
0123I—07/18/05
3
ICS9148-12
Technical Pin Function Descriptions
VDD(1,2,3,4)
device. See the Functionality Table for a list of the
specific frequencies that are available for these Clocks
and the selection codes to produce them.
This is the power supply to the internal core logic of the
device as well as the clock output buffers for REF(0:1),
PCICLK, 48/24MHzA/B and SDRAM(0:7).
SDRAM(0:7)
This pin operates at 3.3V volts. Clocks from the listed
buffers that it supplies will have a voltage swing from
Ground to this level. For the actual guaranteed high and
low voltage levels for the Clocks, please consult the DC
parameter table in this data sheet.
These Output Clocks are use to drive Dynamic RAM’s
and are low skew copies of the CPU Clocks. The voltage
swing of the SDRAM’s output is controlled by the supply
voltage that is applied toVDD3 of the device, operates at
3.3 volts.
VDDL1,2
48/24MHzA, B
This is the power supplies for the CPUCLK and IOAPCI
output buffers. The voltage level for these outputs may
be 2.5 or 3.3volts. Clocks from the buffers that each
supplies will have a voltage swing from Ground to this
level. For the actual Guaranteed high and low voltage
levels of these Clocks, please consult the DC parameter
table in this Data Sheet.
This is a fixed frequency Clock output that is typically
used to drive Super I/O devices. Outputs A and B are
defined as 24 or 48MHz by I2C register (see table).
IOAPIC
This Output is a fixed frequency Output Clock that runs
at the Reference Input (typically 14.31818MHz) . Its
voltage level swing is controlled by VDDL1 and may
operate at 2.5 or 3.3volts.
GND
This is the power supply ground (common or negative)
return pin for the internal core logic and all the output
buffers.
REF(0:1)
The REF Outputs are fixed frequency Clocks that run at
the same frequency as the Input Reference Clock X1 or
the Crystal (typically 14.31818MHz) attached across X1
and X2.
X1
This input pin serves one of two functions. When the
device is used with a Crystal, X1 acts as the input pin for
thereferencesignalthatcomesfromthediscretecrystal.
Whenthedeviceisdrivenbyanexternalclocksignal, X1
is the device input pin for that reference clock. This pin
also implements an internal Crystal loading capacitor
that is connected to ground. See the data tables for the
value of this capacitor.
PCICLK_F
This Output is equal to PCICLK(0:5) and is FREE
RUNNING, and will not be stopped by PCI_STP#.
PCICLK(0:5)
These Output Clocks generate all the PCI timing
requirements for a Pentium/Pro based system. They
conform to the current PCI specification.They run at 1/
2 CPU frequency.
X2
This Output pin is used only when the device uses a
Crystal as the reference frequency source. In this mode
ofoperation, X2isanoutputsignalthatdrives(orexcites)
the discrete Crystal. The X2 pin will also implement an
internal Crystal loading capacitor that is connected to
ground. See the Data Sheet for the value of this
capacitor.
SELECT 66.6/60MHz#
This Input pin controls the frequency of the Clocks at the
CPU, PCICLKandSDRAMoutputpins.Ifalogic“1”value
is present on this pin, the 66.6 MHz Clock will be
selected. If a logic “0” is used, the 60MHz frequency will
be selected.
CPUCLK(0:3)
These Output pins are the Clock Outputs that drive
processor and other CPU related circuitry that requires
clocks which are in tight skew tolerance with the CPU
clock. The voltage swing of these Clocks are controlled
by the Voltage level applied to the VDDL2 pin of the
0123I—07/18/05
4
ICS9148-12
Technical Pin Function Descriptions
MODE
CPU_STOP#
This Input pin is used to select the Input function of the
I/O pins. An active Low will place the I/O pins in the Input
mode and enable those stop clock functions.
This is a synchronous active Low Input pin used to stop
the CPUCLK clocks in an active low state. All other
ClocksincludingSDRAMclockswillcontinuetorunwhile
this function is enabled. The CPUCLK’s will have a turn
ON latency of at least 3 CPU clocks.This input pin only
valid when MODE=0 (Power Management Mode)
CPU3.3_2.5#
ThisInputpincontrolstheCPUandIOAPICoutputbuffer
strength for skew matching CPU and SDRAM outputs to
compensate for the externalVDDL supply condition.It is
important to use this function when selecting power
supplyrequirementsforVDDL1,2.Alogic“0”(ground)will
indicate 2.5V operation and a logic “1” will indicate 3.3V
operation.ThispinhasaninternalpullupresistortoVDD.
PCI_STOP#
This is a synchronous active Low Input pin used to stop
the PCICLK clocks in an active low state. It will not effect
PCICLK_Fnoranyotheroutputs.Thisinputpinonlyvalid
whenMODE=0(PowerManagementMode)
PWR_DWN#
This is an asynchronous active Low Input pin used to
Power Down the device into a Low Power state by not
removing the power supply. The internal Clocks are
disabledandtheVCOandCrystalarestopped. Powered
Down will also place all the Outputs in a low state at the
endoftheircurrentcycle. ThelatencyofPowerDownwill
not be greater than 3ms. The I2C inputs will beTri-Stated
and the device will retain all programming information.
This input pin only valid when MODE=0 (Power
ManagementMode)
I2C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in
the I2C protocol. It will allow read-back of the registers.
See configuration map for register functions. The I2C
specification in Philips I2C Peripherals Data Handbook
(1996) should be followed.
0123I—07/18/05
5
ICS9148-12
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controler (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0123I—07/18/05
6
ICS9148-12
SelectFunctions
Functionality
PCI,
PCI_F
24 MHz
Selection Selection
48 MHz
CPU
SDRAM
REF
IOAPIC
Tristate
HI - Z
HI - Z
HI - Z
HI - Z
HI - Z
HI - Z
HI - Z
Testmode
TCLK/21
TCLK/41
TCLK/21
TCLK1
TCLK1
TCLK/41
TCLK/21
Notes:
1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (default on Bits 7, 6, 5, 4, 1, 0 = 0)
(default on Bits 3, 2 = 1)
Note: PWD = Power-Up Default
BIT
Bit 7
Bit 6
PIN#
-
-
DESCRIPTION
PWD
0
0
Reserved
Must be 0 for normal operation
In Spread Spectrum, Controls type
(0=centered, 1=down spread)
In Spread Spectrum, Controls Spreading
(0=1.8% 1=0.6%)
Bit 5
Bit 4
-
0
0
Bit 3
Bit 2
23
22
48/24 MHz (Frequency Select) 1=48 MHz, 0=24 MHz
48/24 MHz (Frequency Select) 1=48 MHz, 0=24 MHz
1
1
Bit1
1
1
Bit0
1 - Tri-State
0 - Spread Spectrum Enable
1 - Testmode
Bit 1
Bit 0
-
0
0
0
0
0 - Normal operation
0123I—07/18/05
7
ICS9148-12
Byte2:PCICLKClockRegister
Byte 1: CPU, 24/48 MHz Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
Reserved
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
23
22
-
PWD
DESCRIPTION
48/24 MHz (Act/Inact)
48/24 MHz (Act/Inact)
Reserved
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
PCICLK_F (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
16
14
13
12
11
9
-
Reserved
38
39
41
42
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte4:SDRAMClockRegister
Byte3:SDRAMClockRegister
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
Reserved
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1(Act/Inact)
SDRAM0 (Act/Inact)
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
26
27
29
30
32
33
35
36
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 5: Peripheral Clock Register
Byte 6: Optional Register for Future
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
Reserved
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
Reserved
-
-
1
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
Reserved
45
-
IOAPIC0 (Act/Inact)
Reserved
-
Reserved
1
2
REF1 (Act/Inact)
REF0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
Note: PWD = Power-Up Default
0123I—07/18/05
8
ICS9148-12
Power Management
Clock Enable Configuration
Other Clocks,
SDRAM,
REF,
IOAPICs,
CPU_STOP# PCI_STOP# PWR_DWN#
CPUCLK
PCICLK
Crystal
VCOs
48/24 MHz A
48/24 MHz B
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Low
Low
Low
Low
Stopped
Running
Running
Running
Running
Off
Off
Running
Running
Running
Running
Running
Running
Running
Running
Low
33.3/30 MHz
Low
66.6/60 MHz
66.6/60 MHz
33.3/30 MHz
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During
power up and power down operations using the PWR PD# select pin will not cause clocks of a short or longer pulse
than that of the running clock.The first clock pulse coming out of a stopped clock condition may be slightly distorted
due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock
distortion also.
ICS9148-12PowerManagementRequirements
Latency
SIGNAL
SIGNAL STATE
No. of rising edges of free running
PCICLK
CPU_ STOP#
0 (Disabled)2
1 (Enabled)1
0 (Disabled)2
1
1
1
PCI_STOP#
1 (Enabled)1
1
PWR_DWN#
1 (Normal Operation)3
0 (Power Down)4
3mS
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only.
The REF and IOAPIC will be stopped independant of these.
0123I—07/18/05
9
ICS9148-12
CPU_STOP# Timing Diagram
CPUSTOP#isanasychronousinputtotheclocksynthesizer.ItisusedtoturnofftheCPUCLKsforlowpoweroperation.
CPU_STOP#issynchronizedbytheICS9148-12.TheminimumthattheCPUCLKisenabled(CPU_STOP#highpulse)
is 100 CPUCLKs.All other clocks will continue to run while the CPUCLKs are disabled.The CPUCLKs will always be
stoppedinalowstateandstartinsuchamannerthatguaranteesthehighpulsewidthisafullpulse.CPUCLKonlatency
is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions
may exist. This signal is synchronized to the CPUCLKs inside the
ICS9148-12.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-12. It is used to turn off the PCICLK (0:5) clocks for low power
operation.PCI_STOP# is synchronized by the ICS9148-12 internally.The minimum that the PCICLK (0:5) clocks are
enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state
and started with a full high pulse width guaranteed.PCICLK (0:5) clock on latency cycles are only one rising PCICLK
clock off latency is one PCICLK clock.
(Drawingshownonnextpage.)
0123I—07/18/05
10
ICS9148-12
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input.This signal is synchronized internal by the ICS9148-12 prior to its control
action of powering down the clock synthesizer.Internal clocks will not be running after the device is put in power down
state.When PD# is active (low) all clocks are driven to a low state and held prior to turning off theVCOs and the Crystal
oscillator.Thepoweronlatencyisguaranteedtobelessthan3mS.ThepowerdownlatencyislessthanthreeCPUCLK
cycles.PCI_STOP# and CPU_STOP# are don’t care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
0123I—07/18/05
11
ICS9148-12
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C
CaseTemperature . . . . . . . . . . . . . . . . . . . . . 115°C
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD + 0.3
0.8
UNITS
V
VIL
VSS - 0.3
V
IIH
VIN = VDD
0.1
2.0
-100
60
5
mA
mA
mA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
IDD3.3OP CL = 0 pF; Select @ 66M
100
600
Supply Current
Power Down
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
400
mA
Supply Current
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V;
14.318
MHz
pF
CIN
Logic Inputs
5
45
3
CINX
Ttrans
Ts
X1 & X2 pins
27
36
pF
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
mS
ps
TSTAB
3
TCPU-SDRAM1 VT = 1.5 V
TCPU-PCI1 VT = 1.5 V;
200
3.2
500
4.5
1.5
ns
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
CONDITIONS
MIN
TYP
5
MAX UNITS
IDD2.5OP CL = 0 pF; Select @ 66M
20
mA
Supply Current
Power Down
Supply Current
Skew1
IDD2.5PD CL = 0 pF;
0.21
1.0
mA
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads
TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
150
2.8
500
4
ps
ns
1
1Guaranteed by design, not 100% tested in production.
0123I—07/18/05
12
ICS9148-12
Electrical Characteristics - CPU
TA = 0 - 70°C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO2
CONDITIONS
MIN
60
TYP
MAX UNITS
66
20
20
MHz
Ω
1
RDSP2A
VO = VDD*(0.5)
10
1
RDSN2A
VO = VDD*(0.5)
IOH = -28 mA
10
Ω
VOH2A
VOL2A
IOH2A
IOL2A
2.4
2.5
0.35
-52
59
V
IOL = 27 mA
0.4
-48
V
VOH = 2.0 V
mA
mA
ns
ns
%
VOL = 0.8 V
49.3
45
1
tr2A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.1
0.95
51
2.85
2.85
55
1
Fall Time
tf2A
1
Duty Cycle
dt2A
1
Skew
tsk2A
VT = 1.5 V
80
250
250
150
+250
ps
ps
ps
ps
1
tjcyc-cyc2A VT = 1.5 V
170
60
1
Jitter
tj1s2A
VT = 1.5 V
VT = 1.5 V
1
tjabs2A
-250
100
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO2
CONDITIONS
MIN
60
TYP
MAX UNITS
66
20
20
MHz
Ω
1
RDSP2B
VO = VDD*(0.5)
10
1
RDSN2B
VO = VDD*(0.5)
IOH = -8.0 mA
10
Ω
VOH2B
VOL2B
IOH2B
IOL2B
2.1
2.15
0.3
-22
36
V
IOL = 21 mA
0.4
-18
V
VOH = 1.8 V
mA
mA
ns
ns
ns
ps
ps
ps
ps
VOL = 0.5 V
33
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.2
0.95
50
1.5
1.3
1
Fall Time
tf2B
1
Duty Cycle
dt2B
55
1
Skew
tsk2B
VT = 1.25 V
60
250
250
150
+250
1
tjcyc-cyc2B VT = 1.25 V
150
50
1
Jitter
tj1s2B
VT = 1.25 V
VT = 1.25 V
1
tjabs2B
-250
80
1Guaranteed by design, not 100% tested in production.
0123I—07/18/05
13
ICS9148-12
Electrical Characteristics - PCI
TA = 0 - 70°C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
30
TYP
-
MAX UNITS
33
55
55
MHz
Ω
1
RDSP1
VO = VDD*(0.5)
12
1
RDSN1
VO = VDD*(0.5)
IOH = -14.5 mA
IOL = 9.4 mA
12
Ω
VOH1
VOL1
IOH1
IOL1
2.4
2.7
0.2
-47
47.5
1.5
1.1
51
V
0.4
-22
V
VOH = 2.0 V
mA
mA
ns
ns
%
VOL = 0.8 V
17.1
45
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
1
Skew
tsk1
VT = 1.5 V
100
50
250
150
250
ps
ps
ps
1
Jitter
tj1s1
VT = 1.5 V
1
tjabs1
VT = 1.5 V
-250
120
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70°C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO3
CONDITIONS
MIN
60
TYP
MAX UNITS
66
24
24
MHz
Ω
1
RDSP3
VO = VDD*(0.5)
10
1
Ω
RDSN3
VO = VDD*(0.5)
IOH = -24 mA
IOL = 23 mA
10
VOH3
VOL3
IOH3
IOL3
2.4
2.5
0.35
-47
47.5
1.45
1.2
51
V
0.4
-40
V
VOH = 2.0 V
mA
mA
ns
ns
%
VOL = 0.8 V
41
45
1
Tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.7
1.5
55
1
Fall Time
Tf3
1
Duty Cycle
Dt3
1
Skew
Tsk3
VT = 1.5 V
80
250
150
250
ps
ps
ps
1
Jitter
Tj1s3
VT = 1.5 V
40
1
Tjabs3
VT = 1.5 V
-250
-
1Guaranteed by design, not 100% tested in production.
0123I—07/18/05
14
ICS9148-12
Electrical Characteristics - IOAPIC
TA = 0 - 70°C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO4
CONDITIONS
MIN
TYP
MAX UNITS
MHz
14.318
1
Ω
Ω
RDSP4A
VO = VDD*(0.5)
10
10
30
30
1
RDSN4A
VO = VDD*(0.5)
IOH = -13 mA
VOH4A
VOL4A
IOH4A
IOL4A
2.5
2.6
0.35
-29
37
V
IOL = 18 mA
0.4
-23
V
VOH = 2.0 V
mA
mA
ns
ns
%
VOL = 0.8 V
33
1
tr4A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.1
1.6
51
2
2
1
Fall Time
tf4A
1
Duty Cycle
dt4A
45
55
1
Jitter
tj1s4A
VT = 1.5 V
160
-
350
600
ps
ps
1
tjabs4A
VT = 1.5 V
-600
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO4
CONDITIONS
MIN
60
TYP
MAX UNITS
66
30
30
MHz
Ω
1
RDSP4B
VO = VDD*(0.5)
10
1
Ω
RDSN4B
VO = VDD*(0.5)
IOH = -5.5 mA
IOL = 9.0 mA
10
VOH4\B
VOL4B
IOH4B
2.1
2.2
0.25
-17
16
V
0.3
-15
V
VOH = 1.7 V
mA
mA
ns
ns
%
IOL4B
VOL = 0.7 V
15
1
tr4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.4
1.1
53
1.6
1.6
60
1
Fall Time
tf4B
1
Duty Cycle
dt4B
40
1
Jitter
tj1s4B
VT = 1.25 V
130
-
300
700
ps
ps
1
tjabs4B
VT = 1.25 V
-700
1Guaranteed by design, not 100% tested in production.
0123I—07/18/05
15
ICS9148-12
Electrical Characteristics - REF0
TA = 0 - 70°C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
FO7
CONDITIONS
MIN
TYP
14.318
MAX UNITS
MHz
RDSP7
RDSN7
VOH7
VOL7
VO = VDD*(0.5)
10
10
24
24
Ω
Ω
VO = VDD*(0.5)
IOH = -24 mA
2.4
2.5
0.35
-47
47.5
1.8
1.4
52
V
IOL = 23 mA
0.4
-40
V
IOH7
VOH = 2.0 V
mA
mA
ns
ns
%
IOL7
VOL = 0.8 V
41
1
Rise Time
Fall Time
Duty Cycle
Jitter
Tr7
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2
2
1
Tf7
1
Dt7
45
45
1
Tj1s7
VT = 1.5 V
150
-
350
600
ps
ps
1
Tjabs7
VT = 1.5 V
-600
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24M, 48M, REF(1:2)
TA = 0 - 70°C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Frequency
Output Frequency
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO24M
CONDITIONS
MIN
TYP
24
MAX UNITS
MHz
FO48M
48
MHz
FOREF
14.318
MHz
1
RDSP5
VO = VDD*(0.5)
20
20
60
60
Ω
Ω
1
RDSN5
VO = VDD*(0.5)
VOH5
VOL5
IOH5
IOL5
IOH = -16 mA
2.4
2.5
0.2
-29
25
V
IOL = 9 mA
0.4
-22
V
VOH = 2.0 V
mA
mA
ns
ns
%
VOL = 0.8 V
16
45
1
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.8
1.7
51
4
1
Fall Time
tf5
4
1
Duty Cycle
dt5
55
1
Jitter
tj1s5A
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
50
150
350
250
600
ps
1
tj1s5B
150
120
-
1
tjabs5A
-250
-600
1
tjabs5B
ps
1Guaranteed by design, not 100% tested in production.
0123I—07/18/05
16
ICS9148-12
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
MAX.
.110
.016
.092
.0135
.0085
MIN.
.620
NOM. MAX.
A
A1
A2
B
AC
.625
.630
48
C
.006
D
E
See Variations
.296
.292
.299
e
H
h
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
L
.032
N
See Variations
0°
.085
5°
.093
8°
.100
∝
X
This table in inches
Ordering Information
ICS9148yF-12LF-T
Example:
ICS XXXX y F PPP LF- T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
0123I—07/18/05
ICS = Standard Device
17
ICS9148-12
240 mil (6.10mm)TSSOP Package
VARIATIONS
COMMON
DIMENSIONS
SYMBOL
N
D
MIN. NOM. MAX.
MIN.
12.40
13.90
NOM.
12.50
14.00
MAX
12.60
14.10
A
A1
A2
b
—
—
—
1.10
0.15
0.95
0.27
0.20
48
56
0.05
0.85
0.17
0.09
0.90
—
C
—
D
E1
e
See Variations
6.00
6.10
0.50 BSC
8.10 BSC
0.60
6.20
E
Ordering Information
L
0.50
0.70
N
α
See Variations
—
ICS9148yG-12LF-T
Example:
0°
8°
Diminisions are in millimeters
ICS XXXX y G PPP LF- T
240TSSOP_AN
Designation for tape and reel packaging
Lead Free (Optional)
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0123I—07/18/05
18
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