ICS9161A-01CM16 [IDT]
Clock Generator, CMOS, PDSO16;
| 型号： | ICS9161A-01CM16 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, CMOS, PDSO16 光电二极管 |
| 文件： | 总15页 (文件大小：544K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9161A
Integrated
Circuit
Systems, Inc.
Dual Programmable Graphics Frequency Generator
General Description
Features
•
•
•
Pin-for-pin and function compatible with ICD2061A
The ICS9161A is a fully programmable graphics clock
generator.It can generate user-specified clock
frequencies using an externally generated input
reference or a single crystal.The output frequency is
programmed by entering a 24-bit digital word through
the serial port.Two fully user-programmable phase-
locked loops are offered in a single package. One PLL
is designed to drive the memory clock, while the
second drives the video clock.The outputs may be
changed on-the-fly to any desired frequency between
390 kHz and 120 MHz.The ICS9161A is ideally suited
for any design where multiple or varying frequencies
arerequired.
Dual programmable graphics clock generator
Memory and video clocks are individually
programmableon-the-fly
Ideal for designs where multiple or varying
frequencies arerequired
•
•
Increased frequency resolution from optional pre-
divide by 2 on the M counter
•
•
Output enable feature available for tristating outputs
Independent clock outputs range from 390 kHz to
120 MHz for VDD >4.75V
•
•
•
•
Power-downcapabilities
Low power, high speed 0.8µ CMOS technology
Glitch-free transitions
This part is ideal for graphics applications. It generates
lowjitter, highspeedpixelclocks.Itcanbeusedtoreplace
multiple, expensive high speed crystal oscillators. The
flexibility of the device allows it to generate non-standard
graphics clocks.
Available in 16-pin, 300-mil SOIC or PDIP package
The ICS9161A is also ideal in disk drives. It can generate
zone clocks for constant density recording schemes. The low
profile, 16-pin SOIC or PDIP package and low jitter outputs
are especially attractive in board space critical disk drives.
Theleaderintheareaofmultipleoutputclocksonasingle
chip,ICShasbeenshippinggraphicsfrequencygenerators
since October, 1990, and is constantly improving the
phase-lockedloop.The ICS9161Aincorporatesapatented
fourthgenerationPLLthatoffersthebestjitterperformance
available.
Block Diagram
EXTCLK EXTSEL
D14-D20
7
D0-D3
D11-D13
3
4
REF
DIVIDE
(M÷)
f
X1
X2
XTAL
OSC
REF
CMOS
OUTPUT
DRIVER
VCO OUTPUT
DIVIDER
R=1,2,4,8,16
32,64,128
VCO
MUX
VCLK
D4-D10
7
ADDRESS
24
CONTROL REG
REGISTERS
VCO
DIVIDE
(N÷)
21
21
VCLK
(D0-D20)
SEL0-CLK
Pscale
P= 2 or 4
3
3-TO-1
MUX
21
21
OE
DECODE
LOGIC
DATA
24
21
SEL1-DATA
21
D14-D20
7
D0-D3
4
D11-D13
MCLK
(D0-D20)
3
INIT1
INIT2
INIT
ROM
REF
DIVIDE
(M÷)
CMOS
OUTPUT
DRIVER
VCO
VCO OUTPUT
DIVIDER
R=1,2,4,8,16
32,64,128
MCLK
D4-D10
7
POR
VCO
DIVIDE
(N÷)
Pscale
P= 2
PD
0210I—03/21/05
9161
ICS9161A
Pin Configuration
16-Pin 300- mil SOIC or PDIP
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
Clock input in serial programming mode. Clock select pin in operating
mode. Has internal pull-down to GND.
1
SEL0-CLK
SEL1-DATA
IN
Data input in serial programming mode. Clock select pin in operating
mode. Has internal pull-down to GND.
2
IN
3
4
5
AVDD
OE
PWR
IN
Power.
Tristates outputs when low. Has internal pull-up to VDD.
Ground.
GND
PWR
Crystal input. This input includes XTAL load capacitance and feedback
bias for the crystal.
6
X1
IN
7
X2
OUT
OUT
OUT
OUT
IN
Crystal output which includes internal XTAL load capacitance.
Memory clock output.
8
MCLK
VCLK
ERROUT#
EXTCLK
INIT0
9
Video clock output.
10
11
12
13
14
Output low signals an error in the serially programmed word.
External clock input. Has internal pull-up to VDD.
Selects initial power-up conditions, LSB. Has internal pull-down to GND.
Power.
IN
VDD
PWR
IN
INIT1
Selects initial power-up conditions, MSB. Has internal pull-down to GND.
Selects external clock input (EXTCLK) as VCLK output. Has internal pull-
up to VDD.
15
16
EXTSEL
PD#
IN
IN
Power-down pin, active low. Has internal pull-up to VDD.
0210I—03/21/05
2
ICS9161A
Register Definitions
As seen in the VCLK Selection table, OE acts to tristate
theoutput.ThePD#pinforcestheVCLKsignalhighwhile
powering down the part. The EXTCLK pin will only be
multiplexed in when EXTSEL and SEL0 are logic 0 and
SEL1 is a logic 1.
The register file consists of the following six registers:
RegisterAddressing
Address
(A2 - A0)
The memory clock outputs are controlled by PD# and
OE as follows:
Register
REG0
REG1
REG2
MREG
PWRDWN
CNTL REG
Definition
000
001
010
011
100
110
Video Clock Register 1
Video Clock Register 2
Video Clock Register 3
Memory Register
Divisor for Power-down mode
Control Register
MCLK Selection
OE
PD#
MCLK
0
1
1
x
1
0
Tristate
MREG
PWRDWN
The ICS9161A places the three video clock registers and
the memory clock register in a known state upon power-
up.The registers are initialized based on the state of the
INIT1andINIT0pinsatapplicationofpowertothedevice.
TheINITpinsmustrampupwithVDDifalogical1oneither
pinisrequired.Theseinputpinsareinternallypulleddown
and will default to a logical 0 if left unconnected.
TheClockSelectpinsSEL0andSEL1havetwopurposes.
In serial programming mode, these pins act as the clock
and data pins. New data bits come in on SEL1 and these
bits are clocked in by a signal on SEL0.While these pins
are acquiring new information, the VCLK signal remains
unchanged.When SEL0 and SEL1 are acting as register
selects,atime-outintervalisrequiredtodeterminewhether
theuserisselectinganewregisterorwantstoprogramthe
part.During this initial time-out, theVCLK signal remains
at its previous frequency. At the end of this time-out
interval, a new register is selected. A second time-out
interval is required to allow the VCO to settle to its new
value. During this period of time, typically 5ms, the input
reference signal is multiplexed to the VCLK signal.
The registers are initialized as follows:
Register Initialization
INIT1
INIT0
MREG
REG0
REG1
REG2
0
0
1
1
0
1
0
1
32.500 25.175 28.322 28.322
40.000 25.175 28.322 28.322
50.350 40.000 28.322 28.322
56.644 40.000 50.350 50.350
When MCLK or the active VCLK register is being re-
programmed, then the reference signal is multiplexed
glitch-free to the output during the first time-out interval. A
second time-Register out interval is also required to allow
theVCO to settle.During this period, the reference signal
is multiplexed to the appropriate output signal.
Register Selection
When the ICS9161A is operating, the video clock output
is controlled with a combination of the SEL0, SEL1, PD#
and OE pins. The video clock is also multiplexed to an
external clock (EXTCLK) which can be selected with the
EXTSELpin.TheVCLKSelectionTableshowshowVCLK
is selected.
VCLK Selection
OE
PD#
EXTSEL
SEL1 SEL0
VCLK
0
1
1
1
1
1
1
x
0
1
1
1
1
1
x
x
x
x
0
1
x
x
x
0
0
1
1
1
x
x
0
1
0
x
1
Tristate
Forced High
REG0
REG1
EXTCLK
REG2
REG2
0210I—03/21/05
3
ICS9161A
Control Register Definitions
The control register allows the user to adjust various internal options.The register is defined as follows:
Bit
Bit Name
Default Value
Description
This bit determines which power-down mode the PD# pin will implement.
Power-down mode 1, C5=0, forces the MCLK signals to be a function of
the power-down register. Power-down mode 2, C5=1, turns off the crystal
and disables all outputs.
21
C5
0
This bit determines which clock is multiplexed to VCLK during frequency
changes. C4=0 multiplexes the reference frequency to the VCLK output.
C4=1 multiplexes MCLK to the VCLK output for applications where the
graphics controller cannot run as slow as fREF.
20
19
C4
C3
0
0
This bit determines the length of the time-out interval. The time-out interval
is derived from the MCLK VCO. If this VCO is programmed to certain
extremes, the time-out interval may be too short. C3=0, normal time-out.
C3=1, doubled time-out interval.
18
17
C2
C1
0
1
Reserved, must be set to 0.
This bit adjusts the duty cycle. C1=0 causes a 1ns decrease in output high
time. C1=1 causes no adjustment. If the load capacitance is high, the
adjustment can bring the duty cycle closer to 50%.
16
15
C0
0
0
Reserved, must be set to 0.
Acts on register 2. NS2=0 prescales the N counter by 2. NS2=1 prescales
the P counter value to 4.
NS2
Acts on register 1. NS1=0 prescales the N counter by 2. NS1=1 prescales
the P counter value to 4.
14
13
NS1
NS0
0
0
Acts on register 0. NS1=0 prescales the N counter by 2. NS0=1 prescales
the P counter value to 4.
0210I—03/21/05
4
ICS9161A
Serial Programming Architecture
Since the VCLK registers are selected by the SEL0 and
SEL1 pins, and since any change in their state may affect
The pins SEL0 and SEL1 perform the dual functions of the output frequency, new data input on the selection bits
select-ing registers and serial programming. In serial isonlypermittedtopassthroughthedecodelogicafterthe
programming mode, SEL0 acts as a clock pin while SEL1 watchdogtimerhastimedout.ThisdelayofSEL0orSEL1
actsasthedatapin.TheICS9161A-01maynotbeserially data permits a serial program cycle to occur without
programmedwheninpower-downmode.
affecting the current register selection.
In order to program a particular register, an unlocking
sequencemustoccur.Theunlockingsequenceisdetailed
in the following timing diagram:
Serial Data Register
Theserialdataisclockedintotheserialdataregisterinthe
order described in Figure 1 below (Serial DataTiming).
The serial data is sent as follows: An individual data bit is
sampledontherisingedgeofCLK.Thecomplementofthe
data bit must be sampled on the previous falling edge of
CLK.The setup and hold time requirements must be met
onbothCLKedges. Forspecificsontiming, seethetiming
diagrams on pages 10, 11 and 12.
The bits are shifted in this order: a start bit, 21 data bits,
3addressbits(whichdesignatethedesiredregister), and
a stop bit. A total of 24 bits must always be loaded into the
serialdataregisteroranerrorisissued. Followingtheentry
of the last data bit, a stop bit or load command is issued
by bringing DATA high and toggling CLK high-to-low and
low-to-high.The unlocking mechanism then resets itself
following the load. Only after a time-out period are the
SEL0 and SEL1 pins allowed to return to a register
selection function.
The unlock sequence consists of at least five low-to-high
transitionsofCLKwhiledataishigh, followedimmediately
byasinglelow-to-hightransitionwhiledataislow.Following
this unlock sequence, data can be loaded into the serial
dataregister.Thisprogrammingmustincludethestartbit,
shown in Figure 1.
Following any transition of CLK or DATA, the watchdog
timer is reset and begins counting. The watchdog timer
ensuresthatsuccessive risingedgesofCLKandDATAdo
not violate the time-out specification of 2ms. If a time-out
occurs, the lock mechanism is reset and the data in the
serial data register is ignored.
Figure 1: Serial Data Timing
0210I—03/21/05
5
ICS9161A
The equations used to determine the oscillator frequency
The serial data register is exactly 24 bits long, enough to
accept the data being sent. The stop bit acts as a load
command that passes the contents of the Serial Data
Register into the register indicated by the three address
bits. If a stop bit is not received after the serial register is
full, andmoredataissent, alldataintheregisterisignored
and an error issued. If correct data is received, then the
unlocking mechanism re-arms, all data in the serial data
register is ignored, and an error is issued.
a
r
e
:
N=N’ + 3 M=M’ + 2
FVCO=Prescale • N/M • FREF
where 3 ≤ M ≤ 129 and 4 ≤ N ≤ 130
and prescale=2 or 4, as set in the control register
(Where N is the VCO divider & M is the reference
divider)
The value of FVCO must remain between 50 MHz and 120
MHz. As a result, for output frequencies below 50 MHz,
FVCO must be brought into range. To achieve this, an
output divisor is selected by setting the values of the Mux
Field (R) as follows:
ERROUT# Operation
Any error in programming the ICS9161A is signaled by
ERROUT#. When the pin goes low, an error has been
detected.It stays low until the next unlock sequence.The
signal is invoked for any of the following errors: incorrect
start bit, incorrect data encoding, incorrect length of data
word, and incorrect stop bit.
OutputDivisor
R
Divisor
000
001
010
011
100
101
110
111
1
2
4
Programming the ICS9161A
8
The ICS9161A has a wide operating range, but it is
recommendedthatitisoperatedwithinthefollowinglimits:
16
32
64
128
4.75V< VDD <5.25V
VDD supply voltage
Unlike the ICD2061A, the ICS9161A’s VCO does not
requiretuningtoplaceitincertainranges.TheICS9161A’s
VCO will operate from 50 MHz to 120 MHz without
adjustingtheVCOgain.However, tomaintaincompatibility,
the I bits are programmed as in the ICD2061A.
1 MHz <FREF <60 MHz
200 kHz <FREF/M <5 MHz
50 MHz < FVCO <120 MHz
FCLK ≤ 120 MHz
FREF=InputReference
Frequency
M=Reference divide 3
to 129
FVCO=VCO output
frequency
FCLK=output frequency
These bits are dummy bits except for the following two
cases:
The frequency of the programmable oscillator FVCO is
determined by the following fields:
Index Field (I)
I
VCLK FVCO
MCLK FVCO
Field
# of Bits
1110
1111
Turn off VCLK
Mux MCLK to VLCK
50 - 120 MHz
50 - 120 MHz
Index (I)
N counter value (N')
Mux (R)
4
7
3
7
Whentheindexfieldissetto1111,VCLKisturnedoffand
bothchannelsrunfromthesameMCLKVCO.Thisisdone
in an effort to reduce jitter, which may increase when
VCOsrunat2n multiplesofoneanother.Ifthetwooutputs
havetobemultiplesofoneanother, itisbesttomuxMCLK
overtotheoutputoftheVCLKVCOandtopower-downthe
VCLK VCO. The multiplexed frequency will be divided
down by the correct divisor (M) and output on VCLK.
M counter value (M')
Where the least significant bit is the last bit of M and the
most significant bit is the first bit of I.
0210I—03/21/05
6
ICS9161A
Power Management Issues
Power-down mode 2
Whenthereisnoneedforanyoutputduringpower-down,
an alternate mode is available which will completely shut
down all outputs and the reference oscillator, but still
preserves all register contents. Power-down mode 2 in
invoked by first programming the power-down bit in the
CNTL register and then pulling the PD# pin low.
Power-down mode 1
The ICS9161A contains a mechanism to reduce the
quiescent power when stand-by operation is desired.
Power-down mode 1 is invoked by polling PD# low and
having the proper CNTL register bit set to zero. In this
mode, VCOs are shut down, the VCLK output is forced
high, and the MCLK output is set to a user-defined low
frequency value to refresh dynamic RAM.
The PD# pin
ThePD#pinhasastandardinternalpull-upresistorduring
normal operation. When the chip goes into power-down
mode 1 or 2, the normal pull-up resistor is dynamically
switched to a weak pull-up, which reduces power
consumption. If the PD# pin is allowed to float after it has
Thepower-downMCLKvalueisdeterminedbythefollowing
equation:
MCLKPD = FREF/(PWRDWN register divisor value)
been
pulled
down, theweakpull-upwillbringthesignalhighandallow
the device to resume operation.
The power-down register divisor is determined according
to the 4-bit word programmed into the PWRDWN register
(see table below).
Power-Down Register Table
PWRDWN bits
PWRDWN
Power-down
Divisor
MCLKPD
P3
P2
P1
P0
Register Value
(fREF=14.31818)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
n/a
32
30
28
26
24
22
20
18
16
14
12
10
8
n/a
447.4 kHz
477.3 kHz
511.4 kHz
550.7 kHz
596.6 kHz
650.8 kHz
715.9 kHz
795.5 kHz
894.9 kHz
1.02 MHz
1.19 MHz
1.43 MHz
1.79 MHz
2.39 MHz
3.58 MHz
8 (default)
9
A
B
C
D
E
F
6
4
0210I—03/21/05
7
ICS9161A
Absolute Maximum Ratings
VDD referenced to GND..........................................7V
Operatingtemperatureunderbias(TOPER) ..............0°C to 70°C
Storagetemperature ...............................................-40°C to +150°C
Max. soldering temperature (10 sec) (TSOL) ............+260°C
Voltage on I/O pins referenced to GND ...................GND -0.5V to VDD +0.5V
Junctiontemperature(Tj) ........................................+125°C
Power dissipation ....................................................0.35Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device.This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 5.0V
VDD = +5V 5%, 0°C ≤ TAMBIENT ≤ +70°C
DC Characteristics
PARAMETER
High level input voltage
Low level input voltage
SYMBOL
VIH
TEST CONDITIONS
MIN
2.0
-
TYP
MAX
-
UNITS
-
-
-
-
V
V
V
V
VIL
0.8
-
High level CMOS output voltage1
Low level output voltage1
VOH
IOH=-4mA
IOL=4mA
3.84
-
VOL
0.4
VDD=VIH=5.25V for pull-
downs
Input high current
IIH
-
-
100
µA
Input low current
IIL
IOZ
VIL=0V for pull-ups
(tristate)
-250
-
-
-
µA
µA
Output leakage current
Power supply current
Power supply current (typical)
Analog power supply current
Power-down current (Mode 1)
Power-down current (Mode 2)
Input capacitance1
-10
10
65
-
IDD
15
-
-
mA
mA
mA
mA
µA
IDD-TYP
IADD
IPD1
IPD2
CIN
@60 MHz
35
-
-
20
7.5
50
10
-
6
25
-
-
-
pF
Note
1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
0210I—03/21/05
8
ICS9161A
Electrical Characteristics at 5.0V (continued)
AC Characteristics
DESCRIPTION
Reference oscillator value2
1/fREF
NAME
SYMBOL
MIN
1
TYP
14.31818
69.8408
-
MAX
60
UNITS
MHz
ns
Reference
frequency
fREF
tREF
t1
Reference period
16.6
25%
1000
75%
Duty cycle for the input oscillator
defined as t1/tREF
Input duty cycle
-
Output clock
periods
8.33 (120
MHz)
2564 (390
kHz)
Output oscillator values
t2
t3
t4
-
-
-
ns
-
Duty cycle for the output oscillators3
Output duty cycle
Rise times
45%
-
55%
3
Rise time for the output oscillators
into a 25pF load
ns
Fall time for the output oscillators into
a 25pF load
Fall times
t5
-
-
3
ns
Old frequency output
New frequency output
freq1 output
freq2 output
tfreq1
tfreq2
-
-
-
-
-
-
-
-
Time clock output remains high while
output muxes to reference frequency
f
REF mux time
tA
ttime-out
tB
0.5 tREF
-
5
1.5tREF
ns
ms
ns
Interval for serial programming and
for VCO changes to settle4
Time-out interval
2
10
-
Time clock output remains high while
output muxes to new frequency value
t
freq2muxtime
0.5 tREF
1.5 tREF
Time for the output oscillators to go
into tristate mode after OUTDIS-
signal assertion
Tristate
t6
-
-
25
12
-
-
ns
ns
Time for the output oscillators to
recover from tristate mode after
OUTDIS-signal goes high
CLK valid
t7
Time for power-down mode of
operation to take effect
Power-down
t8
t9
-
25
12
-
-
ns
ns
ns
ns
Time for recovery from power-down
mode to a valid CLK
Power-up
-
0
-
Time for MCLK to go high after
PWRDWN is asserted high
MCLKOUT high
MCLKOUT delay
t10
tPWRDWN
Delay of MCLK prior to fMCLK signal at
output
t11
0.5 tMCLK
-
1.5 tMCLK
Clock period of serial clock
Set-up time
tserclk
tSU
2 • tREF
20
-
-
-
-
2
ms
ns
ns
ns
-
-
Hold time
tHD
10
Load command
tldcmd
0
t1+30
Notes:
1.Parameter guaranteed by design and characterization.Not 100% tested in production.
2. For reference frequencies other than 14.81818 MHz, the pre-loaded ROM frequencies will shift proportionally.
3. Duty cycle is measured at CMOS threshold levels. At 5 volts, VTH=2.5 volts.
4. If the interval is too short, see the time-out interval section in the control register definition.
0210I—03/21/05
9
ICS9161A
Rise and Fall Times
TristatedTiming
0210I—03/21/05
10
ICS9161A
SelectionTiming
MCLK and ActiveVCLK Register ProgrammingTiming
0210I—03/21/05
11
ICS9161A
Soft Power-Down Timing (Mode 2)
Serial ProgrammingTiming
0210I—03/21/05
12
ICS9161A
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1) All clock outputs should have series
terminating resistor. Not shown in
all places to improve readibility of
diagram.
2) 47 ohm / 56pf RC termination
should be used on all over 50MHz
outputs.
3) Optional crystal load capacitors are
recommended.
CapacitorValues:
C1, C2 : Crystal load values determined by user
C3 : 100pF ceramic
All unmarked capacitors are 0.01µF ceramic
ConnectionstoVDD:
0210I—03/21/05
13
ICS9161A
16-Pin PDIP Package
Ordering Information
ICS9161A-01CN16LF
Example:
ICS XXXX- PPP M X#WLF
Annealed Lead Free (Optional)
Lead Count & Package Width
Lead Count=1, 2 or 3 digits
W=.3” SOIC or .6” DIP; None=Standard Width
Package Type
N=DIP (Plastic)
Pattern Number (2 or 3 digit number for parts with ROM code patterns, if applicable)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device
0210I—03/21/05
14
ICS9161A
LEAD COUNT
DIMENSION L
16L
0.404
SOIC Package (wide body)
Ordering Information
ICS9161A-01CW16
Example:
ICS XXXX- PPP M X#WLF
Annealed Lead Free (Optional)
Lead Count & Package Width
Lead Count=1, 2 or 3 digits
W=.3” SOIC or .6” DIP; None=Standard Width
Package Type
M=SOIC
Pattern Number (2 or 3 digit number for parts with ROM code patterns, if applicable)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device
0210I—03/21/05
15
相关型号：
SI9130DB
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