ICS9161A-01CW16WLF [IDT]

Video Clock Generator, 120MHz, CMOS, PDSO16, 0.300 INCH, SOIC-16;


型号：	ICS9161A-01CW16WLF
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Video Clock Generator, 120MHz, CMOS, PDSO16, 0.300 INCH, SOIC-16 光电二极管
文件：	总15页 (文件大小：539K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Integrated

Circuit

Systems, Incꢀ

ICS9161A

Dual Programmable Graphics Frequency Generator

General Description

Features

•

Pin-for-pin and function compatible with ICD2061A

The ICS9161A is a fully programmable graphics clock

generatorꢀ It can generate user-specified clock frequencies

usinganexternallygeneratedinputreferenceorasinglecrystalꢀ

The output frequency is programmed by entering a 24-bit

digital word through the serial portꢀ Two fully user-

programmable phase-locked loops are offered in a single

packageꢀ One PLL is designed to drive the memory clock,

while the second drives the video clockꢀ The outputs may be

changed on-the-fly to any desired frequency between 390 kHz

and 120 MHzꢀ The ICS9161A is ideally suited for any design

where multiple or varying frequencies are requiredꢀ

Dual programmable graphics clock generator

Memory and video clocks are individually

programmable on-the-fly

•

Ideal for designs where multiple or varying frequencies

are required

Increased frequency resolution from optional pre-

divide by 2 on the M counter

•

Output enable feature available for tristating outputs

Independent clock outputs range from 390 kHz to 120

MHzforVDD>4.75V

This part is ideal for graphics applicationsꢀ It generates low

jitter, high speed pixel clocksꢀ It can be used to replace multiple,

expensive high speed crystal oscillatorsꢀ The flexibility of the

device allows it to generate non-standard graphics clocksꢀ

•

Power-down capabilities

Low power, high speed 0.8µ CMOS technology

Glitch-free transitions

Available in 16-pin, 300-mil SOIC or PDIP package

The ICS9161A is also ideal in disk drives. It can generate

zone clocks for constant density recording schemes. The low

profile, 16-pin SOIC or PDIP package and low jitter outputs

are especially attractive in board space critical disk drives.

The leader in the area of multiple output clocks on a single

chip, ICS has been shipping graphics frequency generators

since October, 1990, and is constantly improving the phase-

locked loopꢀ The ICS9161A incorporates a patented fourth

generationPLLthatoffersthebestjitterperformanceavailableꢀ

Block Diagram

EXTCLK EXTSEL

D14-D20

D0-D3

D11-D13

REF

DIVIDE

(M÷)

XTAL

OSC

REF

CMOS

OUTPUT

DRIVER

VCO OUTPUT

DIVIDER

R=1,2,4,8,16

32,64,128

VCO

MUX

VCLK

D4-D10

ADDRESS

CONTROL REG

REGISTERS

VCO

DIVIDE

(N÷)

VCLK

(D0-D20)

SEL0-CLK

Pscale

P= 2 or 4

3-TO-1

MUX

DECODE

LOGIC

DATA

SEL1-DATA

D14-D20

D0-D3

D11-D13

MCLK

(D0-D20)

INIT1

INIT2

INIT

ROM

REF

DIVIDE

(M÷)

CMOS

OUTPUT

DRIVER

VCO

VCO OUTPUT

DIVIDER

R=1,2,4,8,16

32,64,128

MCLK

D4-D10

POR

VCO

DIVIDE

(N÷)

Pscale

P= 2

9161-A RevG 10/04/00

ICS reserves the right to make changes in the device data identified in this publication

without further notice. ICS advises its customers to obtain the latest version of all

device data to verify that any information being relied upon by the customer is current

and accurate.

9161

ICS9161A

Pin Configuration

16-Pin 300- mil SOIC or PDIP

Pin Descriptions

PIN NUMBER

PIN NAME

SEL0-CLK

TYPE

DESCRIPTION

Clock input in serial programming mode. Clock select pin in operating mode.

Has internal pull-down to GND.

Data input in serial programming mode. Clock select pin in operating mode. Has

internal pull-down to GND.

SEL1-DATA

AVDD

PWR

Power.

Tristates outputs when low. Has internal pull-up to VDD.

Ground.

GND

PWR

Crystal input. This input includes XTAL load capacitance and feedback bias for

the crystal.

OUT

Crystal output which includes internal XTAL load capacitance.

Memory clock output.

MCLK

VCLK

ERROUT#

EXTCLK

INIT0

Video clock output.

Output low signals an error in the serially programmed word.

External clock input. Has internal pull-up to VDD.

Selects initial power-up conditions, LSB. Has internal pull-down to GND.

Power.

VDD

PWR

INIT1

Selects initial power-up conditions, MSB. Has internal pull-down to GND.

Selects external clock input (EXTCLK) as VCLK output. Has internal pull-up to

VDD.

EXTSEL

PD#

Power-down pin, active low. Has internal pull-up to VDD.

ICS9161A

As seen in the VCLK Selection table, OE acts to tristate the

outputꢀ The PD# pin forces the VCLK signal high while

powering down the partꢀ The EXTCLK pin will only be

multiplexed in when EXTSEL and SEL0 are logic 0 and SEL1

is a logic 1ꢀ

The register file consists of the following six registers:

Address

(A2 - A0)

The memory clock outputs are controlled by PD# and OE

as follows:

REG0

REG1

REG2

MREG

PWRDWN

CNTL REG

Definition

000

001

010

011

100

110

Video Clock Register 1

Video Clock Register 2

Video Clock Register 3

Memory Register

Divisor for Power-down mode

Control Register

MCLK Selection

PD#

MCLK

Tristate

MREG

PWRDWN

The ICS9161A places the three video clock registers and the

memory clock register in a known state upon power-upꢀ The

registers are initialized based on the state of the INIT1 and

INIT0 pins at application of power to the deviceꢀ The INIT pins

must ramp up with VDD if a logical 1 on either pin is requiredꢀ

These input pins are internally pulled down and will default to

a logical 0 if left unconnectedꢀ

The Clock Select pins SEL0 and SEL1 have two purposesꢀ In

serial programming mode, these pins act as the clock and data

pinsꢀ New data bits come in on SEL1 and these bits are

clocked in by a signal on SEL0ꢀ While these pins are acquiring

new information, the VCLK signal remains unchangedꢀ When

SEL0 and SEL1 are acting as register selects, a time-out

interval is required to determine whether the user is selecting

a new register or wants to program the partꢀ During this initial

time-out, the VCLK signal remains at its previous frequencyꢀ

At the end of this time-out interval, a new register is selectedꢀ

A second time-out interval is required to allow the VCO to

settle to its new valueꢀ During this period of time, typically

5ms, the input reference signal is multiplexed to the VCLK

signalꢀ

The registers are initialized as follows:

INIT1

INIT0

MREG

REG0

REG1

REG2

32.500

40.000

50.350

56.644

25.175

40.000

28.322

50.350

28.322

50.350

When MCLK or the active VCLK register is being re-

programmed, then the reference signal is multiplexed glitch-

free to the output during the first time-out intervalꢀ A second

time-Register out interval is also required to allow the VCO

to settleꢀ During this period, the reference signal is

multiplexed to the appropriate output signalꢀ

When the ICS9161A is operating, the video clock output is

controlled with a combination of the SEL0, SEL1, PD# and

OE pinsꢀ The video clock is also multiplexed to an external

clock (EXTCLK) which can be selected with the EXTSEL

pinꢀTheVCLK SelectionTable shows howVCLK is selectedꢀ

VCLK Selection

PD#

EXTSEL

SEL1 SEL0

VCLK

Tristate

Forced High

REG0

REG1

EXTCLK

REG2

ICS9161A

Control Register Definitions

The control register allows the user to adjust various internal optionsꢀ The register is defined as follows:

Bit

Bit Name

Default Value

Description

This bit determines which power-down mode the PD# pin will implement.

Power-down mode 1, C5=0, forces the MCLK signals to be a function of the

power-down register. Power-down mode 2, C5=1, turns off the crystal and

disables all outputs.

This bit determines which clock is multiplexed to VCLK during frequency

changes. C4=0 multiplexes the reference frequency to the VCLK output. C4=1

multiplexes MCLK to the VCLK output for applications where the graphics

controller cannot run as slow as f_REF.

This bit determines the length of the time-out interval. The time-out interval is

derived from the MCLK VCO. If this VCO is programmed to certain extremes,

the time-out interval may be too short. C3=0, normal time-out. C3=1, doubled

time-out interval.

Reserved, must be set to 0.

This bit adjusts the duty cycle. C1=0 causes a 1ns decrease in output high time.

C1=1 causes no adjustment. If the load capacitance is high, the adjustment can

bring the duty cycle closer to 50%.

Reserved, must be set to 0.

Acts on register 2. NS2=0 prescales the N counter by 2. NS2=1 prescales the P

counter value to 4.

NS2

Acts on register 1. NS1=0 prescales the N counter by 2. NS1=1 prescales the P

counter value to 4.

NS1

NS0

Acts on register 0. NS1=0 prescales the N counter by 2. NS0=1 prescales the P

counter value to 4.

ICS9161A

SerialProgrammingArchitecture

Since the VCLK registers are selected by the SEL0 and SEL1

pins, and since any change in their state may affect the output

The pins SEL0 and SEL1 perform the dual functions of select- frequency, new data input on the selection bits is only permitted

ing registers and serial programmingꢀ In serial programming to pass through the decode logic after the watchdog timer has

mode, SEL0 acts as a clock pin while SEL1 acts as the data pinꢀ timed outꢀ This delay of SEL0 or SEL1 data permits a serial

The ICS9161A-01 may not be serially programmed when in program cycle to occur without affecting the current register

power-down modeꢀ

selectionꢀ

In order to program a particular register, an unlocking sequence

must occurꢀThe unlocking sequence is detailed in the following

timing diagram:

Serial Data Register

The serial data is clocked into the serial data register in the

order described in Figure 1 below (Serial Data Timing)ꢀ

The serial data is sent as follows: An individual data bit is

sampled on the rising edge of CLKꢀ The complement of the

data bit must be sampled on the previous falling edge of CLKꢀ

The setup and hold time requirements must be met on both

CLK edgesꢀ For specifics on timing, see the timing diagrams

on pages 10, 11 and 12ꢀ

The bits are shifted in this order: a start bit, 21 data bits, 3

address bits (which designate the desired register), and a stop

bitꢀ A total of 24 bits must always be loaded into the serial data

data bit, a stop bit or load command is issued by bringing

DATA high and toggling CLK high-to-low and low-to-highꢀ

The unlocking mechanism then resets itself following the

loadꢀ Only after a time-out period are the SEL0 and SEL1 pins

allowed to return to a register selection functionꢀ

The unlock sequence consists of at least five low-to-high

transitions of CLK while data is high, followed immediately

by a single low-to-high transition while data is lowꢀ Following

this unlock sequence, data can be loaded into the serial data

registerꢀ This programming must include the start bit, shown

in Figure 1ꢀ

Following any transition of CLK or DATA, the watchdog

timer is reset and begins countingꢀ The watchdog timer

ensures that successive rising edges of CLK and DATAdo not

violate the time-out specification of 2msꢀ If a time-out

occurs, the lock mechanism is reset and the data in the serial

data register is ignoredꢀ

Figure 1: Serial Data Timing

ICS9161A

The equations used to determine the oscillator frequency are:

The serial data register is exactly 24 bits long, enough to

accept the data being sentꢀ The stop bit acts as a load command

that passes the contents of the Serial Data Register into the

received after the serial register is full, and more data is sent,

all data in the register is ignored and an error issuedꢀ If correct

data is received, then the unlocking mechanism re-arms, all

data in the serial data register is ignored, and an error is

issuedꢀ

N=N + 3 M=M + 2

F_VCO=Prescale N/M F_REF

where 3 £ M £ 129 and 4 £ N £ 130

and prescale=2 or 4, as set in the control register

(Where N is the VCO divider & M is the reference divider)

ThevalueofF_VCOmustremainbetween50MHzand120MHzꢀ

As a result, for output frequencies below 50 MHz, F_VCOmust

be brought into rangeꢀ To achieve this, an output divisor is

selected by setting the values of the Mux Field (R) as follows:

ERROUT# Operation

Any error in programming the ICS9161A is signaled by

ERROUT#ꢀWhen the pin goes low, an error has been detectedꢀ

It stays low until the next unlock sequenceꢀ The signal is

invoked for any of the following errors: incorrect start bit,

incorrect data encoding, incorrect length of data word, and

incorrect stop bitꢀ

Output Divisor

Divisor

000

001

010

011

100

101

110

111

Programming the ICS9161A

128

The ICS9161A has a wide operating range, but it is

recommended that it is operated within the following limits:

3ꢀ15V< V_DD<5ꢀ25V

V_DDsupply voltage

Unlike the ICD2061A, the ICS9161As VCO does not

require tuning to place it in certain rangesꢀ The ICS9161As

VCO will operate from 50 MHz to 120 MHz without adjusting

the VCO gainꢀ However, to maintain compatibility, the I bits

are programmed as in the ICD2061Aꢀ

1 MHz <F_REF<60 MHz

200 kHz <F_REF/M<5 MHz

50 MHz < F_VCO<120 MHz

F_CLK£ 120 MHz

F_REF=Input Reference

Frequency

M=Reference divide 3

to 129

F_VCO=VCO output

frequency

F_CLK=output frequency

These bits are dummy bits except for the following two cases:

Index Field (I)

The frequency of the programmable oscillator FVCO is

determined by the following fields:

VCLK F_VCO

MCLK F_VCO

Field

# of Bits

1110

1111

Turn off VCLK

Mux MCLK to VLCK

50 - 120 MHz

Index (I)

N counter value (N')

Mux (R)

M counter value (M')

When the index field is set to 1111, VCLK is turned off and

both channels run from the same MCLK VCOꢀ This is done in

an effort to reduce jitter, which may increase when VCOs run

at 2ⁿmultiples of one anotherꢀ If the two outputs have to be

multiples of one another, it is best to mux MCLK over to the

output of the VCLK VCO and to power-down the VCLK VCOꢀ

The multiplexed frequency will be divided down by the correct

divisor (M) and output on VCLKꢀ

Where the least significant bit is the last bit of M and the most

significant bit is the first bit of Iꢀ

ICS9161A

Power Management Issues

Power-down mode 2

When there is no need for any output during power-down, an

alternate mode is available which will completely shut down

all outputs and the reference oscillator, but still preserves all

programming the power-down bit in the CNTL register and

then pulling the PD# pin lowꢀ

Power-down mode 1

The ICS9161A contains a mechanism to reduce the quiescent

power when stand-by operation is desiredꢀ Power-down mode

1 is invoked by polling PD# low and having the proper CNTL

VCLK output is forced high, and the MCLK output is set to a

user-defined low frequency value to refresh dynamic RAMꢀ

The PD# pin

The PD# pin has a standard internal pull-up resistor during

normal operationꢀ When the chip goes into power-down

mode 1 or 2, the normal pull-up resistor is dynamically

switched to a weak pull-up, which reduces power consumptionꢀ

If the PD# pin is allowed to float after it has been pulled

down, the weak pull-up will bring the signal high and allow the

device to resume operationꢀ

The power-down MCLK value is determined by the following

equation:

MCLK_PD= F_REF/(PWRDWN register divisor value)

The power-down register divisor is determined according to

the 4-bit word programmed into the PWRDWN register (see

table below)ꢀ

Power-DownRegisterTable

PWRDWN bits

PWRDWN

Power-down

Divisor

MCLKPD

(f_REF=14.31818)

n/a

447.4 kHz

477.3 kHz

511.4 kHz

550.7 kHz

596.6 kHz

650.8 kHz

715.9 kHz

795.5 kHz

894.9 kHz

1.02 MHz

1.19 MHz

1.43 MHz

1.79 MHz

2.39 MHz

3.58 MHz

8 (default)

ICS9161A

Absolute Maximum Ratings

VDD referenced to GNDꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 7V

Operating temperature under bias (T_OPER)ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 0°C to 70°C

Storage temperature ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ -40°C to +150°C

Maxꢀ soldering temperature (10 sec) (T_SOL) ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ +260°C

Voltage on I/O pins referenced to GNDꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ GND -0ꢀ5V to VDD +0ꢀ5V

Junction temperature (T_j) ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ +125°C

Power dissipationꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 0ꢀ35 Watts

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the deviceꢀ This

is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operational sections of the specifications is not impliedꢀ Exposure to absolute maximum rating

conditions for extended periods may affect product reliabilityꢀ

Electrical Characteristics at 5$0V

V_DD= +5V ± 5%, 0°C £ T_AMBIENT£ +70°C

DC Characteristics

PARAMETER

High level input voltage

SYMBOL

V_IH

TEST CONDITIONS

MIN

2.0

TYP

MAX

UNITS

Low level input voltage

V_IL

0.8

High level CMOS output voltage¹

Low level output voltage¹

V_OH

I_OH=-4mA

I_OL=4mA

3.84

V_OL

0.4

V_DD=V =5.25V for pull-

downs ^IH

Input high current

I_IH

100

µA

Input low current

I_IL

I_OZ

V_IL=0V for pull-ups

(tristate)

-250

µA

Output leakage current

Power supply current

Power supply current (typical)

Analog power supply current

Power-down current (Mode 1)

Power-down current (Mode 2)

Input capacitance¹

-10

I_DD

µA

I_DD-TYP

I_ADD

I_PD1

I_PD2

C_IN

@60 MHz

7.5

Note

1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

ICS9161A

Electrical Characteristics at 5$0V (continued)

AC Characteristics

DESCRIPTION

Reference oscillator value²

1/f_REF

NAME

Reference

frequency

SYMBOL

MIN

TYP

14.31818

69.8408

MAX

UNITS

f_REF

t_REF

t₁

MHz

Reference period

16.6

25%

1000

75%

Duty cycle for the input oscillator

defined as t₁/t_REF

Input duty cycle

Output clock

periods

8.33 (120

MHz)

2564 (390

kHz)

Output oscillator values

t₂

t₃

t₄

Duty cycle for the output oscillators³

Output duty cycle

Rise times

45%

55%

Rise time for the output oscillators into a

25pF load

Fall time for the output oscillators into a

25pF load

Fall times

t₅

Old frequency output

New frequency output

freq1 output

freq2 output

t_freq1

t_freq2

Time clock output remains high while

output muxes to reference frequency

_REFmux time

t_A

t_time-out

t_B

0.5 t_REF

1.5t_REF

Interval for serial programming and for

VCO changes to settle⁴

Time-out interval

t_freq2muxtime

Time clock output remains high while

output muxes to new frequency value

0.5 t_REF

1.5 t_REF

Time for the output oscillators to go into

tristate mode after OUTDIS-signal

assertion

Tristate

t₆

Time for the output oscillators to recover

from tristate mode after OUTDIS-signal CLK valid

goes high

t₇

Time for power-down mode of operation

Power-down

t₈

t₉

to take effect

Time for recovery from power-down

Power-up

mode to a valid CLK

Time for MCLK to go high after

PWRDWN is asserted high

MCLKOUT high

MCLKOUT delay

t₁₀

t₁₁

t_PWRDWN

1.5 t_MCLK

Delay of MCLK prior to f_MCLKsignal at

output

0.5 t_MCLK

Clock period of serial clock

Set-up time

t_serclk

t_SU

2 • t_REF

Hold time

t_HD

Load command

t_ldcmd

t₁+30

Notes:

1ꢀ Parameter guaranteed by design and characterizationꢀ Not 100% tested in productionꢀ

2ꢀ For reference frequencies other than 14ꢀ81818 MHz, the pre-loaded ROM frequencies will shift proportionallyꢀ

3ꢀ Duty cycle is measured at CMOS threshold levelsꢀ At 5 volts, V_TH=2ꢀ5 voltsꢀ

4ꢀ If the interval is too short, see the time-out interval section in the control register definitionꢀ

ICS9161A

Rise and Fall Times

Tristated Timing

ICS9161A

Selection Timing

MCLK and Active VCLK Register Programming Timing

ICS9161A

Soft Power-Down Timing (Mode 2)

Serial Programming Timing

ICS9161A

General Layout Precautions:

1) Use a ground plane on the top layer

of the PCB in all areas not used by

traces.

2) Make all power traces and vias as

wide as possible to lower inductance.

Notes:

1) All clock outputs should have series

terminating resistor. Not shown in

all places to improve readibility of

diagram.

2) 47 ohm / 56pf RC termination

should be used on all over 50MHz

outputs.

3) Optional crystal load capacitors are

recommended.

CapacitorValues:

C1, C2 : Crystal load values determined by user

C3 : 100pF ceramic

All unmarked capacitors are 0.01µF ceramic

ConnectionstoVDD:

ICS9161A

16-Pin PDIP Package

OrderingInformation

ICS9161A-01CN16

Example:

ICS XXXX- PPP M X#W

LeadCount&PackageWidth

Lead Count=1, 2 or 3 digits

W=!3 SOIC or !6 DIP; None=Standard Width

PackageType

N=DIP (Plastic)

PatternNumber(2or3digitnumberforpartswithROMcodepatterns, ifapplicable)

Device Type (consists of 3 or4 digit numbers)

Prefix

ICS, AV=Standard Device

ICS9161A

LEAD COUNT

DIMENSION L

16L

0.404

SOIC Package (wide body)

Ordering Information

ICS9161A-01CW16

Example:

ICS XXXX- PPP M X#W

LeadCount&PackageWidth

Lead Count=1, 2 or 3 digits

W=!3 SOIC or !6 DIP; None=Standard Width

PackageType

W=SOIC

PatternNumber(2or3digitnumberforpartswithROMcodepatterns, ifapplicable)

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

ICS reserves the right to make changes in the device data identified in this publication

without further notice. ICS advises its customers to obtain the latest version of all

device data to verify that any information being relied upon by the customer is current

and accurate.

ICS9161A-01CW16WLF [IDT]

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