ICS9169CM-232LF [IDT]
Processor Specific Clock Generator, 83.3MHz, PDSO28, SOIC-28;
| 型号： | ICS9169CM-232LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 83.3MHz, PDSO28, SOIC-28 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总8页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9169C-232
Frequency Generator for Pentium™ Based Systems
General Description
Features
•
•
•
Strong output drive.
The ICS9169C-232 is a low-cost frequency generator
designed specifically for Pentium and Pentium-Pro based
chip set systems. The integrated buffer minimizes skew
and provides all the clocks required. A 14.318 MHz XTAL
oscillator provides the reference clock to generate standard
Pentium frequencies. The CPU clock makes gradual
frequency transitions without violating the PLL timing of
internal microprocessor clock multipliers. A raised
frequency setting of 68.5 MHz is available for Turbo-mode
of the 66.8 MHz CPU. The ICS9169C-232 contains 8 CPU
clocks, 6 PCI clocks, 1 REF at 48MHz and 1 at 24MHz.
Eight selectable CPU clocks operate up to 83.3 MHz
Frequency selections include Turbo-mode speed of 68.5
MHz
•
•
•
Maximum CPU jitter of ±200ps
Six BUS clocks support sync or async bus operation
250ps skew window for CPU outputs, 500ps skew window for
BUS outputs
CPU clocks to BUS clocks skew 1-4 ns (CPU early)
48 MHz clock for USB support & 24 MHz clock for FD.
Logic inputs latched at Power-On for frequency selection
saving pins as Input/Output
Integrated buffer outputs drive up to 30pF loads
3.0V - 3.7V supply range, CPU (1:6) outputs 2.5V
(2.375 - 2.6V) VDD option
•
•
•
Either synchronous (CPU/2) or asynchronous (32 MHz)
PCI bus operation can be selected by latching data on
BSEL input.
•
•
•
28-pin SOIC or SSOP package
Block Diagram
Pin Configuration
28-Pin SOIC or SSOP
Functionality
3.3V±10%, 0-70°C
Crystal (X1, X2) = 14.31818 MHz
ADDRESS
SELECT
CPU(1:8)
(MHz)
BUS (1:6)MHz
48MHz 24MHz REF
FS2 FS1 FS0
BSEL=1 BSEL=0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
60
25
30
32
32
32
32
32
32
32
32
48
48
48
48
48
48
48
48
24
24
24
24
24
24
24
24
REF
REF
REF
REF
REF
REF
REF
REF
VDD Groups:
Latched Inputs:
L1 = BSEL
L2 = FS0
VDD1 = X1, X2, REF/BSEL
VDD2 = CPU1-6
66.8
75.9
55
33.4
32
VDD3 = CPU7-8 & PLL Core
VDD4 = BUS1-6
VDD5 = 48/24 MHz
L3 = FS1
27.5
37.5
41.7
34.25
L4 = FS2
75.9
83.3
68.5
Pentium is a trademark of Intel Corporation.
9169C-232RevB031897
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS169C-232
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
Power for control logic and crystal oscillator circuit and
14.318 MHz output
1
VDD1
X1
PWR
XTAL or external reference frequency input. This input includes XTAL
load capacitance and feedback bias for a 12-16MHz crystal, nominally
14.31818MHz. External crystal load of 30pF to GND recommended for
VDD power on faster than 2.0ms.
2
IN
XTAL output which includes XTAL load capacitance. External crystal
load of 10pF to GND recommended for VDD power on faster than 2.0ms.
3
X2
OUT
PWR
OUT
4,11,16,22
6,7,9,10,15
GND
Ground for control logic.
Processor clock outputs which are a multiple of the input reference clock
as shown in the preceding table.
CPU(2,3,4,5,8)
CPU1, CPU6,
CPU7
Processor clock outputs which are a multiple of the input reference clock
as shown in the preceding table.
5,12,13
OUT
IN
Frequency multiplier select pins. See shared pin programming description
later in this data sheet for further explanation. 350K* internal pull up.
5,12,13
FS (0:2)
VDD2
Power for CPU (1:6) clock buffers only. This VDD supply can be reduced
to 2.5V for CPU (1:6) outputs.
8
14
PWR
PWR
OUT
Power for CPU (7:8) clock buffers and internal PLL and Core logic. Must
be nominal 3.3V (3.0 to 3.7V)
VDD3
BUS clock outputs which are a multiple of the input reference clock as
shown in the preceding table.
17,18,20,21,23, 24
BUS(1:6)
19
25
26
27
VDD4
PWR
PWR
OUT
OUT
Power for BUS clock buffers BUS (1;6)
VDD5
Power for fixed clock buffer (48 MHz, 24 MHz)
24 MHz
48 MHz
Fixed 24 MHz clock (assuming a 14.31818 MHz REF frequency).
Fixed 48 MHz clock (assuming a 14.31818 MHz REF frequency).
REF
OUT
Fixed 14.31818 MHz clock (assuming a 14.31818 MHz REF frequency).
28
Selection for synchronous or asynchronous bus clock operation. 350K*
internal pull up.
BSEL
IN
* The internal pull up will vary from 350K to 500K based on temperature
2
ICS169C-232
Shared Pin Operation -
Input/Output Pins
Test Mode Operation
The ICS9169C-232 includes a production test verification
mode of operation. This requires that the FS0 and FS1 pins
be programmed to a logic high and the FS2 pin be
programmed to a logic low(see Shared Pin Operation
section). In this mode the device will output the following
frequencies.
Shared Pin Operation - Input/Output, Pins 5, 28, 12 and
13 on the ICS9169C-232 serve as dual signal functions to
the device. During initial power-up, they act as input pins.
The logic level (voltage) that is present on these pins at
this time is read and stored into a 4-bit internal data latch.
At the end of Power-On reset, (see AC characteristics for
timing values), the device changes the mode of operations
for these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
Pin
Frequency
REF
REF/2
REF/4
REF2
REF/4
REF/3
REF
48MHz
24MHz
CPU (1:8)
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic
1) power supply or the GND (logic 0) voltage potential. A
10 Kilohm(10K) resistor is used to provide both the solid
CMOS programming voltage needed during the power-up
programming period and to provide an insignificant load
on the output clock during the subsequent operating
period.
BSEL=1
BESEL = 0
BUS (1:6)
Note: REF is the frequency of either the crystal connected
between the devices X1and X2 or, in the case of a device
being driven by an external reference clock, the frequency
of the reference (or test) clock on the device’s X1 pin.
Figs. 1 and 2 show the recommended means of
implementing this function. In Fig. 1 either one of the
resistors is loaded onto the board (selective stuffing) to
configure the device’s internal logic. Figs. 2a and b provide
a single resistor loading option where either solder spot
tabs or a physical jumper header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance
clock signals. The layouts have been optimized to provide
as little impedance transition to the clock signal as possible,
as it passes through the programming resistor pad(s).
Fig. 1
3
ICS169C-232
Fig. 2b
Fig. 2a
Fig. 3
4
ICS169C-232
Technical Pin Function Descriptions
VDD1
BUS (1:6)
This is the power supply to the internal logic of the device
as well as the following clock output buffers:
This pin is the clock output that is intended to drive the
systems plug-in card bus. The voltage swing of these
clocks is controlled by the supply that is applied to the
VDD pin of the device. See the Functionality table at the
beginning of this data sheet for a list of the specific
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies.
A. REF clock output buffers
B. BUS clock output buffers
C. Fixed clock output buffers
This pin may be operated at any voltage between 3.0 and
5.5 volts. Clocks from the listed buffers that it supplies
will have a voltage swing from ground to this level. For the
actual guaranteed high and low voltage levels of these
clocks, please consult the AC parameter table in this data
sheet.
FS0, FS1, FS2
These pins control the frequency of the clocks at the CPU,
CPUL, BUS, SDRAM, AGP and IOAPIC pins. See the Fun-
tionality table at the beginning of this data sheet for a list
of the specific frequencies that this clock operates at and
the selection codes that are necessary to produce these
frequencies. The device reads these pins at power-up and
stores the programmed selection code in an internal data
latch. (See programming section of this data sheet for
configuration circuitry recommendations.
GND
This is the power supply ground return pin for the internal
logic of the device as well as the following clock output
buffers:
A. REF clock output buffers
B. BUS clock output buffers
C. CPU clock output buffers
BSEL
When this pin is a logic 1, it will place the CPU clocks in
the synchronous mode (running at half the frequency of
the Ref). If this pin is a logic 0, it will be in the asynchronous
mode for the CPU clocks and will operate at the
preprogrammed fixed frequency rate. It is a shared pin
and is programed the same way as the Frequency Select
pins.
X1
This pin serves one of two functions. When the device is
used with a crystal, X1 acts as the input pin for the
reference signal that comes from the discrete crystal.
When the device is driven by an external clock signal, X1
is the device’ input pin for that reference clock. This pin
also implements an internal crystal loading capacitor that
is connected to ground. See the data tables for the value of
the capacitor.
VDD 2, 3
These are the power supply pins for the CPU clock buffers.
By separating the clock power pins, each group can receive
the appropriate power decoupling and bypassing necessary
tominimizeEMIandcrosstalkbetweentheindividualsignals.
VDD2 can be reduced to 2.5V VDD for advanced processor
clocks, which will bring CPU (1:6) outputs at 0 to 2.5V output
swings.
X2
This pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2
is an output signal that drives (or excites) the discrete
crystal. This pin also implements an internal crystal loading
capacitor that is connected to ground. See the data tables
for the value of the capacitor.
48 MHz
This is a fixed frequency clock that is typically used to
drive Super I/O peripheral device needs.
CPU (1:8)
24 MHz
This pin is the clock output that drives processor and other
CPU related circuitry that require clocks which are in tight
skew tolerance with the CPU clock. The voltage swing of
these clocks is controlled by that which is applied to the
VDD pin of the device. See the Functionality table at the
beginning of this data sheet for a list of the specific
frequencies this clock operates at and the selection codes
that are necessary to produce these frequencies.
This is a fixed frequency clock that is typically used to
drive Keyboard controller clock needs.
VDD4
This power pin supplies the BUS clock buffers.
REF
This is a fixed frequency clock that runs at the same
frequency as the input reference clock (typically 14.31818
MHz) is and typically used to drive Video and ISA BUS
requirements.
VDD5
This power pin supplies the 48/24 MHz clocks.
5
ICS169C-232
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7V, TA = 0 –70°C unless otherwise stated
DC Characteristics
PARAMETER
SYMBOL TEST CONDITIONS
MIN
-
TYP
-
MAX
UNITS
V
IL
V
DD
0.2V
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Current1
Output High Current1
Output Low Current1
Output High Current1
Output Low Voltage1
Output High Voltage1
Output Low Voltage1
Output High Voltage1
Supply Current
IH
DD
V
0.7V
-28.0
-5.0
19.0
-
-
-
-
V
IL
IN
= 0V
I
V
-10.5
-
µA
µA
mA
mA
mA
mA
V
IH
IN
V
DD
= V
I
5.0
-
OL
OL
I
V
= 0.8V; for CPU, BUS, REF CLKs
= 2.0V; for CPU, BUS, REF CLKs
= 0.8V; for fixed CLKs
OL
= 2.0V; for fixed CLKs
30.0
-38.0
25.0
-30.0
0.3
2.8
0.3
2.8
70
OH
OL
OL
V
I
-16.0
-
OL
V
I
16.0
-
OH
I
V
-14.0
0.4
-
OL
OL
V
I
I
= 10mA; for CPU, BUS, REF CLKs
OH
= -15mA; for CPU, BUS, REF CLKs
-
OH
V
2.4
-
V
OL
V
IOL = 8mA; for fixed CLKs
0.4
-
V
OH
OH
V
I
= -8mA; for fixed CLKs
2.4
-
V
DD
I
@66.6 MHz; all outputs unloaded
140
mA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
6
ICS169C-232
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7 V, TA = 0 – 70°C unless otherwise stated
AC Characteristics
PARAMETER
Rise Time1
SYMBOL TEST CONDITIONS
MIN
TYP
0.9
0.8
1.5
1.4
50
MAX
1.5
UNITS
ns
20pF load, 0.8 to 2.0V
CPU & BUS
20pF load, 2.0 to 0.8V
CPU & BUS
20pF load, 20% to 80%
CPU & BUS
20pF load, 80% to 20%
CPU & BUS
Tr1
Tf1
Tr2
Tf2
Dt
-
-
Fall Time1
1.4
ns
Rise Time1
-
2.5
ns
Fall Time1
-
2.4
ns
Duty Cycle1
Jitter, One Sigma1
20pF load @ VOUT=1.4V
45
-
60
%
CPU & BUS Clocks; Load=20pF,
BSEL=1
Tj1s1
50
150
ps
CPU & BUS Clocks; Load=20pF,
BSEL=1
Jitter, Absolute1
Tjab1
Tj1s2
Tjab2
Fi
-250
-
250
ps
%
Jitter, One Sigma1
Jitter, Absolute1
REF & Fixed CLKs; Load=20pF
-
1
2
3
5
REF & Fixed CLKs; Load=20pF
-5
%
Input Frequency1
12.0
14.318
5
16.0
-
MHz
pF
Logic Input Capacitance1
Crystal Oscillator Capacitance1
Power-on Time1
CIN
CINX
ton
Logic input pins
X1, X2 pins
-
-
-
18
-
pF
From VDD=1.6V to 1st crossing of
66.6 MHz VDD supply ramp < 40ms
From 1st crossing of acquisition to <
1% settling
2.5
4.5
ms
Frequency Settling Time1
Clock Skew1
ts
-
-
2.0
150
160
2.6
4.0
250
500
4
ms
ps
ps
ns
Tsk1
Tsk2
Tsk3
CPU to CPU; Load=20pF; @1.4V
BUS & BUS; Load=20pF; @1.4V
Clock Skew1
-
CPU to BUS; Load=20pF; @1.4V
(CPU is early)
Clock Skew1
1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
7
ICS169C-232
SSOP Package
SOIC Package
COMMON
D
SSOP
DIMENSIONS
SSOP
SYMBOL
VARIATIONS
MIN.
0.068
0.002
NOM.
MAX.
0.078
MIN.
NOM.
0.244
MAX.
0.249
A
A1
A2
B
C
D
E
0.073
0.005
0.068
0.012
0.006
14
16
20
24
28
30
0.239
0.239
0.278
0.318
0.397
0.397
0.008
0.070
0.015
0.008
0.244
0.284
0.323
0.402
0.402
0.249
0.289
0.328
0.407
0.407
0.066
0.010
0.004
See Variations
0.209
0.205
0.212
e
H
L
0.0256 BSC
0.307
0.301
0.025
0.311
0.037
0.030
N
See Variations
4°
0°
8°
Ordering Information
ICS9169CF-232
SOIC Package (wide body)
e = 0.05 BSC
ICS9169CM-232
LEAD COUNT
DIMENSION L
14L
16L
18L
20L
0.504
24L
28L
0.704
32L
Example:
0.354
0.404
0.454
0.604
0.804
ICS XXXX F- PPP
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
8
相关型号：
ICS9169CM-23LF
Processor Specific Clock Generator, 83.3MHz, PDSO28, 0.300 INCH, ROHS COMPLIANT, MS-013, MO-119, SOIC-28
IDT
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