ICS9179BF-03 [IDT]
Low Skew Clock Driver, 9179 Series, 18 True Output(s), 0 Inverted Output(s), PDSO48, SSOP-48;
| 型号： | ICS9179BF-03 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 9179 Series, 18 True Output(s), 0 Inverted Output(s), PDSO48, SSOP-48 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总11页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9179-03
Low Skew Fan Out Buffers
General Description
Features
•
Ten High speed, low noise non-inverting buffers for (to
133MHz), clockbufferapplications.
Output slew rate faster than 1.5V/ns into 20pF
Supports up to four small outline DIMMS (S.O. DIMM).
The ICS9179-03 generates low skew clock buffers required
for high speed RISC or CISC microprocessor systems such as
Intel PentiumPro. Outputs will handle up to 133MHz clocks.
An output enable is provided for testability.
•
•
•
Synchronous clocks skew matched to 250ps window on
OUTPUTs(0:9).
The device is a buffer with low output to output skew. This is
a Fanout buffer device, not using an internal PLL. This buffer
can also be a feedback to an external PLL stage for phase
synchronization to a master clock. There are a total of ten
outputs, sufficient for feedback to a PLL source and to drive
four small outline DIMM modules (S.O. DIMM) at 2 clocks
each. Or a total of ten outputs as a Fanout buffer from a
common clock source.
•
I2C Serial Configuration interface to allow individual
OUTPUTs to be stopped low.
•
•
•
•
Multiple VDD, VSS pins for noise reduction
Tri-state pin for testing
3.0V – 3.7V supply range
28-pin(209mil)SSOPand(6.1mm)TSSOPpackage
The individual clock outputs are addressable through I2C to
be enabled, or stopped in a low state for reduced EMI when
the lines are not needed.
Block Diagram
Pin Configuration
28-Pin SSOP & TSSOP
0258K 12/15/08
PentiumPro is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9179-03
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE DESCRIPTION
2, 3
OUTPUT (0:1)
OUT
OUT
Clock outputs1, uses VDD0, GND0
Clock outputs1, uses VDD1, GND1
6, 7
OUTPUT (2:3)
22, 23
26, 27
11
OUTPUT (4:5)
OUTPUT (6:7)
OUTPUT8
OUT
OUT
OUT
OUT
IN
Clock outputs1 uses VDD2, GND2
Clock output1 uses VDD3, GND3
Clock output1 uses VDD4, GND4
Clock output1 uses VDD5, GND5
Input for buffers
18
OUTPUT9
9
BUF_IN
20
14
OE
IN
Tri-states all outputs when held LOW. Has internal pull-up.2
Data pin for I2C circuitry3
Clock pin for I2C circuitry3
SDATA
SCLK
I/O
I/O
15
1, 5, 10,
19, 24, 28
4, 8, 12,
VDD (0:5)
GND (0:5)
PWR
PWR
3.3V Power supply for OUTPUT buffers
Ground for OUTPUT buffers
16, 17, 21, 25
13
16
VDDI
GNDI
PWR
PWR
3.3V Power supply for I2C circuitry and internal logic
Ground for I2C circuitry and internal logic
Notes:
1.
2.
3.
At power up all ten OUTPUTs are enabled and active.
OE has a 100K Ohm internal pull-up resistor to keep all outputs active.
The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for
completeplatformflexibility.
Power Groups
VDD(0:5), GND(0:5) =PowersupplyforOUTPUTbuffer
VDDI, GNDI=PowersupplyforI2Ccircuitry
0258K 12/15/08
2
ICS9179-03
Technical Pin Function Descriptions
VDD
This is the power supply to the internal core logic of the
device as well as the clock output buffers for OUTPUT (0:9).
This pin operates at 3.3V volts. Clocks from the listed buffers
that it supplies will have a voltage swing from Ground to this
level. For the actual guaranteed high and low voltage levels
for the Clocks, please consult the DC parameter table in this
data sheet.
GND
This is the power supply ground (common or negative) return
pin for the internal core logic and all the output buffers.
OUTPUT(0:9)
These Output Clocks are use to drive Dynamic RAM’s and
are low skew copies of the CPU Clocks. The voltage swing of
the OUTPUTs output is controlled by the supply voltage
that is applied to VDD of the device, operates at 3.3 volts.
I2C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in the
I2C protocol. It will allow read-back of the registers. See
configurationmapforregisterfunctions. TheI2Cspecification
in Philips I2C Peripherals Data Handbook (1996) should be
followed.
BUF_IN
Input for Fanout buffers (OUTPUT 0:9).
OE
OE tristates all outputs when held low.
VDD1
This is the power supply to I2C circuitry.
0258K 12/15/08
3
ICS9179-03
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controler (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Address
Controller (Host)
ICS (Slave/Receiver)
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Dummy Byte Count
Byte 0
Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
0258K 12/15/08
4
ICS9179-03
Serial Configuration Command Bitmaps
Byte0:OUTPUTClockRegister(Default=0)
BIT
Bit7
Bit6
Bit5
Bit4
PIN#
PWD
DESCRIPTION
Reserved
-
-
-
1
1
1
Reserved
Reserved
Reserved
OUTPUT3
OUTPUT2
OUTPUT1
OUTPUT0
-
1
1
1
7
6
Bit3
Bit2
Bit1
Bit0
3
2
1
1
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD=Power-UpDefault
Byte 2: OUTPUT Clock Register
Byte 1: OUTPUT Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
OUTPUT9 (Act/Inact)
OUTPUT8 (Act/Inact)
Reserved
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
OUTPUT7 (Act/Inact)
OUTPUT6 (Act/Inact)
OUTPUT5 (Act/Inact)
OUTPUT4 (Act/Inact)
Reserved
18
11
-
1
1
1
1
1
1
1
1
27
26
23
22
-
1
1
1
1
1
1
1
1
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD=Power-UpDefault
Notes: 1 = Enabled; 0 = Disabled, outputs held low
ICS9179-03 Power Management
The values below are estimates of target specifications.
Max 3.3V supply consumption
Max discrete cap loads
VDD = 3.465V
Condition
All static inputs = VDD or GND
No Clock Mode
(BUF_IN - VDD1 or GND)
I2C Circuitry Active
3mA
Functionality
Active 66MHz
(BUF_IN = 66.66MHz)
230mA
360mA
460mA
OE#
OUTPUT (0:9)
Active 100MHz
(BUF_IN = 100.00MHz)
0
1
Hi-Z
Active 133MHz
(BUF_IN = 133.33MHz)
1 X BUF_IN
0258K 12/15/08
5
ICS9179-03
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
IIH
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
uA
uA
uA
mA
mA
mA
mA
mA
mA
MHz
pF
IIL
-5
IIL
VIN = 0 V; Inputs with 100K pull-up resistors -60
CL = 0 pF; FIN @ 66M
-33
80
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
Fi1
120
180
240
260
360
460
133
5
Operating
CL = 0 pF; FIN @ 100M
120
170
180
240
350
CL = 0 pF; FIN @ 133M
Supply Current
C = 30 pF; RS=33 ; F @ 66M
Ω
L IN
C = 30 pF; RS=33 ; F @ 100M
Ω
L
IN
C = 30 pF; RS=33 ; F @ 133M
Ω
L
IN
Input frequency
VDD = 3.3 V; All Outputs Loaded
10
1
CIN
Input Capacitance
Logic Inputs
1Guarenteed by design, not 100% tested in production.
0258K 12/15/08
6
ICS9179-03
Electrical Characteristics - Outputs
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
RDSP
RDSN
VOH
VOL
IOH
CONDITIONS
MIN
10
TYP
MAX UNITS
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -30 mA
IOL = 23 mA
VOH = 2.0 V
24
24
Ω
Ω
10
2.3
3
V
0.27
-115
57
0.4
-54
V
mA
mA
ns
ns
%
IOL
VOL = 0.8 V
40
0.5
0.5
45
Tr
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.95
0.95
50
1.33
1.33
55
250
5.5
5.5
5
Fall Time1
Duty Cycle1
Tf
Dt
Skew1
Tsk
VT = 1.5 V
110
5.2
ps
ns
ns
ns
ns
ns
ns
TPHL1
TPLH1
VT = 1.5 V
1
1
1
1
1
1
VT = 1.5 V
5.2
Propagation1,2
TPHL2
TPLH2
TEN
50% Buffer In to 90% Out
50% Buffer In to 10% Out
VT = 1.5 V
4.3
4.3
5
8
TDIS
VT = 1.5 V
8
Note1: Paramater is guaranteed by design and characterization for all operating frequencies, (10MHz - 133MHz).
Not 100% tested in production
1V/ns
Note2: Duty cycle of input clock is 47.5% to 52.5%. Input edge rate is for propagation delay
≥
0258K 12/15/08
7
ICS9179-03
GeneralLayoutPrecautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
CapacitorValues:
All unmarked capacitors are 0.01µF ceramic
0258K 12/15/08
8
ICS9179-03
209 mil SSOP
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
1.65
0.22
0.09
MAX
2.00
--
1.85
0.38
0.25
MIN
--
.002
.065
.009
.0035
MAX
.079
--
.073
.015
.010
A
A1
A2
b
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
7.40
5.00
8.20
5.60
.291
.197
.323
.220
0.65 BASIC
0.0256 BASIC
L
0.55
0.95
.022
.037
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
VARIATIONS
D mm.
D (inch)
N
MIN
9.90
MAX
10.50
MIN
.390
MAX
.413
28
Reference Doc.: JEDEC Publication 95, MO-150
10-0033
209 mil SSOP
Ordering Information
9179yF-03LF-T
Example:
XXXX y F - PPPLF - T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
0258K 12/15/08
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
9
ICS9179-03
6.10 mm. Body, 0.65 mm. Pitch TSSOP
(240 mil) (25.6 mil)
In Millimeters
COMMON DIMENSIONS
c
N
In Inches
COMMON DIMENSIONS
SYMBOL
MIN
--
0.05
0.80
0.19
0.09
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.012
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
2
E1
e
L
6.00
0.65 BASIC
0.45
6.20
.236
0.0256 BASIC
.018 .030
SEE VARIATIONS
.244
α
0.75
D
N
SEE VARIATIONS
α
0°
--
8°
0.10
0°
--
8°
.004
aaa
A
A2
VARIATIONS
D mm.
D (inch)
N
A1
MIN
9.60
MAX
9.80
MIN
.378
MAX
.386
- C -
28
e
SEATING
PLANE
Reference Doc.: JEDEC Publication 95, MO-153
10-0038
b
aaa
C
Ordering Information
9179yG-03LF-T
Example:
XXXX y G - PPPLF - T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
0258K 12/15/08
10
ICS9179-03
Revision History
Rev.
J
Issue Date Description
Page #
9, 10
8/29/2005 Added LF Ordering Information.
K
12/15/2008 Removed ICS prefix from ordering information
9, 10
0258K 12/15/08
11
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