ICS9179F-03-T [IDT]
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO28, 0.209 INCH, SSOP-28;
| 型号： | ICS9179F-03-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO28, 0.209 INCH, SSOP-28 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Incꢀ
ICS9179-03
Low Skew Fan Out Buffers
General Description
Features
Ten High speed, low noise non-inverting buffers for (to
The ICS9179-03 generates low skew clock buffers required
for high speed RISC or CISC microprocessor systems such as
Intel PentiumProꢀ Outputs will handle up to 133MHz clocksꢀ
An output enable is provided for testabilityꢀ
133MHz), clock buffer applicationsꢀ
Output slew rate faster than 1ꢀ5V/ns into 20pF
Supports up to four small outline DIMMS (SꢀOꢀ DIMM)ꢀ
Synchronous clocks skew matched to 250ps window on
OUTPUTs(0:9)ꢀ
The device is a buffer with low output to output skewꢀ This is
a Fanout buffer device, not using an internal PLLꢀ This buffer
can also be a feedback to an external PLL stage for phase
synchronization to a master clockꢀ There are a total of ten
outputs, sufficient for feedback to a PLL source and to drive
four small outline DIMM modules (SꢀOꢀ DIMM) at 2 clocks
eachꢀ Or a total of ten outputs as a Fanout buffer from a
common clock sourceꢀ
I2C Serial Configuration interface to allow individual
OUTPUTs to be stopped lowꢀ
Multiple VDD, VSS pins for noise reduction
Tri-state pin for testing
3ꢀ0V 3ꢀ7V supply range
28-pin(209mil)SSOPand(6ꢀ1mm)TSSOPpackage
The individual clock outputs are addressable through I2C to
be enabled, or stopped in a low state for reduced EMI when
the lines are not neededꢀ
Block Diagram
Pin Configuration
28-Pin SSOP & TSSOP
PentiumPro is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9179-03 Rev H 10/16/00
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9179-03
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE DESCRIPTION
2, 3
OUTPUT (0:1)
OUTPUT (2:3)
OUT
OUT
Clock outputs1, uses VDD0, GND0
Clock outputs1, uses VDD1, GND1
6, 7
22, 23
26, 27
11
OUTPUT (4:5)
OUTPUT (6:7)
OUTPUT8
OUT
OUT
OUT
OUT
IN
Clock outputs1 uses VDD2, GND2
Clock output1 uses VDD3, GND3
Clock output1 uses VDD4, GND4
Clock output1 uses VDD5, GND5
Input for buffers
18
OUTPUT9
9
BUF_IN
20
OE
IN
Tri-states all outputs when held LOW. Has internal pull-up.2
14
15
SDATA
SCLK
I/O
I/O
Data pin for I2C circuitry3
Clock pin for I2C circuitry3
1, 5, 10,
19, 24, 28
4, 8, 12,
VDD (0:5)
GND (0:5)
PWR
PWR
3.3V Power supply for OUTPUT buffers
Ground for OUTPUT buffers
16, 17, 21, 25
13
16
VDDI
GNDI
PWR
PWR
3.3V Power supply for I2C circuitry and internal logic
Ground for I2C circuitry and internal logic
Notes:
1ꢀ
2ꢀ
3ꢀ
AtpowerupalltenOUTPUTsareenabledandactiveꢀ
OE has a 100K Ohm internal pull-up resistor to keep all outputs activeꢀ
The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for
completeplatformflexibilityꢀ
Power Groups
VDD(0:5), GND(0:5) =PowersupplyforOUTPUTbuffer
VDDI, GNDI = Power supply for I2C circuitry
2
ICS9179-03
Technical Pin Function Descriptions
VDD
This is the power supply to the internal core logic of the
device as well as the clock output buffers for OUTPUT (0:9)ꢀ
This pin operates at 3ꢀ3V voltsꢀ Clocks from the listed buffers
that it supplies will have a voltage swing from Ground to this
levelꢀ For the actual guaranteed high and low voltage levels
for the Clocks, please consult the DC parameter table in this
data sheetꢀ
GND
This is the power supply ground (common or negative) return
pin for the internal core logic and all the output buffersꢀ
OUTPUT(0:9)
These Output Clocks are use to drive Dynamic RAMs and
are low skew copies of the CPU Clocksꢀ The voltage swing of
the OUTPUTs output is controlled by the supply voltage
that is applied to VDD of the device, operates at 3ꢀ3 voltsꢀ
I2C
The SDATA and SCLOCK Inputs are use to program the
deviceꢀ The clock generator is a slave-receiver device in the
I2C protocolꢀ It will allow read-back of the registersꢀ See
configurationmapforregisterfunctionsꢀTheI2Cspecification
in Philips I2C Peripherals Data Handbook (1996) should be
followedꢀ
BUF_IN
Input for Fanout buffers (OUTPUT 0:9)ꢀ
OE
OE tristates all outputs when held lowꢀ
VDD1
This is the power supply to I2C circuitryꢀ
3
ICS9179-03
General I2C serial interface information
The information in this section assumes familiarity with I2C programmingꢀ
For more information, contact ICS for an I2C programming application noteꢀ
How to Write:
Controller (host) sends a start bitꢀ
Controller (host) sends the write address D2(H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bitꢀ
Controler (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a timeꢀ
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Address
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Dummy Byte Count
Byte 0
Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
Stop Bit
Stop Bit
Notes:
1ꢀ
TheICSclockgeneratorisaslave/receiver,I 2C componentꢀ It can read back the data stored in the latches for verificationꢀ
Read-BackwillsupportIntelPIIX4"Block-Read"protocolꢀ
2ꢀ
3ꢀ
4ꢀ
5ꢀ
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3ꢀ3V logic levelsꢀ
The data byte format is 8 bit bytesꢀ
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controllerꢀ The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferredꢀ The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytesꢀ The data is loaded until a Stop sequence is issuedꢀ
6ꢀ
At power-on, all registers are set to a default condition, as shownꢀ
4
ICS9179-03
Serial Configuration Command Bitmaps
Byte0:OUTPUTClockRegister(Default=0)
BIT
Bit7
Bit6
Bit5
Bit4
PIN#
PWD
DESCRIPTION
Reserved
-
-
-
1
1
1
Reserved
Reserved
Reserved
OUTPUT3
OUTPUT2
OUTPUT1
OUTPUT0
-
1
1
1
7
6
Bit3
Bit2
Bit1
Bit0
3
2
1
1
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Byte 2: OUTPUT Clock Register
Byte 1: OUTPUT Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
OUTPUT7 (Act/Inact)
OUTPUT6 (Act/Inact)
OUTPUT5 (Act/Inact)
OUTPUT4 (Act/Inact)
Reserved
18
11
-
1
1
1
1
1
1
1
1
OUTPUT9 (Act/Inact)
27
26
23
22
-
1
1
1
1
1
1
1
1
OUTPUT8 (Act/Inact)
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Notes: 1 = Enabled; 0 = Disabled, outputs held low
ICS9179-03 Power Management
The values below are estimates of target specificationsꢀ
Max 3.3V supply consumption
Max discrete cap loads
VDD = 3.465V
Condition
All static inputs = VDD or GND
No Clock Mode
(BUF_IN - VDD1 or GND)
I2C Circuitry Active
3mA
Functionality
Active 66MHz
(BUF_IN = 66.66MHz)
230mA
360mA
460mA
OE#
OUTPUT (0:9)
Active 100MHz
(BUF_IN = 100.00MHz)
0
1
Hi-Z
Active 133MHz
(BUF_IN = 133.33MHz)
1 X BUF_IN
5
ICS9179-03
Absolute Maximum Ratings
Supply Voltage ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 7ꢀ0V
Logic Inputs ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ GND 0ꢀ5 V to VDD +0ꢀ5 V
Ambient Operating Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 0°C to +70°C
Storage Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the deviceꢀ These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not impliedꢀ Exposure to absolute maximum rating conditions for extended periods
may affect product reliabilityꢀ
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
IIH
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
uA
IIL
-5
uA
IIL
VIN = 0 V; Inputs with 100K pull-up resistors -60
CL = 0 pF; FIN @ 66M
-33
80
uA
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
Fi1
120
180
240
260
360
460
133
5
mA
mA
mA
mA
mA
mA
MHz
pF
Operating
CL = 0 pF; FIN @ 100M
120
170
180
240
350
CL = 0 pF; FIN @ 133M
Supply Current
C = 30 pF; RS=33 ; FIN @ 66M
Ω
L
C = 30 pF; RS=33 ; FIN @ 100M
Ω
L
C = 30 pF; RS=33 ; FIN @ 133M
Ω
L
Input frequency
VDD = 3.3 V; All Outputs Loaded
10
1
CIN
Input Capacitance
1Guarenteed by design, not 100% tested in production.
Logic Inputs
6
ICS9179-03
Electrical Characteristics - Outputs
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
RDSP
RDSN
VOH
VOL
IOH
CONDITIONS
MIN
10
TYP
MAX UNITS
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -30 mA
IOL = 23 mA
VOH = 2.0 V
24
24
Ω
Ω
10
2.3
3
V
0.27
-115
57
0.4
-54
V
mA
mA
ns
ns
%
IOL
VOL = 0.8 V
40
45
Tr
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.95
0.95
50
1.33
1.33
55
250
5.5
5.5
5
Fall Time1
Duty Cycle1
Tf
Dt
Skew1
Tsk
VT = 1.5 V
110
5.2
ps
ns
ns
ns
ns
ns
ns
TPHL1
TPLH1
VT = 1.5 V
1
1
1
1
1
1
VT = 1.5 V
5.2
Propagation1,2
TPHL2
TPLH2
TEN
50% Buffer In to 90% Out
50% Buffer In to 10% Out
VT = 1.5 V
4.3
4.3
5
8
TDIS
VT = 1.5 V
8
Note1: Paramater is guaranteed by design and characterization for all operating frequencies, (10MHz - 133MHz).
Not 100% tested in production
1V/ns
Note2: Duty cycle of input clock is 47.5% to 52.5%. Input edge rate is for propagation delay
≥
7
ICS9179-03
GeneralLayoutPrecautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
tracesꢀ
2) Make all power traces and vias as
wide as possible to lower inductanceꢀ
Notes:
1 All clock outputs should have series
terminating resistorꢀ Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputsꢀ
CapacitorValues:
All unmarked capacitors are 0ꢀ01µF ceramic
8
ICS9179-03
Ordering Information
ICS9179yF-03-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
9
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9179-03
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
MIN
-
MAX
.047
.006
.041
.012
.008
A
A1
A2
b
0.05
0.80
0.19
0.09
.002
.032
.007
.0035
c
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319
D
E
E1
e
6.00
6.20
0.65 BASIC
0.75
.236
.244
0.0256 BASIC
L
0.45
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
0°
-
8°
0°
-
8°
α
aaa
0.10
.004
VARIATIONS
D mm.
D (inch)
N
MIN
9.60
MAX
9.80
MIN
.378
MAX
6ꢀ10 mmꢀ Body, 0ꢀ65 mmꢀ pitch TSSOP
(0ꢀ0256 mil)
28
.386
7/6/00 Rev B
(240 mil)
MO-153 JEDEC
Doc.# 10-0038
Ordering Information
ICS9179yG-03-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
10
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