ICS9250YF-13LF [IDT]
Processor Specific Clock Generator, 90MHz, PDSO56, 0.300 INCH, SSOP-56;
| 型号： | ICS9250YF-13LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 90MHz, PDSO56, 0.300 INCH, SSOP-56 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总15页 (文件大小：563K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9250-13
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
Features
3.3Voutputs:SDRAM, PCI, REF, 48/24MHz
2.5Vor3.3Voutputs:CPU
The ICS9250-13 generates all clocks required for high speed
RISCorCISCmicroprocessorsystemssuchasIntel PentiumPro
orCyrix. Eightdifferentreferencefrequencymultiplyingfactors
are externally selectable with smooth frequency transitions.
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
Skew from CPU (earlier) to PCI clock - 1 to 4 ns,
center 2.6 ns.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9250-13
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
No external load cap for CL=18pF crystals
±250 ps CPU, PCI clock skew
400ps (cycle to cycle) CPU jitter
Smooth frequency switch, with selections from
50to83.3MHzCPU.
I2C interface for programming
2ms power up clock stable time
Clock duty cycle 45-55%.
56pin300milSSOPpackage
3.3V operation, 5V tolerant input.
Block Diagram
Recomended Application:
440LX/EX type chipset Motherboard single chip
clock solution.
Pin Configuration
Power Groups
56-Pin SSOP
VDDREF=REF(0:1),X1,X2
VDDPCI=PCICLK_F,PCICLK(0:5)
VDDSDR=SDRAM(0:11), supplyforPLLcore,
VDD48=24MHz,48MHz
* Internal Pull-up Resistor of
120K to VDD on indicated inputs
VDDLIOAPIC=IOAPIC
VDDL2CPU= CPUCLK(0:3)
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9250-13RevA3/25/99
information being relied upon by the customer is current and accurate.
ICS9250-13
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
PWR
OUT
IN
DESCRIPTION
Ref (0:1), XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
1
VDDREF
REF0
FS31, 2
2
Frequency select pin. Latched Input
3,9,16,22,28, 29, 35,
41, 47, 53
GND
X1
PWR
IN
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
4
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
5
X2
OUT
6,14
VDDPCI
PCICLK_F
FS11, 2
PWR
OUT
IN
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock
7
Frequency select pin. Latched Input
PCI clock output.
PCICLK0
FS21, 2
OUT
IN
8
Frequency select pin. Latched Input
PCI clock outputs.
10, 11, 12, 13
PCICLK(1:4)
PCICLK5
OUT
OUT
PCI clock output. (In desktop mode, MODE=1)
15
Halts PCICLK(0:5) clocks at logic 0 level, when input low
(In mobile mode, MODE=0)
PCI_STOP#1
SDRAM (0:15)
VDDSDR
IN
17, 18, 20, 21, 26,
27, 30, 31, 36, 37,
39, 40, 42, 43, 45,
46
OUT
SDRAM clock outputs.
Supply for SDRAM (0:15), PLL Core and 24MHz clocks,
nominal 3.3V.
19, 25, 38, 44
PWR
23
24
32
SDATA
SCLK
IN
IN
Data input for I2C serial input.
Clock input of I2C input
VDD48
24MHz
PWR
OUT
Supply for 48MHz clocks 3.3V nominal
24MHz output clock
33
34
Pin 15, pin 54 function select pin, 1=Desktop Mode,
0=Mobile Mode. Latched Input.
MODE1, 2
IN
48MHz
OUT
48MHz output clock
FS01, 2
IN
Frequency select pin. Latched Input
48, 49, 51, 52
50
CPUCLK(0:3)
VDDLCPU
OUT
PWR
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Supply for CPU (0:3), either 2.5V or 3.3V nominal
14.318 MHz reference clock, (in Desktop Mode, MODE=1) This REF output
is the STRONGER buffer for ISA BUS loads.
Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile
Mode, MODE=0)
REF1
OUT
IN
54
CPU_STOP#1
55
56
IOAPIC
OUT
PWR
IOAPIC clock output. 14.318 MHz Powered by VDDL1.
Supply for IOAPIC, either 2.5 or 3.3V nominal
VDDLIOAPIC
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
2
ICS9250-13
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
Pin 46
Pin 15
CPU_STOP#
(INPUT)
PCI_STOP#
(INPUT)
0
REF1
(OUTPUT)
PCICLK5
(OUTPUT)
1
Power Management Functionality
PCICLK_F,
REF,
24/48MHz
and SDRAM
CPUCLK
Outputs
PCICLK
(0:5)
Crystal
OSC
CPU_STOP# PCI_STOP#
VCO
0
1
1
1
1
0
Stopped Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK and IOAPIC drivers.
CPU3.3#_2.5
Buffer Selected for
Input level
operation at:
(Latched Data)
1
0
2.5V VDD
3.3V VDD
Functionality
VDD1,2,3 = 3.3V±5%, VDDL1,2 = 2.5V±5% or 3.3±5%, TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz
CPU
(MHz)
90.00
89.01
88.00
86.99
85.91
85.01
84.00
82.00
81.01
80.00
83.31
68.49
78.00
75.00
71.99
66.82
SDRAM
(MHz)
90.00
89.01
88.00
PCICLK
(MHz)
45.00
44.51
44.00
43.50
42.95
42.51
42.00
41.00
40.00
41.65
34.24
34.24
39.00
37.50
35.99
33.41
REF, IOAPIC
(MHz)
14.318
14.318
14.318
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
86.99
85.91
85.01
84.00
82.00
81.01
80.00
83.31
68.49
78.00
75.00
71.99
66.82
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
3
ICS9250-13
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
4
ICS9250-13
Serial Configuration Command Bitmap
Byte0:FunctionalityandFrequencySelectRegister(default=0)
Bit
Description
0 - ±0.25% Spread Spectrum Modulation
1 - ±0.6% Spread Spectrum Modulation
PWD
1
Bit 7
CPUCLK
(MHz)
90.00
89.01
88.00
86.99
85.91
85.01
84.00
82.00
81.01
80.00
83.31
68.49
78.00
75.00
71.99
66.82
SDRAM PCICLK
Bit (2,6:4)
(MHz)
90.00
89.01
88.00
86.99
85.91
85.01
84.00
82.00
81.01
80.00
83.31
68.49
78.00
75.00
71.99
66.82
(MHz)
45.00
44.51
44.00
43.50
42.95
42.51
42.00
41.00
40.51
40.00
41.65
34.24
39.00
37.50
35.99
33.41
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bit
(2,6:4)
XXX
Note 1
0-Frequency is selected by hardware select,
Bit 3
latched inputs
0
1- Frequency is selected by Bit 2,6:4
0 - Normal operation
Bit 1
Bit 0
1
0
1 - Spread Spectrum Enabled
0 - Running
1 - Tristate all outputs
Note 1. Default at Power-up will be for latched logic inputs to define frequenc,. Bits 2, 6:4 are default to 0000.
5
ICS9250-13
Byte 1: Control Register
(1 = enable, 0 = disable)
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Pin # PWD
Description
(Reserved)
(Reserved)
FS2#
FS0#
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Bit
Pin # PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
X
1
1
1
1
1
1
1
FS3#
7
PCICLK_F (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
-
-
48
49
51
52
X
X
1
1
1
15
13
12
11
10
8
1
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: Control Register
(1 = enable, 0 = disable)
Byte 4: Control Register
(1 = enable, 0 = disable)
Bit
Pin #
36
37
39
40
42
43
45
46
PWD
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Bit
Pin #
26
27
30
31
17
18
20
21
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
SDRAM15 (Act/Inact)
SDRAM14 (Act/Inact)
SDRAM13 (Act/Inact)
SDRAM12 (Act/Inact)
SDRAM11 (Act/Inact)
SDRAM10 (Act/Inact)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: Control Register
(1 = enable, 0 = disable)
Bit
Pin #
-
-
-
55
-
-
54
2
PWD
1
1
1
1
X
1
1
Description
(Reserved)
(Reserved)
(Reserved)
IOAPIC (Act/Inact)
FS1#
(Reserved)
REF1 (Act/Inact)
REF0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
6
ICS9250-13
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9250-13. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9250-13.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
7
ICS9250-13
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9250-13. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by theICS9250-13 internally.The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
8
ICS9250-13
Shared Pin Operation -
Input/Output Pins
header may be used.
Pins 2, 7, 8, 25, and 26 on the ICS9250-13 serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 4-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
Fig. 1
9
ICS9250-13
Fig. 2a
Fig. 2b
10
ICS9250-13
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V ±5% VDDL = 2.5V ± 5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating Supply Current
Input Frequency
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
IIH
VIN = VDD
0.1
2.0
µA
µA
µA
mA
MHz
pF
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66MHz
VDD = 3.3 V
-5
IIL2
-200
-100
IDD2.5OP
Fi
160
16
5
12
27
14.32
CIN
Logic Inputs
Input Capacitance1
CINX
TTrans
Ts
X1 & X2 pins
36
1.3
0.3
< 2
2.15
70
45
2
pF
Transition Time1
Settling Time1
Clk Stabilization1
To 1st crossing of target Freq.
ms
TSTAB
From VDD = 3.3 V to 1% target Freq.
2
4
ms
ns
ps
TCPU-PCI2 VT = 1.5 V
TCPU-SDRAM2 VT = 1.5 V
1
Skew1
500
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating Supply Current
Skew1
SYMBOL
IDD2.5OP
CONDITIONS
MIN
TYP
MAX UNITS
CL = 0 pF; Select @ 66.8 MHz
20
mA
TCPU-PCI2 VT=1.5 V; VTL=1.25 V
TCPU-SDRAM2
1
2.15
70
4
ns
ps
VT=1.5 V;VTL=1.25 V
1Guaranteed by design, not 100% tested in production.
500
11
ICS9250-13
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH3
CONDITIONS
MIN
2.4
TYP
2.85
0.35
-60
45
MAX UNITS
V
IOH = -25 mA
IOL = 20 mA
VOH = 2.0 V
VOL = 0.8 V
VOL3
0.4
-40
V
mA
mA
ns
IOH3
IOL3
35
46
1
Tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.6
2.4
2.2
56
1
Fall Time
Tf3
1.8
ns
1
Duty Cycle
Dt3
52
%
Skew1
Tsk1
VT = 1.5 V
325
500
ps
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
CONDITIONS
MIN
2
TYP
2.4
0.32
-37
26
MAX UNITS
V
IOH = -8.0 mA
IOL = 12 mA
VOH =1.7 V
VOL = 0.7 V
0.4
-16
V
mA
mA
ns
IOH2B
IOL2B
19
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.3
1.5
50
1.9
1.9
55
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
%
1
Skew
tsk2B
VT = 1.25 V
78
175
350
150
250
ps
1
Jitter, Cycle-to-cycle
tjcyc-cyc2B
VT = 1.25 V, Normal or Spread mode
VT = 1.25 V
170
45
ps
1
Jitter, One Sigma
Jitter, Absolute
tj1σ2B
ps
1
tjabs2B
VT = 1.25 V
-250
120
ps
1Guaranteed by design, not 100% tested in production.
12
ICS9250-13
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
IOH = -28 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
3
VOL1
0.17
-60
45
0.4
-40
V
IOH1
mA
mA
IOL1
41
45
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.4
1.4
50
2
ns
ns
%
ps
ps
ps
ps
Fall Time1
Duty Cycle1
2
dt1
55
Skew1
tsk1
VT = 1.5 V
280
230
75
500
400
150
250
Jitter, Cycle-to-cycle1
Jitter, One Sigma1
Jitter, Absolute1
tjcyc-cyc1a
tj1σ1a
tjabs1a
VT = 1.5 V, Normal or Spread mode
VT = 1.5 V
VT = 1.5 V
-250
160
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH4B
VOL4B
CONDITIONS
MIN
2
TYP
2.3
0.3
-26
27
MAX UNITS
V
IOH = -8.0 mA
IOL = 12 mA
VOH =1.7 V
VOL = 0.7 V
0.4
-15
V
mA
mA
ns
IOH4B
IOL4B
19
1
tr4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.3
1.35
52
2.2
2
1
Fall Time
tf4B
ns
1
Duty Cycle
dt4B
45
55
%
1
Jitter, One Sigma
Jitter, Absolute
tj1σ4B
VT = 1.25 V
235
510
350
800
ps
1
tjabs4B
VT = 1.25 V
-800
ps
1Guaranteed by design, not 100% tested in production.
13
ICS9250-13
Electrical Characteristics - REF, 24 MHz, 48 MHz
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
2.9
0.3
-30
23
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 10 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-20
V
IOH5
mA
mA
IOL5
16
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.95
2.1
4
ns
ns
%
ps
ps
4
dt5
45
51
55
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
170
400
400
800
VT = 1.5 V
-800
1Guaranteed by design, not 100% tested in production.
14
ICS9250-13
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
NOM. MAX.
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
.006
See Variations
.296
MAX.
.110
.016
.092
.0135
.0085
MIN.
.720
A
A1
A2
B
C
D
E
e
H
h
AD
.725
.730
56
.292
.299
SSOP Package
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
L
.032
N
See Variations
5°
.093
0°
.085
8°
.100
X
Ordering Information
ICS9250yF-13
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
RevisionDesignator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
15
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