ICS9250YF-19LF [IDT]
Processor Specific Clock Generator, 150MHz, PDSO56, 0.300 INCH, SSOP-56;
| 型号： | ICS9250YF-19LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 150MHz, PDSO56, 0.300 INCH, SSOP-56 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总15页 (文件大小：562K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9250-19
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
BX, Appollo Pro 133 type of chip set.
Output Features:
Pin Configuration
•
•
•
•
•
•
•
3 - CPUs @2.5V, up to 150MHz.
17 - SDRAM @ 3.3V, up to 150MHz.
7 - PCI @3.3V
2 - IOAPIC @ 2.5V
1 - 48MHz, @3.3V fixed.
1 - 24MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
Features:
•
•
Up to 150MHz frequency support
Support power management: CPU, PCI, stop and Power
down Mode form I2C programming.
•
•
Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
Uses external 14.318MHz crystal
Key Specifications:
•
•
•
•
CPU – CPU: <175ps
CPU – PCI: 1 - 4ns
PCI – PCI: <500ps
SDRAM - SDRAM: <250ps
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
** Internal Pull-down resistor of 240K to GND on indicated inputs.
Block Diagram
Functionality
CPU
(MHz)
133
FS3
FS2
FS1
FS0
PCICLK (MHz)
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
124
150
140
105
110
115
120
100.0
133
112
103
66.6
83.3
75
35 (CPU/3)
36.67 (CPU/3)
38.33 (CPU/3)
40.00 (CPU/3)
33.43 (CPU/3)
44.33 (CPU/3)
37.33 (CPU/3)
34.33 (CPU/2)
33.40 (CPU/2)
41.65 (CPU/2)
37.5 (CPU/2)
41.33 (CPU/2)
124
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9250-19 Rev C 4/12/01
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.
ICS9250-19
Pin Configuration
PIN NUMBER
PIN NAME
REF1
FS21
TYPE
OUT
IN
DESCRIPTION
14.318 MHz reference clock output
2
Latched frequency select input. Has pull-up to VDDPCI
14.318MHz reference clock output
REF0
OUT
3
Halts PCICLK [5:1] at logic "0" level when low.
(in mobile, MODE=0)
PCI_STOP#
IN
4, 10, 23, 26, 34, 42,
48, 53
GND
X1
PWR
IN
Ground.
5
6
14.318MHz input. Has internal load cap, (nominal 33pF).
Crystal output. Has internal load cap (33pF) and feedback
resistor to X1
X2
OUT
OUT
IN
PCICLK_F
MODE1
Free running BUS clock not afected by PCI_STOP#
8
9
Latched input for MODE select. Converts pin 3 to PCI_STOP# when
low for power management.
FS3
IN
Latched frequency select input, pull-down
PCICLK0
OUT
Free running BUS clock not afected by PCI_STOP#
16, 14, 13, 12, 11 PCICLK [5:1]
OUT
PCI Clock Outputs.
17
27
28
BUFFERIN
SDATA
IN
IN
IN
Input for Buffers
Serial data in for serial config port. (I2C)
Clock input for serial config port. (I2C)
SCLK
24MHz
FS01
OUT
IN
24MHz clock output for Super I/O or FD.
30
Latched frequency select input. Has pull-up to VDD4.
48MHz
FS11
OUT
IN
48MHz clock output for USB.
29
Latched frequency select input. Has pull-up to VDD2.
1, 7, 15, 20,
31, 37, 45
24, 25, 32, 33, 18,
19, 21, 22, 35, 36,
38, 39, 40, 41, 43,
44
VDDPCI, VDDREF,
VDDSDR, VDD48
PWR
Nominal 3.3V power supply, see power groups for function.
SDRAM clocks
SDRAM [15:0]
OUT
46
47
SDRAM_F
OUT
IN
Free running SDRAM clock Not affected by CPU_STOP#
Halts CPUCLK [2:1], IOAPIC0, SDRAM [15:0]
clocks at logic "0" level when low.
CPU_STOP#
VDDLCPU,
VDDLIOAPIC
50, 56
PWR
CPU and IOAPIC clock buffer power supply, 2.5V nominal.
55
51, 49
52
IOAPIC0
OUT
OUT
OUT
IOAPIC clock output. (14.318 MHz) Poweredby VDDL1
CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz)
Free running CPU output clock. Not affected ty the CPU_STOP#.
CPUCLK [2:1]
CPUCLK_F
Freerunning IOAPIC clock output. Not affected by the CPU_STOP#
(14.31818 MHz) Powered by VDDL1
54
IOAPIC_F
OUT
Notes:
1: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9250-19
General Description
The ICS9250-19 is the single chip clock solution for Desktop/designs using BX, Appollo Pro 133 type of chip sets. It provides
all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-19
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
MODE
(Latched Input)
PCI_STOP#
0
(Input)
REF0
(Output)
1
Third party brands and names are the property of their respective owners.
3
ICS9250-19
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Address
D2(H)
Address
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
D3(H)
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
4
ICS9250-19
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
0
0 = 0 to -0.5% Down Spread Spectrum Modulation
1 = ±0.25% Center Spread Spectrum Modulation
Bit 7
Bit2 Bit6 Bit5 Bit4
CPU clock
PCI
0111
0110
0101
0100
0011
0010
0001
0000
1111
1110
1101
1100
1011
1010
1001
1000
100.0
133
112
103
66.6
83.3
75
124
133
124
150
140
105
110
115
120
33.43 (CPU/3)
44.33 (CPU/3)
37.33 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.65(CPU/2)
37.5 (CPU/2)
41.33 (CPU/3)
33.25 (CPU/4)
31.00 (CPU/4)
37.50 (CPU/4)
35.00 (CPU/4)
35.00 (CPU/3)
36.67 (CPU/3)
38.33 (CPU/3)
40.00 (CPU/3)
Note1
Bit 2,
Bit 6:4
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 6:4 (above)
0 - Normal
1 - Spread Spectrum Enabled (Center Spread)
0 - Running
Bit 3
Bit 1
Bit 0
0
1
0
1- Tristate all outputs
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6
are default to 000, and if bit 3 is written to a 1 to use Bits 6:4, then these should be
defined to desired frequency at same write cycle.
Note: PWD = Power-Up Default
Third party brands and names are the property of their respective owners.
5
ICS9250-19
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Reserved
8
PCICLKF (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
-
Reserved
16
14
13
12
11
9
-
Reserved
46
49
51
52
SDRAM_F (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK_F (Act/Inact)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
X
1
Latched FS0#
Reserved
-
1
1
1
1
-
Reserved
1
Reserved
29
30
48MHz (Act/Inact)
24MHz (Act/Inact)
X
1
Latched FS1#
Reserved
33, 32,
25, 24
22, 21,
19, 18
39, 38,
36, 35
44, 43,
41, 40
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
SDRAM(12:15) (Act/Inact)
SDRAM (8:11) (Act/Inact)
SDRAM (4:7) (Act/Inact)
SDRAM (0:3) (Act/Inact)
1
Reserved
X
1
Latched FS3#
Reserved
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
X
1
Notes:
Latched FS2#
1. Inactive means outputs are held LOW and are disabled
from switching.
54
55
-
IOAPIC_F (Act/Inact)
IOAPIC0 (Act/Inact)
Reserved
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
1
1
-
1
Reserved
2
1
REF1 (Act/Inact)
REF0 (Act/Inact)
3
1
Third party brands and names are the property of their respective owners.
6
ICS9250-19
Shared Pin Operation -
Input/Output Pins
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
The I/O pins designated by (input/output) on the ICS9250-
19 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 4-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the device’s
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Fig. 1
Third party brands and names are the property of their respective owners.
7
ICS9250-19
Fig. 2a
Fig. 2b
Third party brands and names are the property of their respective owners.
8
ICS9250-19
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9250-19. All other clocks will continue to run while the CPUCLKs are disabled. The
CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the
CPUCLKs inside the ICS9250-19.
3. IOAPIC output is stopped Glitch Free by CPUSTOP# going low.
4. PCI_STOP# is shown in a high (true) state.
5. All other clocks continue to run undisturbed.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9250-19. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9250-19 internally. PCICLK (0:5) clocks are stopped in a low state and started with a full
high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK
clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the device.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
Third party brands and names are the property of their respective owners.
9
ICS9250-19
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
IIH
VIN = VDD
0.1
2.0
µ
µ
µ
A
A
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
-100
150
IDD3.3OP100 Select @ 100MHz; Sdram running
IDD3.3OP133 Select @ 133MHz; Sdram running
180
mA
Supply Current
200
n/a
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V
12
27
14.318
16
MHz
pF
CIN
Logic Inputs
5
45
4
CINX
TTrans
TS
X1 & X2 pins
36
1
pF
Transition Time1
Settling Time1
Clk Stabilization1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ms
3
TStab
4
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
IDD2.5OP100
IDD2.5OP133
CONDITIONS
Select @ 100MHz; Max discrete cap loads
MIN
TYP
13
18
MAX UNITS
Operating
25
mA
25
Select @ 133MHz; Max discrete cap loads
Supply Current
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
10
ICS9250-19
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
2.3
0.2
-41
37
0.4
-19
V
mA
mA
ns
IOL2B
19
0.4
0.4
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.6
1.6
1
Fall Time
tf2B
1
ns
1
Duty Cycle
dt2B
51
55
%
1
Skew
group1: 1,2 and 1,F
tsk2B
VT = 1.25 V
120
175
295
250
+250
250
ps
1
Skew
group2: 2, F
tsk2B
VT = 1.25 V
ps
1
tj1 2B
σ
Jitter, One Sigma
Jitter, Absolute
VT = 1.25 V
120
100
150
ps
1
tjabs2B
VT = 1.25 V
-250
ps
1
tjcyc-cyc2B
VT = 1.25 V
Jitter, Cycle-to-cycle
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz, 24MHz,REF0
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
2.9
0.25
-42
18
1.1
1
MAX UNITS
V
IOH = -14 mA
IOL = 6.0 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
IOH5
IOL5
tr5
tf5
dt5
tj1s5
tjabs5
0.4
-20
V
mA
mA
10
45
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
2.5
2.5
ns
ns
Fall Time1
Duty Cycle1
VT = 1.5 V
50
100
55
250
%
ps
Jitter1
VT = 1.5 V, 24, 48MHz
VT = 1.5 V, REF0
Jitter1
250
800
ps
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
ICS9250-19
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs
PARAMETER
SYMBOL
VOH1
VOL1
CONDITIONS
MIN
2.4
TYP
2.9
0.2
-58
52
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
0.4
-22
V
mA
mA
IOH1
IOL1
25
45
Rise Time1
Fall Time1
tr1
tf1
VOL = 0.8 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.4
50
2.5
2.5
55
ns
ns
%
Duty Cycle1
Skew1
dt1
tsk1
tj1
VT = 1.5 V
270
50
500
150
500
ps
ps
ps
Jitter, One Sigma1
VT = 1.5 V
VT = 1.5 V
1
σ
Jitter, Absolute1
tjabs1
200
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL =30 pF
PARAMETER
SYMBOL
VOH1
VOL1
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -28 mA
IOL = 19 mA
VOH = 2.0 V
VOL = 0.8 V
2.8
0.34
-72
50
0.4
-42
V
mA
mA
IOH1
IOL1
33
0.5
0.5
45
Rise Time1
Fall Time1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 04 V
VT = 1.5 V
2
ns
ns
%
2.4
55
Duty Cycle1
dt1
50
Skew(Group1: F,0:4, 8:11)1
Skew(Group2: 5, 7, 12:15)1
Skew(Group3: 0, 13)1
Skew(Group4: 6, 13)1
Skew(Buferin-Output)1
Jitter, One Sigma1
Jitter, Absolute1
tsk1
tsk1
tsk1
tsk1
tsk1
VT = 1.5 V
130
180
250
250
490
910
4.4
150
250
ps
ps
ps
ps
ns
ps
ps
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
3.5
50
tj1
1
VT = 1.5 V
VT = 1.5 V
σ
tjabs1
-250
130
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
ICS9250-19
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH4B
VOL4B
CONDITIONS
MIN
2
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
2.2
0.3
-32
26
1.5
1
51
240
619
0.4
-19
V
mA
mA
IOH4B
IOL4B
Tr4B
Tf4B
Dt4B
19
0.4
0.4
45
Rise Time1
Fall Time1
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.8
1.6
55
300
650
ns
ns
%
ps
ps
Duty Cycle1
Jitter, One Sigma1
Tj1σ4B
Tjabs4B
VT = 1.25 V
VT = 1.25 V
Jitter, Absolute1
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
13
ICS9250-19
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
Ferrite
Bead
Ferrite
Bead
C2
22µF/20V
Tantalum
C2
22µF/20V
Tantalum
VDD
VDD
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
1
56
C3
2
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
3
2.5V Power Route
4
Notes:
C1
C1
5
1) All clock outputs should have a
series terminating resistor, and a 20pF
capacitor to ground between the
resistor and clock pin. Not shown in
all places to improve readibility of
diagram.
1
6
Clock Load
2
7
C3
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2) Optional crystal load capacitors are
recommended. They should be
included in the layout but not
inserted unless needed.
3.3V Power Route
3.3V Power Route
Ground
Ground
Component Values:
C1 : Crystal load values determined by user
C2 : 22 F/20V/D case/Tantalum
AVX TAJD226M020R
C3 : 100pF ceramic capacitor
C4 : 20pF capacitor
FB = Fair-Rite products 2512066017X1
All unmarked capacitors are 0.01 F ceramic
Connections to VDD:
= Routed Power
= Ground Connection (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
Third party brands and names are the property of their respective owners.
14
ICS9250-19
In Millimeters
In Inches
c
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
a
hh xx 4455°°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
α
A1
VARIATIONS
D mm.
- CC --
D (inch)
N
e
SEATING
PLANE
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
b
56
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS9250yF-19
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
15
information being relied upon by the customer is current and accurate.
相关型号：
ICS9250YF-27LF-T
Processor Specific Clock Generator, 133MHz, PDSO56, 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56
IDT
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