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ICS93716BGLF

更新时间：2024-09-18 14:55:59

品牌：IDT

描述：Clock Driver, PDSO28

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ICS93716BGLF 概述

Clock Driver, PDSO28 时钟驱动器

ICS93716BGLF 规格参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.83	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3	最大I（ol）：	0.012 A
湿度敏感等级：	3	端子数量：	28
最高工作温度：	85 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP28,.3	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
电源：	2.5 V	认证状态：	Not Qualified
子类别：	Clock Drivers	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	温度等级：	OTHER
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	Base Number Matches：	1

ICS93716BGLF 数据手册

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ICS93716

Integrated

Circuit

Systems,Inc.

Low Cost DDR Phase Lock Loop Clock Driver

RecommendedApplication:

DDR Clock Driver

Pin Configuration

CLKC0

CLKT0

VDD

CLKT1

CLKC1

GND

CLKC5

CLKT5

CLKC4

CLKT4

VDD

SDATA

FBINC

FBINT

FB_OUTT

FB_OUTC

CLKT3

CLKC3

GND

ProductDescription/Features:

•

Low skew, low jitter PLL clock driver

I²C for functional and output control

•

Feedback pins for input to output synchronization

Spread Spectrum tolerant inputs

SCLK

CLK_INT

CLK_INC

VDDA

GND

VDD

CLKT2

CLKC2

•

Bypass mode on B revision only

SwitchingCharacteristics:

•

PEAK - PEAK jitter (66MHz): <75ps

CYCLE - CYCLE jitter (>100MHz):<65ps

OUTPUT - OUTPUT skew: <100ps

Output Rise and Fall Time: 550ps - 950ps

28-Pin SSOP and TSSOP

Functionality

INPUTS

OUTPUTS

PLL State

AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC

2.5V

(nom)

off

2.5V

(nom)

2.5V

(nom)

<20MHz

GND

Bypassed/off

Block Diagram

FB_OUTT

FB_OUTC

Control

SCLK

CLKT0

CLKC0

Logic

SDATA

CLKT1

CLKC1

CLKT2

CLKC2

CLKT3

CLKC3

FB_INT

FB_INC

PLL

CLK_INC

CLK_INT

CLKT4

CLKC4

CLKT5

CLKC5

0420H—09/10/08

ICS93716

Pin Descriptions

PIN NUMBER

PIN NAME

GND

TYPE

DESCRIPTION

6, 11, 15, 28

PWR Ground

27, 25, 16, 14, 5, 1 CLKC(5:0)

26, 24, 17, 13, 4, 2 CLKT(5:0)

OUT

"Complementary" clocks of differential pair outputs.

"True" Clock of differential pair outputs.

3, 12, 23

VDD

PWR Power supply 2.5V

SCLK

Clock input of I²C input, 5V tolerant input

CLK_INT

CLK_INC

VDDA

"True" reference clock input

"Complementary" reference clock input

PWR Analog power supply, 2.5V

"Complementary" Feedback output, dedicated for external feedback. It

switches at the same frequency as the CLK. This output must be wired

to FB_INC.

FB_OUTC

OUT

"True" " Feedback output, dedicated for external feedback. It switches

at the same frequency as the CLK. This output must be wired to

FB_INT.

FB_OUTT

FB_INT

OUT

"True" Feedback input, provides feedback signal to the internal PLL for

synchronization with CLK_INT to eliminate phase error.

"Complementary" Feedback input, provides signal to the internal PLL

for synchronization with CLK_INC to eliminate phase error.

FB_INC

SDATA

Data input for I²C serial input, 5V tolerant input

0420H—09/10/08

ICS93716

Byte0:OutputControl

(1= enable, 0 = disable)

Byte1:OutputControl

(1= enable, 0 = disable)

BIT

Bit 7

Bit 6

Bit 5

Bit 4

PIN# PWD

DESCRIPTION

CLKT0, CLKC0

BIT

PIN# PWD

DESCRIPTION

2, 1

Bit 7

Reserved

Bit 6 17, 16

CLKT3, CLKC3

Reserved

4, 5

CLKT1, CLKC1

Reserved

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

Bit 3 13, 14

Bit 2 26, 27

CLKT2, CLKC2

CLKT5, CLKC5

Reserved

Bit 1

Bit 0 24, 25

CLKT4, CLKC4

Byte2:Reserved

(1= enable, 0 = disable)

Byte3:Reserved

(1= enable, 0 = disable)

BIT

PIN# PWD

DESCRIPTION

BIT PIN# PWD

DESCRIPTION

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

Byte4:Reserved

(1= enable, 0 = disable)

Byte5:Reserved

(1= enable, 0 = disable)

BIT

PIN# PWD

DESCRIPTION

BIT PIN# PWD

DESCRIPTION

Reserved (Note)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Reserved (Note)

Note: Don’t write into this register, writing into this

0420H—09/10/08

ICS93716

Absolute Maximum Ratings

Supply Voltage (VDD & AVDD). . . . . . . . . . . -0.5V to 4.6V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to V_DD+ 0.5V

Ambient OperatingTemperature . . . . . . . . . . 0°C to +85°C

StorageTemperature. . . . . . . . . . . . . . . . . . . -65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These

ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose

listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect product reliability.

Electrical Characteristics - Input/Supply/Common Output Parameters

T_A= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R_L= 120Ω, C_L=15pF (unless otherwise stated)

PARAMETER

Input High Current

Input Low Current

SYMBOL

I_IH

CONDITIONS

V_I= V_DDor GND

MIN

TYP

MAX

UNITS

µA

I_IL

V_I= V_DDor GND

R_L= 120Ω, C_L= 0pf @ 170MHz

Operating Supply

Current

I_DD2.5

250

350

I_DDPDC_L= 0pf

Input Clamp Voltage

V_IK

V_DDQ= 2.3V Iin = -18mA

I_OH= -1 mA

-1.2

High-level output

voltage

V_DD- 0.1

1.7

V_OH

_OH= -12 mA

_OL=1 mA

0.1

0.6

Low-level output voltage

V_OL

C_IN

_OL=12 mA

Input Capacitance¹

Output Capacitance¹

¹Guaranteed by design at 233MHz, not 100% tested in production.

V_I= GND or V_DD

C_OUTV_OUT= GND or V_DD

0420H—09/10/08

ICS93716

DC Electrical Characteristics

(see note1)

T_A= 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)

PARAMETER

Supply Voltage

SYMBOL

CONDITIONS

MIN

2.3

TYP

2.5

MAX

2.7

UNITS

V_DDQ, A_VDD

CLK_INT, CLK_INC, FB_INC,

FB_INT

SCLK, SDATA

CLK_INT, CLK_INC, FB_INC,

FB_INT

SCLK, SDATA

0.4

V_DD/2 - 0.18

0.7

Low level input voltage

High level input voltage

V_IL

-0.3

V_DD/2 + 0.18

1.7

2.1

V_IH

V_IN

DC input signal voltage

(note 2)

-0.3

V_DD+ 0.3

DC - CLK_INT, CLK_INC,

FB_INC, FB_INT

AC - CLK_INT, CLK_INC,

FB_INC, FB_INT

0.36

0.7

V_DD+ 0.6

Differential input signal

voltage (note 3)

V_ID

Output differential cross-

voltage (note 4)

Input differential cross-

voltage (note 4)

High Impedance

Output Current

Operating free-air

temperature

V_OX

V_IX

I_OZ

T_A

V_DD/2 - 0.15

V_DD/2 + 0.15

V_DD/2 - 0.2 V_DD/2 V_DD/2 + 0.2

V_DD=2.7V, V_OUT=V_DDor GND

0.1

µA

°C

Notes:

1. Unused inputs must be held high or low to prevent them from floating.

2. DC input signal voltage specifies the allowable DC excursion of differential input.

3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]

required for switching, where VTR is the true input level and VCP is the

complementary input level.

4. Differential cross-point voltage is expected to track variations of V_DDand is the

voltage at which the differential signal crosses.

0420H—09/10/08

ICS93716

Timing Requirements

T_A= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R_L= 120Ω, C_L=15pF (unless otherwise

CONDITIONS

PARAMETER

SYMBOL

freq_op

MIN

MAX UNITS

Max clock frequency³

Application Frequency

Range³

233

170

MHz

freq_App

d_tin

Input clock duty cycle

CLK stabilization

T_STAB

100

µs

Switching Characteristics

T_A= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R_L= 120 , C_L=15pF (unless otherwise stated)

PARAMETER

Low-to high level

propagation delay time

High-to low level propagation

delay time

SYMBOL

CONDITION

MIN

TYP

MAX UNITS

CLK_IN to any output

5.5

t_PLH

CLK_IN to any output

5.5

t_PHL

Duty Cycle

Input clock slew rate

Cycle to Cycle Jitter¹

Phase error

t_sl(I)

v/ns

t_cyc-t_cyc

100MHz < f < 170MHz

f=66MHz

-150

550

150

100

950

t_{(phase error)}

t_skew

Output to Output Skew

Rise Time, Fall Time

Notes:

t_r, t_f

See figure 8

1. Refers to transition on noninverting output in PLL bypass mode.

2. While the pulse skew is almost constant over frequency, the duty cycle error

increases at higher frequencies.This is due to the formula: duty cycle=t_wH/t_c, were

the cycle (t_c) decreases as the frequency goes up.

3. Switching characteristics guaranteed for application frequency range.

4. Static phase offset shifted by design.

0420H—09/10/08

ICS93716

Parameter Measurement Information

(CLKC)

R = 60Ω

(CLKC)

ICS93716

GND

Figure 1. IBIS Model Output Load

VDD/2

C = 15 pF

ICS93716

-VDD/2

SCOPE

R = 10Ω Z = 50Ω

Z = 60Ω

R = 50Ω

(TT)

R = 10Ω

Z = 50Ω

R = 50Ω

C = 15 pF

-VDD/2

(TT)

-VDD/2

NOTE: V

(TT) = GND

Figure 2. Output Load Test Circuit

Y_X, FB_OUTC

Y_X, FB_OUTT

c(n+1)

c(n)

= t

jit(cc) c(n) c(n+1)

Figure 3. Cycle-to-Cycle Jitter

0420H—09/10/08

ICS93716

Parameter Measurement Information

CLK_INC

CLK_INT

FB_INC

FB_INT

( ) n

( ) n+1

n = N

( ) n

( )

(N is a large number of samples)

Figure 4. Static Phase Offset

Y_X

Y_X, FB_OUTC

Y_X, FB_OUTT

t_(skew)

Figure 5. Output Skew

Y_X, FB_OUTC

Y_X, FB_OUTT

t_C(n)

Y_X, FB_OUTC

Y_X, FB_OUTT

f_O

t_{(jit_per)}t_c(n)

Figure 6. Period Jitter

0420H—09/10/08

ICS93716

Parameter Measurement Information

Y_X, FB_OUTC

Y_X, FB_OUTT

jit(hper_n+1)

jit(hper_n)

t_jit(hper)₌t_{jit(hper_n)}

2xf_O

Figure 7. Half-Period Jitter

80%

V , V

ID OD

20%

Clock Inputs

and Outputs

slf

slr

Figure 8. Input and Output Slew Rates

0420H—09/10/08

ICS93716

General I²C serial interface information

The information in this section assumes familiarity with I²C programming.

For more information, contact ICS for an I²C programming application note.

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D2 _(H)

• ICS clock will acknowledge

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the read address D3 _(H)

• ICS clock will acknowledge

• Controller (host) sends a dummy command code

• ICS clock will acknowledge

• ICS clock will send the byte count

• Controller (host) acknowledges

• Controller (host) sends a dummy byte count

• ICS clock will acknowledge

• Controller (host) starts sending first byte (Byte 0)

through byte 5

• ICS clock sends first byte (Byte 0) through byte 5

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a stop bit

• ICS clock will acknowledge each byte one at a time.

• Controller (host) sends a Stop bit

How to Write:

Controller (Host)

ICS (Slave/Receiver)

How to Read:

Start Bit

Controller (Host)

ICS (Slave/Receiver)

Address

Start Bit

D2_(H)

Address

D3_(H)

ACK

Dummy Command Code

ACK

Byte Count

Dummy Byte Count

Byte 0

ACK

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

ACK

Stop Bit

Notes:

The ICS clock generator is a slave/receiver, I²C component.It can read back the data stored in the latches for

verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.

The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

The input is operating at 3.3V logic levels.

The data byte format is 8 bit bytes.

To simplify the clock generator I²C interface, the protocol is set to use only "Block-Writes" from the controller.

The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any

complete byte has been transferred. The Command code and Byte count shown above must be sent, but the

data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.

At power-on, all registers are set to a default condition, as shown.

0420H—09/10/08

ICS93716

In Millimeters

In Inches

SYMBOL

COMMON DIMENSIONS COMMON DIMENSIONS

MIN

0.05

1.65

0.22

0.09

MAX

2.00

1.85

0.38

0.25

MIN

.002

.065

.009

.0035

MAX

.079

.073

.015

.010

INDEX

AREA

SEE VARIATIONS

7.40

5.00

8.20

5.60

.291

.197

.323

.220

0.65 BASIC

0.0256 BASIC

0.55

0.95

.022

.037

SEE VARIATIONS

0°

8°

0°

8°

- C -

VARIATIONS

D mm.

D (inch)

SEATING

PLANE

MIN

9.90

MAX

10.50

MIN

.390

MAX

.413

.10 (.004) C

Reference Doc.: JEDEC Publication 95, MO-150

10-0033

Ordering Information

93716yFLF-T

Example:

XXXXX y F LF- T

Designation for tape and reel packaging

Annealed Lead Free (Optional)

Package Type

F = SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

0420H—09/10/08

ICS93716

In Millimeters

COMMON DIMENSIONS COMMON DIMENSIONS

In Inches

SYMBOL

MIN

0.05

0.80

0.17

0.09

MAX

1.20

0.15

1.05

0.27

0.20

MIN

.002

.032

.007

.0035

MAX

.047

.006

.041

.012

.008

INDEX

AREA

SEE VARIATIONS

8.10 BASIC

SEE VARIATIONS

0.319 BASIC

6.00

0.65 BASIC

0.45

6.20

.236

0.0256 BASIC

.018

.244

0.75

.030

SEE VARIATIONS

aaa

0°

8°

0.10

0°

8°

.004

VARIATIONS

D mm.

D (inch)

MIN

9.60

MAX

9.80

MIN

.378

MAX

.386

- CC --

Reference Doc.: JEDEC Publication 95, MO-153

SEATING

PLANE

10-0039

aaa

6.10 mm. Body, 0.65 mm. pitch TSSOP

(25.6 mil)

(240 mil)

Ordering Information

93716yGLF-T

Example:

XXXXX y GLF - T

Designation for tape and reel packaging

Annealed Lead Free (Optional)

Package Type

G = TSSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

0420H—09/10/08

ICS93716

Revision History

Rev.

Issue Date Description

Page #

9/10/2008 Updated Product Description/Features

0420H—09/10/08

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