ICS93718F-T [IDT]
Clock Driver, PDSO48;
| 型号： | ICS93718F-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, PDSO48 光电二极管 |
| 文件： | 总9页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ICS93718
DDR and SDRAM Buffer
Pin Configuration
Description
DDR & SDRAM fanout buffer, for VIA Pro 266, KT266 and P4X266
DDR chipsets
FB_OUT
VDD3.3_2.5
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL_DDR*
VDD2.5
GND
DDRT11
DDRC11
DDRT10
DDRC10
VDD2.5
GND
DDRT9
DDRC9
VDD2.5
PD#*
DDRT0_SDRAM0
DDRC0_SDRAM1
DDRT1_SDRAM2
DDRC1_SDRAM3
VDD3.3_2.5
Output Features
•
•
•
Low skew, fanout buffer
1 to 12 differential clock distribution
I2C for functional and output control
GND
DDRT2_SDRAM4
DDRC2_SDRAM5
VDD3.3_2.5
BUF_IN
GND
DDRT3_SDRAM6
DDRC3_SDRAM7
VDD3.3_2.5
•
•
Feedback pin for input to output synchronization
Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs + 2
DDR DIMMs
GND
•
•
•
Frequency supports up to 200MHz (DDR400)
Supports Power Down Mode for power mananagement
CMOS level control signal input
DDRT8
DDRC8
VDD2.5
GND
DDRT7
DDRC7
DDRT6
DDRC6
GND
GND
DDRT4_SDRAM8
DDRC4_SDRAM9
DDRT5_SDRAM10
DDRC5_SDRAM11
VDD3.3_2.5
Key Specifications
•
•
•
•
•
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time for DDR outputs: 500ps - 700ps
DUTY CYCLE: 47% - 53%
48-pin SSOP package
Available in RoHS compliant packaging
SDATA
SCLK
48-Pin SSOP
*Internal Pull-up Resistor of 120K to VDD
Funtional Block Diagram
FuntionalityTable
PIN
VDD
3.3_2.5
MODE
PIN 48
4, 5, 6, 7, 10, 11, 15,
16, 19, 20, 21, 22
FB_OUT
DDRT0_SDRAM0
DDRC0_SDRAM1
BUF_IN
DDR
Mode
These outputs will be
DDR outputs
SEL_DDR=1
SEL_DDR=0
2.5V
3.3V
DDRT1_SDRAM2
DDRC1_SDRAM3
These outputs will be
standard SDRAM
outputs
DDR/SD
Mode
DDRT2_SDRAM4
DDRC2_SDRAM5
SCLK
Control
SDATA
DDRT3_SDRAM6
DDRC3_SDRAM7
Logic
SEL_DDR*
PD#
DDRT4_SDRAM8
DDRC4_SDRAM9
DDRT5_SDRAM10
DDRC5_SDRAM11
DDRT(11:6)
DDRC (11:6)
IDTTM/ICSTM DDR and SDRAM buffer
ICS93718
REV E 02/11/07
ICS93718
DDR and SDRAM Buffer
Pin Description
PIN NUMBER
PIN NAME
FB_OUT
TYPE
DESCRIPTION
1
OUT
Feedback output, dedicated for external feedback
2.5V or 3.3V voltage supply to pins
4, 5, 6, 7, 10, 11, 15 , 16, 19 , 20, 21, 22
2, 8, 12, 17, 23,
VDD3.3_2.5
PWR
3, 9, 14, 18, 26,
31, 35, 40, 46
GND
PWR Ground
45, 43, 39,
34, 30, 28,
DDRT (11:6)
DDRC (11:6)
OUT
OUT
OUT
"True" Clock of differential pair outputs.
44, 42, 38,
33, 29, 27,
"Complementory" clocks of differential pair outputs.
DDRT (5:0)
SDRAM (10, 8, 6, 4, 2, 0)
"True" Clock of differential pair outputs, or 3.3V SDRAM
clock outputs depending on SEL_DDR input
21, 19, 15, 10, 6, 4
DDRC (5:0)
22, 20, 16, 11, 7, 5 SDRAM (11, 9, 7, 5, 3,
1,)
"Complementory" clocks of differential pair outputs, or 3.3V
SDRAM clock outputs depending on SEL_DDR input
OUT
13
BUF_IN
SDATA
SCLK
IN
I/O
IN
Single ended buffer input
24
25
Data pin for I2C circuitry 5V tolerant
Clock input of I2C input, 5V tolerant input
32, 37, 41, 47
VDD2.5
PWR 2.5V voltage supply
Asynchronous active low input pin used to power down the
device into a low power state. The internal clocks are
disabled. The latency of the power down will not be greater
than 3ms.
36
48
PD#
IN
Select input for DDR mode or DDR/SD mode
0=DDR/SD mode 1=DDR mode
SEL_DDR
IN
IDTTM/ICSTM DDR and SDRAM Buffer
ICS93718
REV E 02/11/07
ICS93718
DDR and SDRAM Buffer
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D4(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D5(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte
7
• Controller (host) will need to acknowledge each
byte
• Controller (host) starts sending first byte (Byte 0)
through byte 6
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a
time.
• Controller (host) sends a Stop bit
How to Read:
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Start Bit
Address
Address
D4(H)
D5(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte Count
Dummy Command Code
Dummy Byte Count
Byte 0
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 7
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component.It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes.
The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
IDTTM/ICSTM DDR and SDRAM Buffer
ICS93718
REV E 02/11/07
ICS93718
DDR and SDRAM Buffer
Byte 6: Output Control
(1= enable, 0 = disable)
Byte 7: Output Control
(1= enable, 0 = disable)
BIT
Bit 7 30, 29
Bit 6 28, 27
PIN# PWD
DESCRIPTION
DDRT7, DDRC7
BIT
Bit 7
Bit 6
Bit 5
Bit 4
PIN# PWD
DESCRIPTION
SEL_DDR (Read back only)
(Reserved)
1
1
48
-
1
1
1
1
1
1
1
1
DDRT6, DDRC6
DDRT5, SDRAM10
DDRC5_SDRAM11
DDRT4_SDRAM8
DDRC4_SDRAM9
DDRT3_SDRAM6
DDRC3_SDRAM7
DDRT2_SDRAM4
DDRC2_SDRAM5
DDRT1_SDRAM2
DDRC1_SDRAM3
DDRT0_SDRAM1
DDRC0_SDRAM0
-
(Reserved)
Bit 5 21, 22
Bit 4 19, 20
Bit 3 15, 16
1
1
1
1
1
1
-
(Reserved)
Bit 3 45, 44
Bit 2 43, 42
Bit 1 39, 38
Bit 0 34, 33
DDRT11, DDRC11
DDRT10, DDRC10
DDRT9, DDRC9
DDRT8, DDRC8
Bit 2
Bit 1
Bit 0
10, 11
6, 7
4, 5
IDTTM/ICSTM DDR and SDRAM Buffer
ICS93718
REV E 02/11/07
ICS93718
DDR and SDRAM Buffer
Absolute Max
Supply Voltage (VDD & VDD2.5)
Logic Inputs
Ambient Operating Temperature
Case Temperature
-0.5V to 3.6V
GND –0.5 V to VDD +0.5 V
0°C to +85°C
115°C
Storage Temperature
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
VDD = 3.3V, TA = 0 - 85°C; (unless otherwise stated)
SEL_DDR = 0 SDRAM Outputs
PARAMETER
Input High Current
SYMBOL
IIH
IIL
CONDITIONS
VI = VDD or GND
MIN
TYP
1
MAX
10
UNITS
µA
=
Input Low Current
VI VDD or GND
-100
-20
200
100
3
µA
IDD3.3_2.5 CL = 0pf, 133MHz
250
200
10
mA
mA
mA
mA
Operating Supply Current IDD2.5
IDDPD
CL = 0pf, 133MHz
CL = 0pf, all frequencies
VDD = 3.3V, VOUT = 1V
VDD = 3.3V, VOUT = 1.2V
Output High Current
Output Low Current
IOH
IOL
-74
-18
26
2
42
mA
VDD = 3.3V,
2.95
V
VOH
VOH = -12mA
High-level output voltage
VDD = 3.3V
0.35
2
0.4
VOL
CIN
IOH= 12mA
VI = GND or VDD
Low-level output voltage
Input Capacitance1
pF
1Guaranteed by design, not 100% tested in production.
Recommended Operating Condition
, T = 0 - 85°C; (unless otherwise stated)
SEL_DDR=0 SDRAM Outputs VDD=3.3V
A
PARAMETER
SYMBOL
VDD3.3_2.5
VDD2.5
CONDITIONS
MIN
3.0
2.3
2.0
TYP
3.3
MAX
UNITS
V
3.6
2.7
Power Supply Voltage
2.5
Input High Voltage
Input Low Voltage
VIH
SEL_DDR, PD# input
SEL_DDR, PD# input
V
V
VIL
0.8
Input voltage level
VIN
VDD
V
1Guaranteed by design, not 100% tested in production.
IDTTM/ICSTM DDR and SDRAM Buffer
ICS93718
REV E 02/11/07
ICS93718
DDR and SDRAM Buffer
Electrical Characteristics - Input/Supply/Common Output Parameters
V
DD=2.5, TA = 0 - 85°C; (unless otherwise stated)
SEL_DDR = 1 DDR/DDR_SDRAM Outputs
PARAMETER
Input High Current
SYMBOL
IIH
IIL
CONDITIONS
VI = VDD or GND
MIN
TYP
1
MAX
10
UNITS
µA
=
Input Low Current
VI VDD or GND
-100
-25
76
µA
IDD2.5
IDDPD
IOH
CL = 0pf, 133MHz
200
10
mA
mA
mA
Operating Supply Current
CL = 0pf, all
VDD = 2.5V, VOUT = 1V
3
Output High Current
Output Low Current
-74.5
42.5
-18
VDD = 2.5V, VOUT
=
IOL
26
mA
V
VDD = 2.5V,
1.7
2.3
VOH
VOL
V
V
OH = -12mA
DD = 2.5V
High-level output voltage
0.35
0.46
I
OH = 12mA
Low-level output voltage
Output differential-pair crossing
voltage
Input Capacitance1
(VDD/2) –0.1
1.25 (VDD/2) +0.1
2
V
VOC
CIN
VI = GND or VDD
pF
1Guaranteed by design, not 100% tested in production.
Recommended Operating Condition
SEL_DDR=1 DDR/DDR_SDRAM Outputs = 2.5V
, T = 0 - 85°C (unless otherwise stated)
A
PARAMETER
SYMBOL
VDD3.3_2.5
VDD2.5
VIH
CONDITIONS
MIN
2.3
2.3
2.0
TYP
2.5
MAX
2.7
UNITS
V
Power Supply Voltage
2.5
2.7
Input High Voltage
Input Low Voltage
Input voltage level
SEL_DDR, PD# input
SEL_DDR, PD# input
V
V
V
VIL
0.8
VIN
VDD
1Guaranteed by design, not 100% tested in production.
IDTTM/ICSTM DDR and SDRAM Buffer
ICS93718
REV E 02/11/07
ICS93718
DDR and SDRAM Buffer
Switching Characteristics
DDR_Mode (SEL_DDR = 1), VDD = 2.5 5%
PARAMETER
Operating Frequency
Input clock duty cycle
SYMBOL
CONDITION
MIN
66
40
TYP MAX UNITS
133
50
80
49
50
200
60
100
52
53
MHz
%
ps
%
dtin
Tskew
Output to Output Skew
Output crossover skew DDR[0:11]
66MHz to 100MHz, w/loads
101MHz to 167MHz, w/loads
Measured between 20% and 80%
output, w/loads
48
47
2
Duty cycle
DC
%
Rise Time, Fall Time (DDR
Outputs)
trd, tfd
500
600
700
ps
Switching Characteristics
SD_Mode (SEL_DDR = 0), VDD = 3.3 5%
PARAMETER
Operating Frequency
Input clock duty cycle
SYMBOL
CONDITION
MIN
66
40
TYP MAX UNITS
133
200
MHz
dtin
50
60
%
Output to Output Skew
Duty cycle
Tskew
150
54
ps
%
VT = 1.50V
66MHz to 200MHz
2
DC
Rise Time, Fall Time
(SDRAM Outputs)
SDRAM Buffer LH Prop.
Delay1
SDRAM Bufer HL Prop.
Delay1
VOL = 0.4V, VOH = 2.4V, w/loads
trs, tfs
tPLH
0.5
1.5
2
1.7
2.5
ns
ns
Input edge greater than 1V/ns
Input edge greater than 1V/ns
tPHL
1.9
2.5
ns
Notes:
1. Refers to transition on non-inverting output.
2. While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=t2/t1, were the cycle (t1) decreases
as the frequency goes up.
IDTTM/ICSTM DDR and SDRAM Buffer
ICS93718
REV E 02/11/07
ICS93718
DDR and SDRAM Buffer
300 mil SSOP
In Millimeters
c
N
In Inches
SYMBOL
COMMON DIMENSIONS
COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
0.635 BASIC
0.025 BASIC
α
h x 45°
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
D
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
VARIATIONS
D mm.
D (inch)
A1
N
MIN
15.75
MAX
16.00
MIN
.620
MAX
.630
- C -
48
e
SEATING
PLANE
b
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
.10 (.004) C
300 mil SSOP
Ordering Information
ICS93718yFLFT
Example:
ICS XXXX y F LF - T
Designation for tape and reel packaging
Lead Free (optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
IDTTM/ICSTM DDR and SDRAM Buffer
ICS93718
REV E 02/11/07
ICS93718
DDR and SDRAM Buffer
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Singapore (1997) Pte. Ltd.
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435 Orchard Road
#20-03 Wisma Atria
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TM
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