ICS94258YFT [IDT]
Processor Specific Clock Generator, 133.33MHz, PDSO48, 0.300 INCH, SSOP-48;
| 型号： | ICS94258YFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 133.33MHz, PDSO48, 0.300 INCH, SSOP-48 光电二极管 |
| 文件： | 总20页 (文件大小：348K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Incꢀ
ICS94258
Programmable System Clock Chip for PIII Processor
Recommended Application:
ALI 1644 style chipset
Pin Configuration
Output Features:
•
•
•
2 - CPU clocks (including 1 free running) @ 2.5V
13 - SDRAM @ 3.3V
7 - PCI (including 1 free running and 1 early selectable
free running) @ 3.3V
•
•
•
•
2 - AGP @ 3.3V
1 - IOAPIC 14.318MHz @ 2.5V
1 - 48MHz, @ 3.3V
1 - REF 14.318MHZ @ 3.3V, (selectable strength 1X or
2X) through I2C programming
Features:
•
•
•
•
•
Programmable ouput frequency
Programmable ouput rise/fall time
Programmable CPU, SDRAM, PCI and AGP skew
Real time system reset output
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread percentage
•
Watchdog timer technology to reset system
if over-clocking causes malfunction
Uses external 14.318MHz crystal
48-Pin 300mil SSOP & TSSOP
Notes:
•
REF0 can be 1X or 2X strength controlled by I2Cꢀ
Internal Pull-up Resistor of 120K to VDD
Skew Specifications:
*
•
•
•
•
•
•
•
CPU - CPU: <250ps
PCI - PCI: <500ps
SDRAM - SDRAM: <250ps
AGP - AGP: <500ps
PCI - AGP: <750ps
** Internal Pull-down of 120K to GND
1ꢀ This input has 2X drive strength
CPU - SDRAM:<350ps
CPU - PCI: <3ns
Block Diagram
Functionality
FS3
0
FS2
0
FS1
0
FS0
0
CPU SDRAM
66.66 66.66
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
66.66 100.00
100.00 66.66
100.00 100.00
100.00 133.33
133.33 66.66
133.33 100.00
133.33 133.33
1
0
0
0
66.66
66.66
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
66.66 100.00
100.00 66.66
100.00 100.00
100.00 133.33
133.33 66.66
133.33 100.00
133.33 133.33
Note: PCICLK = 33ꢀ33MHz ,AGP= 66ꢀ66MHz
94258 Rev B - 12/19/01
Third party brands and names are the property of their respective owners.
ICS94258
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
PWR
OUT
IN
DESCRIPTION
Power supply pins, nominal 2.5V
1, 45
VDDL
IOAPIC
X1
2
2.5V clock outputs
4
5
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
X2
OUT
3, 11, 16, 23, 29,
34, 41, 48
6, 8, 17, 21, 28,
35, 40
GND
PWR
PWR
Ground pins
VDD
Power supply pins, nominal 3.3V
FS02, 3
REF
FS12, 3
IN
Frequency select pin, 1X or 2X strength (default = 2X).
14.318 MHz reference clock.
7
OUT
IN
Frequency select pin.
9
AGP0
OUT
OUT
OUT
IN
AGP outputs defined as 2X PCI frequency. These may not be stopped.
AGP outputs defined as 2X PCI frequency. These may not be stopped.
Free running PCICLK not stoped by PCI_STOP#
Frequency select pin.
10
12
AGP1
PCICLK_F
FS21, 3
PCICLK2
OUT
PCI clock output
15
Real time system reset signal for frequency value or watchdog timmer
timeout. This signal is active low. Output is selectable via I2C Byte 5 bit7
RESET#
OUT
OUT
PCICLK
(1, 0)
PCICLK3
MODE1, 3
EPCICLK_F
PCICLK4
14, 13
18
PCI clock outputs.
OUT
IN
PCI clock output.
Function select pin, 1=Desktop Mode, 0=Mobile Mode.
Free running early PCI clock output (default)
PCI clock output.
OUT
OUT
19
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
(See MODE table for further information.)
PD#1
IN
20
PCICLK5
OUT
IN
PCI clock output. This pin is active when MODE = 0 (default)
Frequency select pin.
FS32, 3
48MHz
SCLK
22
24
OUT
IN
48MHz output clock.
Clock input of I2C input, 5V tolerant input
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
(See MODE table for further information.)
PD#1
IN
25
26
SDRAM12
OUT
IN
SDRAM clock output. This pin is active when MODE = 1.
This asynchronous input halts CPU clock at logic "0" level when driven low,
the stop selection can be programmed through I2C. This is activated when
MODE = 0 (default)
CPU_STOP#1
SDRAM11
OUT
IN
SDRAM clock output. This pin is active when MODE = 1.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low. This is activated when MODE = 0 (default)
SDRAM clock output. This pin is active when MODE = 1.
Selects EPCICLK_F This pin is active when MODE = 0 (default).
SDRAM clock output. This pin is active when MODE = 1.
PCI_STOP#1
27
30
SDRAM10
SELPCI_F
SDRAM9
OUT
IN
OUT
31, 32, 33, 36, 37,
38, 39, 42, 43
44
SDRAM ( 8:0 )
OUT
SDRAM clock outputs.
Data pin for I2C circuitry 5V tolerant
Free running CPU clock. Not affected by CPU_STOP#.
2.5V CPU clock.
SDATA
CPUCLK_F
CPUCLK
I/O
46
47
OUT
OUT
Notes:
1: Internal Pull-up Resistor of 120K to 3ꢀ3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-resetꢀ Use 10Kohm resistor
to program logic Hi to VDD or GND for logic lowꢀ
3: Internal Pull-down resistor of 120K to GND on indicated inputsꢀ
Third party brands and names are the property of their respective owners.
2
ICS94258
General Description
The ICS94258 is a main clock synthesizer chip for PIII based systems with ALI 1644 style chipsetꢀ This provides all clocks
required for such a systemꢀ
The ICS94258 belongs to ICS new generation of programmable system clock generatorsꢀ It employs serial programming I2C
interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring
output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocksꢀ
This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system
become unstable from over clockingꢀ
Mode Pin - Power Management Input Control
MODE, Pin 18
(Latched Input)
Pin 20
Pin 25
Pin 26
Pin 27
Pin 30
PCICLK5
(Output)
PD#
(Input)
CPU_STOP#
(Input)
PCI_STOP#
(Input)
SELPCI_F
(Input)
0
PD#
(Input)
SDRAM12
(Output)
SDRAM11
(Output)
SDRAM10
(Output)
SDRAM9
(Output)
1
Third party brands and names are the property of their respective owners.
3
ICS94258
General I2C serial interface information for the ICS94258
How to Write:
How to Read:
Controller (host) sends a start bitꢀ
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) will send start bitꢀ
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending Byte 0 through Byte 20
(see Note)
ICS clock sends Byte 0 through byte 8 (default)
ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 8)ꢀ
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
How to Write:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D3(H)
Address D2(H)
ACK
Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
If 7H has been written to B8
ACK
Byte 7
Byte 6
Byte 18
Byte 19
Byte 20
Stop Bit
ACK
ACK
ACK
If 12H has been written to B8
ACK
Byte18
Byte 19
Byte 20
If 13H has been written to B8
ACK
If 14H has been written to B8
ACK
Stop Bit
*See notes on the following pageꢀ
Third party brands and names are the property of their respective owners.
4
ICS94258
Brief I2C registers description for ICS94258
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Functionality & Frequency
Select Register
See individual
byte description
0
Active / inactive output control
registers/latch inputs read back.
See individual
byte description
Output Control Registers
1-6
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
Vendor ID & Revision ID
Registers
See individual
byte description
Writing to this register will configure
byte count and how many byte will be
read back. Do not write 00H to this byte.
Byte Count
Read Back Register
8
9
08H
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
Watchdog Timer
Count Register
10H
Watchdog enable, watchdog status and
programmable ’safe’frequency’can be
configured in this register.
Watchdog Control Registers 10 Bit [6:0]
000,0000
This bit select whether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
VCO Control Selection Bit
10 Bit [7]
0
These registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.
Depended on
hardware/byte 0
configuration
VCO Frequency Control
Registers
11-12
13-14
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
These registers control the spread
percentage amount.
Group Skews Control
Registers
Increment or decrement the group skew
amount as compared to the initial skew.
See individual
byte description
15-16
17-20
Output Rise/Fall Time
Select Registers
These registers will control the output
rise and fall time.
See individual
byte description
Notes:
1ꢀ
The ICS clock generator is a slave/receiver, I2C componentꢀ It can read back the data stored in the latches for
verificationꢀ Readback will support standard SMBUS controller protocolꢀ The number of bytes to readback is
defined by writing to byte 8ꢀ
2ꢀ
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a setꢀ If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiverꢀ
3ꢀ
4ꢀ
5ꢀ
6ꢀ
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3ꢀ3V logic levelsꢀ
The data byte format is 8 bit bytesꢀ
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controllerꢀ The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferredꢀ The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytesꢀ The data is loaded until a Stop sequence is issuedꢀ
7ꢀ
At power-on, all registers are set to a default condition, as shownꢀ
Third party brands and names are the property of their respective owners.
5
ICS94258
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
FS3 FS2 FS1 FS0
Bit2 Bit7 Bit6 Bit5 Bit4
CPUCLK SDRAM PCICLK AGP
Spread Precentage
(MHz)
(MHz)
(MHz)
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
35ꢀ00
35ꢀ00
35ꢀ00
35ꢀ00
35ꢀ00
35ꢀ00
35ꢀ00
35ꢀ00
36ꢀ66
36ꢀ66
36ꢀ66
36ꢀ66
36ꢀ66
36ꢀ66
36ꢀ66
36ꢀ66
(MHz)
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
69ꢀ99
69ꢀ99
69ꢀ99
69ꢀ99
69ꢀ99
69ꢀ99
69ꢀ99
69ꢀ99
73ꢀ33
73ꢀ33
73ꢀ33
73ꢀ33
73ꢀ33
73ꢀ33
73ꢀ33
73ꢀ33
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66ꢀ66
66ꢀ66
66ꢀ66
100ꢀ00
66ꢀ66
100ꢀ00
133ꢀ33
66ꢀ66
100ꢀ00
133ꢀ33
66ꢀ66
100ꢀ00
66ꢀ66
100ꢀ00
133ꢀ33
66ꢀ66
100ꢀ00
133ꢀ33
69ꢀ99
105ꢀ00
69ꢀ99
105ꢀ00
140ꢀ00
69ꢀ99
105ꢀ00
140ꢀ00
73ꢀ33
110ꢀ00
73ꢀ33
110ꢀ00
146ꢀ66
73ꢀ33
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
0 to -0ꢀ5% Down Spread
0 to -0ꢀ5% Down Spread
0 to -0ꢀ5% Down Spread
0 to -0ꢀ5% Down Spread
0 to -0ꢀ5% Down Spread
0 to -0ꢀ5% Down Spread
0 to -0ꢀ5% Down Spread
0 to -0ꢀ5% Down Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
+/- 0ꢀ25% Center Spread
100ꢀ00
100ꢀ00
100ꢀ00
133ꢀ33
133ꢀ33
133ꢀ33
66ꢀ66
66ꢀ66
100ꢀ00
100ꢀ00
100ꢀ00
133ꢀ33
133ꢀ33
133ꢀ33
69ꢀ99
Bit 2,
Bit 7:4
00000
Note1
69ꢀ99
105ꢀ00
105ꢀ00
105ꢀ00
140ꢀ00
140ꢀ00
140ꢀ00
73ꢀ33
73ꢀ33
110ꢀ00
110ꢀ00
110ꢀ00
146ꢀ66
146ꢀ66
146ꢀ66
110ꢀ00
146ꢀ66
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
Bit 3
Bit 1
Bit 0
0
0
0
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3ꢀ
The I2C readback of the power up default indicates the revision ID in bits 2, 7:4 as shownꢀ
Third party brands and names are the property of their respective owners.
6
ICS94258
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
MODE#
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PIN# PWD
DESCRIPTION
18
20
19
18
15
14
13
12
0
1
1
1
1
1
1
1
-
10
9
X
1
1
1
1
FS3#
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F
AGP1
AGP0
48MHz
IOAPIC
22
2
REF - 1X or 2X
default = 0 = 2X
Bit 2
7
0
Bit 1
Bit 0
46
47
1
1
CPUCLK_F
CPUCLK
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
SDRAM0
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
PWD
DESCRIPTION
43
42
39
38
37
36
33
32
1
1
1
1
1
1
1
1
X
X
X
1
FS0#
FS1#
FS2#
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
-
-
31
30
27
26
25
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
1
1
1
1
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Bit 7
Bit 6
15
-
1
1
1 = PCICLK2, 0 = RESET#
(Reserved)
SDRAM9/SELPCI_F
(default = 1 = SELPCI_F)
Bit 5
30
1
Bit 4
Bit 3
Bit 2
-
-
-
1
1
1
(Reserved)
(Reserved)
(Reserved)
Bit (1:0) = 00 CPU_STOP will
stop CPU clocks
Bit 1
Bit 0
-
-
0
0
Bit (1:0) = 01 CPU_STOP will
stop CPU, SDRAM, AGP clocks
Bit (1:0) = 10 CPU_STOP will
stop CPU, SDRAM clocks
Bit (1:0) = 11 CPU_STOP will
stop CPU, AGP clocks
Notes:
1ꢀ Inactive means outputs are held LOW and are disabled
from switchingꢀ
2ꢀ Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditionsꢀ
Third party brands and names are the property of their respective owners.
7
ICS94258
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
1
X
X
X
X
X
Vendor ID
Vendor ID
Vendor ID
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
Byte 9: Watchdog Timer Count Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
0=Hw/B0 freq / 1=B11 & 12 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
The decimal representation of these
8 bits correspond to how many
290ms the watchdog timer will wait
before it goes to alarm mode and
reset the frequency to the safe
setting. Default at power up is
16X 290ms = 4.64 seconds.
Note: FS values in bit (0:4) will correspond to Byte 0 FS
valuesꢀ Default safe frequency is same as 00000 entry in
byte0ꢀ
Byte 12: VCO Frequency Control Register
Byte 11: VCO Frequency Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit8
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCO Divider Bit7
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
Note: The decimal representation of these 9 bits (Byte 12
bit (7:0) & Byte 11 bit (7) ) + 8 is equal to the VCO divider
valueꢀ For example if VCO divider value of 36 is desired,
user need to program 36 - 8 = 28, namely, 0, 00011100 into
byte 12 bit & byte 11 bit 7ꢀ
Note: The decimal representation of these 7 bits
(Byte 11 (6:0)) + 2 is equal to the REF divider value ꢀ
Notes:
1ꢀ PWD = Power on Default
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8
ICS94258
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Spread Spectrum Bit7
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bi 9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrumꢀ
Incorrect spread percentage may cause system failureꢀ
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrumꢀ
Incorrect spread percentage may cause system failureꢀ
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
0
0
1
0
0
CPUCLK Skew Control
PCICLK (5:0, F) Skew Control
CPUCLK_F Skew Control
SDRAM0 Skew Control
AGP (1:0) Skew Control
SDRAM (12:1) Skew Control
Byte 17: Output Rise/Fall Time Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
CPUCLK Slew Rate Control
SDRAM0 Skew Control
CPUCLK_F Slew Rate Control
PCICLK_F Slew Rate Control
PCICLK (5:0) Slew Rate Control
SDRAM (12:1) Skew Control
AGP (1:0) Slew Rate Control
48MHz Slew Rate Control
Notes:
1ꢀ PWD = Power on Default
2ꢀ The power on default for byte 13-20 depends on the harware (latch inputs FS(4:0)) or I2C (Byte 0 bit (1:7)) settingꢀ Be sure
to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first passꢀ
3ꢀ If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up valueꢀ
Third party brands and names are the property of their respective owners.
9
ICS94258
Byte 19: Reserved Register
Byte 20: Reserved Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Byte 19 and 20 are reserved registers, these are
unused registers writing to these registers will not
affect device performance or functinalityꢀ
VCOProgrammingConstrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
UsefulFormula
VCOFrequency=14ꢀ31818xVCO/REFdividervalue
Phase Detector Stabiliy = 14ꢀ038 x (VCO divider value)-0ꢀ5
ToprogramtheVCOfrequencyforover-clocking*
0ꢀ Before trying to program our clock manually, consider using ICS provided software utilities for easy programmingꢀ
1ꢀ Select the frequency you want to over-clock from with the desire gear ratio (iꢀeꢀ CPU:SDRAM:3V66:PCI ratio) by writing to
byte 0, or using initial hardware power up frequencyꢀ
2ꢀWrite 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20)ꢀ
3ꢀ Read back byte 11-20 and copy values in these registersꢀ
4ꢀ Re-initialize the write sequenceꢀ
5ꢀ Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider valuesꢀ
6ꢀ Write to byte 13 to 20 with the values you copy from step 3ꢀ This maintains the output spread, skew and slew rateꢀ
7ꢀ The above procedure is only needed when changing the VCO for the 1st passꢀ If VCO frequency needed to be changed
again, user only needs to write to byte 11 and 12 unless the system is to rebootꢀ
Note:
1ꢀ User needs to ensure step 3 & 7 is carried outꢀ Systems with wrong spread percentage and/or group to group skew relation
programmed into bytes 13-16 could be unstableꢀ Step 3 & 7 assure the correct spread and skew relationshipꢀ
2ꢀ If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctlyꢀ
3ꢀ Follow min and max VCO frequency range providedꢀ Internal PLLcould be unstable if VCO frequency is too fast or too slowꢀ
Use 14ꢀ31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz)ꢀ
4ꢀ ICS recommends users, to utilize the software utility provided by ICSApplication Engineering to program theVCO frequencyꢀ
5ꢀ Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount desiredꢀ
See Application note for software supportꢀ
Third party brands and names are the property of their respective owners.
10
ICS94258
Absolute Maximum Ratings
Supply Voltage ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 5ꢀ5 V
Logic Inputs ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ GND 0ꢀ5 V to VDD +0ꢀ5 V
Ambient Operating Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 0°C to +70°C
Case Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 115°C
Storage Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the deviceꢀ These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not impliedꢀ Exposure to absolute maximum rating conditions for extended periods
may affect product reliabilityꢀ
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS
MIN
2
VSS-0.3
-5
TYP
MAX UNITS
VIH
VIL
IIH
VDD+0.3
V
V
0.8
5
VIN = VDD
mA
IIL1
IIL2
VIN = 0 V; Inputs with no pull-up resistors
-5
Input Low Current
mA
VIN = 0 V; Inputs with pull-up resistors
CL = 0; CPU=66 MHz, SDRAM=66 MHz
CL = 0; CPU=100 MHz, SDRAM=66, 100,
-200
101
120
125
150
IDD3.3OP
Operating Supply
Current
mA
mA
133 MHz
CPU=133 MHz, SDRAM=133 MHz
CL =0; CPU=66-133 MHz, SDRAM=100
140
11
175
70
IDD2.5OP
IDD3.3PD
CL = 0 pF; Input address to VDD or GND
Powerdown Current
Input Frequency
200
600
Fi
VDD = 3.3 V
14.32
MHz
pF
CIN
Logic Inputs
5
6
Input Capacitance1
Clk Stabilization1
COUT
CINX
Output pin capacitance
X1 & X2 pins
pF
27
45
pF
TSTAB
From VDD = 3.3 V to 1% target frequency
3
ms
tskCPU-SDR VT = 1.25 V/ VT = 1.5 V
tskCPU-PCI VT = 1.25 V/ VT = 1.5 V
tskAGP-PCI VT = 1.5 V
CPU to SDRAM
CPU to PCI
350
3
ps
ns
ps
1.2
AGP to PCI
750
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
ICS94258
Electrical Characteristics - CPU
TA = 0 - 70º C; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH2B
VOL2B
IOH2B
IOL2B
tr2B
CONDITIONS
MIN
2
TYP
2.3
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-27
V
mA
mA
ns
ns
%
-48
27
0.4
0.4
45
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.8
0.9
1.6
1.6
55
Fall Time1
Duty Cycle1
Skew1
tf2B
dt2B
49.1
133
207
tsk2B
VT = 1.25 V
175
250
ps
ps
Jitter, Cycle-to-cycle1
1Guaranteed by design, not 100% tested in production.
tjcyc-cyc2B VT = 1.25 V
Electrical Characteristics - AGP, PCI
TA = 0 - 70º C; VDD = 3.3 V +/-5%, CL = 40 pF for PCI0-1, CL = 10 - 30 pF for other PCIs
(unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
SYMBOL
VOH1
CONDITIONS
MIN
2.3
TYP
0.19
MAX UNITS
V
IOH = -1mA
IOL = 1 mA
VOL1
0.55
-33
V
VOH@MIN = 1 V
IOH1
Output High Current
mA
VOH@MAX = 3.135V
VOL@MIN = 1.95 V
VOL@MAX =0.4V
-33
30
68
24
IOL1
tr1
Output Low Current
Rise Time1
mA
ns
38
2
VOL = 0.4 V, VOH = 2.4 V
0.5
0.5
45
1.74
Fall Time1
Duty Cycle1
Skew1
tf1
dt1
VOL = 2.4 V, VOH = 0.4 V
VT = 1.5 V
1.9
50.9
150
166
168
2
ns
%
55
tsk1
VT = 1.5 V
300
250
500
ps
ps
ps
tjcyc-cyc1
PCI -- VT = 1.5 V
Jitter, cycle-to-cycle1
tjcyc-cyc1
AGP -- VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
ICS94258
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH3
VOL3
IOH3
IOL3
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
MAX UNITS
V
IOL = 23 mA
0.4
-46
V
mA
mA
ns
VOH = 2.0 V
VOL = 0.8V
54
0.4
0.4
45
tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.76
0.85
49.3
243
1.6
1.6
55
Fall Time1
tf3
ns
Duty Cycle1
dt3
%
VT = 1.5 V
VT = 1.5 V
Sdram 0:12
Sdram 0:9
tsk1
250
ps
Skew
tsk1
115
250
ps
VT = 1.5 V
VT = 1.5 V
Sdram 10:12
tsk1
dt3
213
49.3
203
250
55
ps
%
Duty Cycle1
Jitter, cycle-to-cycle1
45
tjcyc-cyc3
VT = 1.5 V
250
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH4B
VOL4B
IOH4B
IOL4B
tr4B
CONDITIONS
MIN
TYP
2.25
MAX UNITS
V
IOH = -12 mA
IOL =12mA
2
0.4
-21
V
mA
mA
ns
VOH = 1.7 V
-48
VOL= 0.7
V
19
0.4
0.4
45
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.96
0.95
53.8
324
1.6
1.6
55
Fall Time1
tf4B
ns
Duty Cycle1
Jitter, Cycle-to-cycle1
dt4B
%
tjcyc-cyc4B VT = 1.25 V
500
ps
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
13
ICS94258
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
VOL5
IOH5
CONDITIONS
MIN
2.4
TYP
2.75
MAX UNITS
V
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.4 V
0.4
-23
V
mA
mA
ns
-40.5
IOL5
29
45
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.8
1.8
2
2
Fall Time1
tf5
ns
Duty Cycle1
Jitter, cycle-to-cycle1
1Guaranteed by design, not 100% tested in production.
dt5
54.5
206
55
500
%
VT = 1.5 V
tjcyc-cyc5
ps
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
VOL5
IOH5
CONDITIONS
MIN
2.4
TYP
2.75
MAX UNITS
V
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.4 V
0.4
-23
V
mA
mA
ns
-40.5
IOL5
29
45
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.1
1.3
2
2
Fall Time1
tf5
ns
Duty Cycle1
Jitter, cycle-to-cycle1
1Guaranteed by design, not 100% tested in production.
dt5
54.5
428
55
%
tjcyc-cyc5
ps
VT = 1.5 V,
1000
Third party brands and names are the property of their respective owners.
14
ICS94258
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is usedꢀ With no jumper is installed
the pin will be pulled highꢀ With the jumper in place the pin
will be pulled lowꢀ If programmability is not necessary, than
only a single resistor is necessaryꢀThe programming resistors
should be located close to the series termination resistor to
minimize the current loop areaꢀ It is more important to locate
the series termination resistor close to the driver than the
programming resistorꢀ
The I/O pins designated by (input/output) serve as dual
signal functions to the deviceꢀ During initial power-up, they
act as input pinsꢀ The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latchꢀ At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output functionꢀ In
this mode the pins produce the specified buffered clocks to
external loadsꢀ
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potentialꢀ A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating periodꢀ
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
15
ICS94258
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94258ꢀ It is used to turn off the PCICLK clocks for low power operationꢀ
PCI_STOP# is synchronized by the ICS94258 internallyꢀ The minimum that the PCICLK clocks are enabled (PCI_STOP# high
pulse) is at least 10 PCICLK clocksꢀ PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteedꢀ
PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clockꢀ
Notes:
1ꢀ All timing is referenced to the Internal CPUCLK (defined as inside the ICS94258 deviceꢀ)
2ꢀ PCI_STOP# is an asynchronous input, and metastable conditions may existꢀ This signal is required to be synchronized
inside the ICS94258ꢀ
3ꢀ All other clocks continue to run undisturbedꢀ
4ꢀ CPU_STOP# is shown in a high (true) stateꢀ
Third party brands and names are the property of their respective owners.
16
ICS94258
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the partꢀ PD# is
an asynchronous active low inputꢀ This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizerꢀ
Internal clocks are not running after the device is put in power downꢀ When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystalꢀ The power up latency needs to be less than 3 mSꢀ The power down
latency should be as short as possible but conforming to the sequence requirements shown belowꢀ PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operationsꢀ The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possibleꢀ Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to completeꢀ
PD#
CPUCLK
PCICLK
VCO
Crystal
Notes:
1ꢀ All timing is referenced to the Internal CPUCLK (defined as inside the ICS94258 device)ꢀ
2ꢀ As shown, the outputs Stop Low on the next falling edge after PD# goes lowꢀ
3ꢀ PD# is an asynchronous input and metastable conditions may existꢀ This signal is synchronized inside this partꢀ
4ꢀ The shaded sections on the VCO and the Crystal signals indicate an active clockꢀ
5ꢀ Diagrams shown with respect to 133MHzꢀ Similar operation when CPU is 100MHzꢀ
Third party brands and names are the property of their respective owners.
17
ICS94258
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizerꢀ It is used to turn off the CPU clocks for low power operationꢀ
CPU_STOP# is synchronized by the ICS94258ꢀ The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocksꢀ All other clocks will continue to run while the CPU clocks are disabledꢀ The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulseꢀ CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocksꢀ
Notes:
1ꢀ All timing is referenced to the internal CPU clockꢀ
2ꢀ CPU_STOP# is an asynchronous input and metastable conditions may existꢀ This signal is synchronized
to the CPU clocks inside the ICS94258ꢀ
3ꢀ All other clocks continue to run undisturbedꢀ
Third party brands and names are the property of their respective owners.
18
ICS94258
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
h x 45°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
D mm.
- C -
D (inch)
N
e
SEATING
PLANE
MIN
15.75
MAX
16.00
MIN
.620
MAX
b
48
.630
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS94258yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
19
ICS94258
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
22
E1
e
6.00
6.20
.236
.244
D
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
α
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
MIN
12.40
MAX
12.60
MIN
.488
MAX
.496
e
SEATING
PLANE
b
48
Reference Doc.: JEDEC Publication 95, MO-153
aaa
C
10-0039
6ꢀ10 mmꢀ Body, 0ꢀ50 mmꢀ pitch TSSOP
(0ꢀ020 mil)
(240 mil)
Ordering Information
ICS94258yG-XX-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
20
相关型号：
ICS94258YG-XX-T-LF
Processor Specific Clock Generator, 133.33MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, TSSOP-48
IDT
ICS950201AFLF-T
200MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56, 0.300 INCH, GREEN, MO-118, SSOP-56
IDT
ICS950201AFLFT
Processor Specific Clock Generator, 200MHz, PDSO56, 0.300 INCH, GREEN, MO-118, SSOP-56
IDT
ICS950201AGLFT
Processor Specific Clock Generator, 200MHz, PDSO56, 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56
IDT
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