ICS951104YGLFT [IDT]
Processor Specific Clock Generator, 133.33MHz, PDSO56, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, TSSOP-56;
| 型号： | ICS951104YGLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 133.33MHz, PDSO56, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, TSSOP-56 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总20页 (文件大小：370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Programmable Timing Control HubTM for P4TM
Pin Configuration
Recommended Application:
ALI 1671/1672 P4 Chipset
AVCO_CORE
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
CLK_STOPB
GND
X1
X2
GND
VDD
3
4
5
6
7
8
9
Output Features:
•
•
•
•
•
•
2 - Pairs of differential CPU clocks (differential current mode)
2 - AGP @ 3.3V
7 - PCI @ 3.3V
1 - 48MHz @ 3.3V fixed
1 - REF @ 3.3V, 14.318MHz
50M/REF_SEL_REF0
REF1
VDD
FS0_REF2
GND
DDRT0
DDRC0
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
REF3_PLL_50
GND
FS1/PCICLK0
FS2/PCICLK9
SSEN_PCICLK1
PCICLK2
7 - Pairs of differential SSTL2 DDR @ 2.5V
VDDL
DDRT1
DDRC1
DDRT2
DDRC2
VDDL
Features/Benefits:
•
•
•
•
•
•
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
GND
VDD
PCICLK3
PCICLK4
GND
DDRT3
DDRC3
DDRT4
DDRC4
GND
Programmable output skew.
PCICLK5
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
PCI_STOPB
SDA
VDD
FS3/AGP0
GND
VDDL
•
•
•
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write operations.
Uses external 14.318MHz crystal.
DDRT5
DDRC5
PWRGD_PDB
SCL
AGP1
AGP2
AGP3
Key Specifications:
56-Pin 300-mil SSOP, 240-mil TSSOP
1 These outputs have 2x drive strength
* Internal Pull-up resistor of 120K to VDD
** These inputs have 120K internal pull-down
to GND
•
•
•
•
•
CPU Output Jitter <150ps
AGP Output Jitter <250ps
DDR Output Jitter <250ps
CPU - DDR Skew <250ps
CPU - AGP/PCI Skew = 2.5ns 500ps
Functionality
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2 FS1 FS0
CPU DDR AGP
66.66 66.66 66.66
66.66 100.00 66.66
100.00 66.66 66.66
100.00 100.00 66.66
100.00 133.33 66.66
133.33 66.66 66.66
133.33 100.00 66.66
133.33 133.33 66.66
66.66 66.66 66.66
66.66 100.00 66.66
100.00 66.66 66.66
100.00 100.00 66.66
100.00 133.33 66.66
133.33 66.66 66.66
133.33 100.00 66.66
133.33 133.33 66.66
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Block Diagram
PLL2
48MHz
REF0
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
CPUCLKT (1:0)
CPUCLKC (1:0)
CPU
DIVDER
2
Stop
Stop
2
PCI
DIVDER
PCICLK (5:0)
PCICLK_E
7
PD#
MULTSEL
FS (3:0)
Control
Logic
AGP
DIVDER
SDATA
Stop
Stop
AGP (1:0)
2
SCLK
Vtt_PWRGD
CLK_STOP#
PCI_STOP#
DDRC (6:0)
DDRT (6:0)
DDR
DIVDER
7
Config.
Reg.
7
Host Swing Select Functions
RESET#
I REF
Reference R,
Board Target
Output
Current
MULTISEL0
Iref =
Voh @ Z
Trace/Term Z
V
DD/(3*Rr)
Rr = 221 1%,
Iref = 5.00mA
0
1
50 ohms
Ioh = 4* I REF 1.0V @ 50
Ioh = 6* I REF 0.7V @ 50
Rr = 475 1%,
Iref = 2.32mA
50 ohms
0485G—10/13/05
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
changewithoutnotice.
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
General Description
The ICS951104 is a single chip clock solution for desktop designs using the ALI 1671/1672 P4 Chipset. It provides all
necessary clock signals for such a system.
The ICS951104 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
AVDD_CORE
PWR Analog core supply 3.3V
PWR 3.3V power supply.
5, 8, 17, 54
VDD
X1
2
3
IN
Crystal input, has internal load cap (33pF) and feedback resistor from X2.
Crystal output, nominally 14.318MHz. Has internal load cap (33pF).
X2
OUT
4, 11, 16, 25, 34, 39,
46, 49, 50
GND
PWR Ground pins for 3.3V supply.
MULTSEL
REF0
IN
3.3V LVTTL input for selecting the current multiplier for CPU outputs
3.3V, 14.318MHz reference clock output.
6
7
OUT
Real time system reset signal for frequency value or watchdog timmer timeout. This
signal is active low.
RESET#
OUT
FS0
IN
Logic input frequency select bit. Input latched at power on.
3.3V clock outputs
9
AGP0
AGP1
OUT
OUT
10
3.3V clock outputs
PCICLK_E
FS1
OUT
IN
3.3V Early PCI clock output.
12
13
Logic input frequency select bit. Input latched at power on.
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock output.
FS2
IN
PCICLK0
OUT
20 , 19, 18,
15, 14
PCICLK (5:1)
PCI_STOP#
Vtt_PWRGD
PD#
OUT
IN
3.3V PCI clock outputs.
Stops all PCICLKs at logic 0 level, when input low besides the PCICLK_F clocks
which are controllable by I2C bits whether they are free running or stopped by
PCI_STOP.
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (3:0)
inputs are valid and are ready to be sampled (active high).
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
21
IN
22
IN
23
24
AVDD48
FS3
PWR Analog power for 48MHz output 3.3V.
IN
Logic input frequency select bit. Input latched at power on.
48MHz
OUT
3.3V Fixed 48MHz clock output
26
27
SDATA
SCLK
IN
Data pin for I2C circuitry 5V tolerant.
Clock pin for I2C circuitry 5V tolerant.
I/O
This asynchronous input halts CPU, AGP or DDR clocks at logic "0" level when
driven low. These stops are configurable via IIC.
28
CLK_STOP#
DDRC (6:0)
IN
o
29, 31, 35, 37, 41,
43, 47
30, 32, 36, 38, 42,
44, 48
OUT
OUT
"Complementory" clocks of differential pair DDRC outputs.
"True" clocks of differential pair DDRT outputs.
DDRT (6:0)
VDDL
33, 40, 45
PWR Power supply for 2.5V
This pin establishes the reference current for the CPUCLK pairs. This pin requires a
51
I REF
OUT
OUT
OUT
fixed precision resistor tied to ground in order to establish the appropriate current.
"True" clocks of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
"Complementory" clocks of differential pair CPU outputs. These are current outputs
and external resistors are required for voltage bias.
53, 56
52, 55
CPUCLKT (1:0)
CPUCLKC (1:0)
0485G—10/13/05
2
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
General I2C serial interface information
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
*See notes on the following page.
0485G—10/13/05
3
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
FS3 FS2 FS1 FS0 CPUCLK
DDR
(MHz)
66.66
100.00
66.66
100.00
133.33
66.66
100.00
133.33
66.66
100.00
66.66
100.00
133.33
66.66
100.00
133.33
70.00
AGP
PCICLK
Spread Precentage
(MHz)
Bit2 Bit7 Bit6 Bit5 Bit4
(MHz)
66.66
(MHz)
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
70.00
62.50
70.00
70.00
70.00
71.43
70.00
70.00
33.33
73.33
73.33
73.33
73.33
73.33
73.33
73.33
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
35.00
31.25
35.00
35.00
35.00
35.72
35.00
35.00
66.65
36.66
36.66
36.66
36.66
36.66
36.66
36.66
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
Spread Off
66.66
100.00
100.00
100.00
133.33
133.33
133.33
66.66
66.66
100.00
100.00
100.00
133.33
133.33
133.33
70.00
Bit 2,
Bit 7:4
00000
Note1
100.00
105.00
105.00
105.00
100.00
140.00
140.00
133.30
73.33
166.67
70.00
105.00
140.00
166.67
105.00
140.00
166.60
110.00
73.33
110.00
146.66
73.33
110.00
146.66
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
110.00
110.00
110.00
146.66
146.66
146.66
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Bit 3
Bit 1
Bit 0
0
0
0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The I2C readback of the power up default indicates the revision ID in bits 2, 7:4 as shown.
0485G—10/13/05
4
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
-
53, 52
56, 55
PWD
Description
Bit7
Bit6
Bit5
X
1
1
MULT_SEL (readback)
CPUT/C1
CPUT/C0
PCICLK_5 drive strength control
1 = 2X, 0 = 1X
Bit4
20
1
Bit3
Bit2
Bit1
Bit0
-
-
-
-
X
X
X
X
FS3 Read back
FS2 Read back
FS1 Read back
FS0 Read back
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
PWD
Description
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
12
1
PCICLK_E
PCICLK_5
20
1
19
18
15
14
13
1
1
1
1
1
PCICLK_4
PCICLK_3
PCICLK_2
PCICLK_1
PCICLK_0
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
24
48, 47
-
PWD
Description
Bit7
Bit6
Bit5
1
1
1
48MHZ
DDRT/C0
Reset gear shift detect 1 = Enable, 0 = Disable
42, 41,
44, 43
36, 35,
38, 37
30, 29,
32, 31
10
Bit4
Bit3
Bit2
1
1
1
DDRT/C (2:1)
DDRT/C (4:3)
DDRT/C (6:5)
Bit1
Bit0
1
1
AGP1
AGP0
9
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
-
-
-
-
0
0
0
0
CPUT/C0 Stop via CLK_STOP enable bit, 0 = Free Run; 1 = Stoppable
CPUT/C1 Stop via CLK_STOP enable bit, 0 = Free Run; 1 = Stoppable
AGP0 Stop via CLK_STOP enable bit, 0 = Free Run; 1 = Stoppable
AGP1 Stop via CLK_STOP enable bit, 0 = Free Run; 1 = Stoppable
DDRT/C(6:0) Stop via CLK_STOP enable bit, 0 = Free Run; 1 =
Stoppable
Bit 3
-
0
Bit 2
Bit 1
Bit 0
-
-
-
0
0
0
DDRT/C0 Stop via CLK_STOP enable bit, 0 = Free Run; 1 = Stoppable
CPUCLKT1 PD# STOP polarity control, 0 = Stop High; 1 = Stop Low
CPUCLKT0 PD# STOP polarity control, 0 = Stop High; 1 = Stop Low
0485G—10/13/05
5
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Bit
Pin#
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
0
PCICLK_E STOP via PCI_STOP enable bit, 0 = Free Run; 1 = Stoppable
X
0
PCICLK5 STOP via PCI_STOP enable bit, 0 = Free Run; 1 = Stoppable
X
X
X
X
X
0
0
0
0
0
PCICLK4 STOP via PCI_STOP enable bit, 0 = Free Run; 1 = Stoppable
PCICLK3 STOP via PCI_STOP enable bit, 0 = Free Run; 1 = Stoppable
PCICLK2 STOP via PCI_STOP enable bit, 0 = Free Run; 1 = Stoppable
PCICLK1 STOP via PCI_STOP enable bit, 0 = Free Run; 1 = Stoppable
PCICLK0 STOP via PCI_STOP enable bit, 0 = Free Run; 1 = Stoppable
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision ID Bit3
Revision ID Bit2
Revision ID Bit1
Revision ID Bit0
Vendor ID Bit3
Vendor ID Bit2
Vendor ID Bit1
Vendor ID Bit0
X
X
X
X
0
0
0
1
Revision ID values will be based on individual device's revision
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 7: Revision ID and Device ID Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Device ID7
Device ID6
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
0
0
1
0
0
0
1
0
Device ID values will be based on individual device
"22H" in this case.
Byte 8: Byte Count Read Back Register
Bit
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
1
1
1
Note: Writing to this register will configure byte count and how
many bytes will be read back, default is 0FH = 15 bytes.
0485G—10/13/05
6
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Byte 9: Watchdog Timer Count Register
Bit
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
The decimal representation of these 8 bits correspond to X •
290ms the watchdog timer will wait before it goes to alarm mode
and reset the frequency to the safe setting. Default at power up is
8 • 290ms = 2.3 seconds.
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit
Name
PWD
Description
Programming Enable bit
Program
Enable
Bit 7
0
0 = no programming. Frequencies are selected by HW latches or Byte0 1
= enable all I2C programing.
Watchdog Enable bit.
This bit will over write WDEN latched value. 0 = disable, 1 = Enable.
Bit 6
WD Enable
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WD Alarm
SF4
0
0
0
0
0
0
Watchdog Alarm Status 0 = normal 1= alarm status
SF3
SF2
SF1
SF0
Watchdog safe frequency bits. Writing to these bits will configure the safe
frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the
reference divider value. Default at power up is equal to the
latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of Ndiv (8:0) correspond to the
VCO divider value. Default at power up is equal to the
latched inputs selecton. Notice Ndiv 8 is located in Byte 11.
0485G—10/13/05
7
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Byte 13: Spread Spectrum Control Register
Bit
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The Spread Spectrum (12:0) (or, see Byte 14) bit will program
the spread precentage. Spread precent needs to be calculated
based on the VCO frequency, spreading profile, spreading
amount and spread frequency. It is recommended to use ICS
software for spread programming. Default power on is latched FS
divider.
Byte 14: Spread Spectrum Control Register
Bit
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Name
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DDRC Div 3
DDRC Div 2
DDRC Div 1
DDRC Div 0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
DDRC clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
CPUCLK1 clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit
Name
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DDRT Div 3
DDRT Div 2
DDRT Div 1
DDRT Div 0
AGP Div 3
AGP Div 2
AGP Div 1
AGP Div 0
DDRT clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
AGP clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
0485G—10/13/05
8
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Byte 17: Output Divider Control Register
Bit
Name
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCI_INV
3V66_INV
Reserved
CPU_INV
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
PCICLK Phase Inversion bit
3V66 Phase Inversion bit
Reserved
CPUCLK Phase Inversion bit
PCI clock divider ratio can be configured via these 4 bits
individually. For divider selection table refer to Table 2. Default at
power up is latched FS divider.
Table 1
Table 2
Div (3:2)
Div (3:2)
00
01
10
11
00
01
10
11
Div (1:0)
Div (1:0)
00
01
10
11
/4
/3
/5
/9
/8
/6
/16
/12
/20
/36
/32
/24
/40
/72
00
01
10
11
/2
/3
/5
/7
/4
/6
/8
/16
/24
/40
/56
/12
/20
/28
/10
/18
/10
/14
Byte 18: Group Skew Control Register
Bit
Name
PWD
Programming Sequence
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
0
0
0
1
0
0
1
1
1
0
1 0
0
1 0
1 0
0
0
0
0
0
1
0ps Reserved
150ps Reserved
300ps Reserved
450ps Reserved
600ps Reserved
These 4bits control
CPU-DDRC (6:0)
0
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1 0 750ps Reserved
These 4 bits control all
clocks to CPUT/C (1:0)
1
1
900ps Reserved
Reserved
Reserved
Byte 19: Group Skew Control Register
Bit
Name
PWD
CPU-DDR
CPU-AGP
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
0
0
0
1
0 0 0 0 0ps 0 0 0 0 1.85ns 1 0 0 0 3.05ns
1 0 0 150ps 0 0 0 1 2.00ns 1 0 0 1 3.20ns
1 0 0 0 300ps 0 0 1 0 2.15ns 1 0 1 0 3.35ns
1 1 0 0 450ps 0 0 1 1 2.30ns 1 0 1 1 3.50ns
1 1 0 1 600ps 0 1 0 0 2.45ns 1 1 0 0 3.65ns
1 1 1 0 750ps 0 1 0 1 2.60ns 1 1 0 1 3.80ns
0
These 4bits control
CPU-DDRT (6:0)
Bit 2
Bit 1
Bit 0
1
0
1
These 4 bits control
CPU-AGP(1:0)
1 1 1 1 900ps 0 1 1 0 2.75ns 1 1 1 0 3.95ns
Reserved
0 1 1 1 2.90ns 1 1 1 1 4.10ns
0485G—10/13/05
9
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Byte 20: Group Skew Control Register
Bit
Name
PWD
CPU-PCI_E
CPU-PCI
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
0
0
0
1
0 0 0 0 0ps 0 0 0 0 1.85ns 1 0 0 0 3.05ns
1 0 0 150ps 0 0 0 1 2.00ns 1 0 0 1 3.20ns
1 0 0 0 300ps 0 0 1 0 2.15ns 1 0 1 0 3.35ns
1 1 0 0 450ps 0 0 1 1 2.30ns 1 0 1 1 3.50ns
1 1 0 1 600ps 0 1 0 0 2.45ns 1 1 0 0 3.65ns
1 1 1 0 750ps 0 1 0 1 2.60ns 1 1 0 1 3.80ns
0
These 4bits control
CPU-PCI(6:0)
Bit 2
Bit 1
Bit 0
0
0
0
These 4 bits control
CPU-PCI_E
1 1 1 1 900ps 0 1 1 0 2.75ns 1 1 1 0 3.95ns
Reserved
0 1 1 1 2.90ns 1 1 1 1 4.10ns
Byte 21: Slew Rate Control Register
Bit
Name
PWD
Strength Select
Bit 7
Bit 6
1
0
Clock slew rate control bits.
01 = strong: 11 = 00 medium: 10 = weak
REF0
Select
1X = 1: 2X = 0
Bit 5
REF0
1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
X
1
Reserved
Clock slew rate control bits.
01 = strong: 11 = 00 medium: 10 = weak
AGP(1:0)
Reserved
0
X
X
Reserved
Byte 22: Slew Rate Control Register
Bit
Name
PWD
Strength Select
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
Clock slew rate control bits.
01 = strong: 11 = 00 medium: 10 = weak
PCI_E
Clock slew rate control bits.
01 = strong: 11 = 00 medium: 10 = weak
PCI5
Clock slew rate control bits.
01 = strong: 11 = 00 medium: 10 = weak
PCI(4:2)
PCI(1:0)
Clock slew rate control bits.
01 = strong: 11 = 00 medium: 10 = weak
Byte 23: Slew Rate Control Register
Bit
Name
PWD
Strength Select
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
1
Reserved
Reserved
Reserved
Reserved
48MHz
Reserved
Reserved
Clock slew rate control bits.
01 = strong: 11 = 00 medium: 10 = weak
0
0485G—10/13/05
10
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%
PARAMETER
SYMBOL
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
V
IH
V
VSS-0.3
-5
V
IL
IIH
IIL1
IIL2
V = VDD
5
mA
mA
mA
mA
mA
mA
mA
MHz
nH
IN
V = 0 V; Inputs with no pull-up resistors
-5
IN
V = 0 V; Inputs with pull-up resistors
-200
IN
CL = 0 pF; Select @ 66M
CL = Full load
IREF=2.32
100
280
20
Operating
IDD3.3OP
IDD3.3PD
Supply Current
Power Down
Supply Current
IREF= 5mA
37
Input frequency
Pin Inductance
Fi
Lpin
CIN
Cout
CINX
Ttrans
Ts
VDD = 3.3 V;
7
5
Logic Inputs
pF
Input Capacitance1
Out put pin capacitance
6
pF
X1 & X2 pins
27
45
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
output enable delay(all outputs)
output disable delay (all outputs)
mS
mS
mS
nS
3
TSTAB
3
tPZH,tPZH
tPLZ,tPZH
1
1
10
10
Delay
nS
1Guarenteed by design, not 100% tested in production.
0485G—10/13/05
11
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Electrical Characteristics - CPUCLKT/C
TA = 0 - 70º C; VDD = 3.3 V +/-5%; (unless otherwise stated)
PARAMETER
SYMBOL
ZO
CONDITIONS
MIN TYP
3000
MAX UNITS
W
Current Source Output
Impedance
VO = VX
Output High Voltage
Output High Current
Rise Time1
VOH
IOH
tr
0.71
-13.9
1.2
V
mA
ps
%
VR = 475W +1%; IREF = 2.32mA; IOH = 6*IREF
VOL = 20%, VOH = 80%
Note 3
175
600
55
Differential Crossover Voltage1
Duty Cycle1
VX
dt
45
45
50
51
VT = 50%
55
%
Skew1, CPU to CPU
tsk
VT = 50%
100
150
ps
ps
Jitter, Cycle-to-cycle1
tjcyc-cyc VT = VX
Notes:
1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
F01
CONDITIONS
MIN
TYP
33.33
MAX
UNITS
MHz
W
1
RDSN1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
55
VOH1
VOL1
IOH1
IOL1
2.4
V
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
mA
mA
ns
1
tr1
0.5
0.5
45
2.5
2.5
55
1
Fall Time
tf1
ns
1
Duty Cycle
dt1
%
1
Skew
tsk1
VT = 1.5 V
150
350
200
3.5
ps
1
Jitter PCI (5:0)
Jitter PCI_E
tjcyc-cyc
VT = 1.5 V
ps
tCYC-CYC VT = 1.5V
tSK VT = 1.5V
ps
Skew PCI_E-PCI (5:0)
1
3.2
ns
1Guarenteed by design, not 100% tested in production.
0485G—10/13/05
12
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Electrical Characteristics - DDRT/C
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH3
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
MAX
UNITS
V
VOL3
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
20-80
0.4
-54
V
IOH3
mA
mA
ps
IOL3
41
450
450
45
1
Tr3
1200
1200
55
1
Fall Time
Tf3
80-20
ps
1
Duty Cycle
Jitter
Dt3
VT = 1.5 V
VT
%
150
150
ps
Skew1
Tsk1
VT = 1.5 V
ps
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-30 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
66.66
MAX
UNITS
MHz
W
1
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
55
VOH1
VOL1
IOH1
IOL1
2.4
V
0.4
-33
38
2
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
mA
mA
ns
1
tr1
0.5
0.5
45
1
Fall Time
tf1
2
ns
1
Duty Cycle
dt1
55
100
450
%
1
Skew
tsk1
VT = 1.5 V
ps
tjcyc-cyc1
VT = 1.5 V
Jitter
ps
1Guarenteed by design, not 100% tested in production.
0485G—10/13/05
13
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
48
MAX
55
UNITS
MHz
W
1
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
FO
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-23
27
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
-29
29
mA
mA
Output Low Current
VCH 48 USB
Rise Time
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1.5
1.5
ns
ns
VCH 48 USB
Fall Time
tf1
1
Duty Cycle
dt1
VT = 1.5 V
VT = 1.5 V
45
55
%
1
tjcyc-cyc
Jitter
350
ps
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
MAX UNITS
MHz
1
RDSP1
VO = VDD*(0.5)
20
60
W
V
1
VOH
IOH = -1 mA
2.4
1
VOL
IOL = 1 mA
0.4
-23
27
2
V
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
-29
29
mA
mA
ns
ns
%
IOH
1
IOL
1
tr1
1
Fall Time
tf1
2
1
Duty Cycle
dt1
VT = 1.5 V
VT = 1.5 V
45
55
1
tjcyc-cyc
Jitter
1000
ps
1Guaranteed by design, not 100% tested in production.
0485G—10/13/05
14
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0485G—10/13/05
15
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
Tsu 10ns min
PCI_F
PCI
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition. When the I2C Bit 6 of Byte 1 is programmed to '0' the final
state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive current values.
The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not be driven . When the
I2C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU and CPU# outputs will not
be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUCLKT
CPUCLKC
0485G—10/13/05
16
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
CPU_STOP# - De-assertion (transition from logic "0" to logic "1")
All CPU outputs that were stopped are to resume normal operation in a glitch free manner.The maximum latency from the de-
assertion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the I2C Bit 6 of Byte
1 is programmed to "1" then the stopped CPU outputs will be driven High within 3 nS of CPU_Stop# de-assertion.
De-assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUCLKT(2:0)
Tdrive_CPU_STOP# <10ns @ 200mV
*CPUCLKT(2:0)TS
CPUCLKC(2:0)
*Signal TS is CPUCLKT in Tri-State mode
PD# - Assertion (transition from logic "1" to logic "0")
When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks
must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must be
held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both CPU and
CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and description is
applicable for all valid CPU frequencies 66, 100, 133, 200 MHz.
Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one
clock cycle to complete.
Power Down Assertion of Waveforms
2 CPU Clock Latency
1.8ms Typical
CPUCLKT
CPUCLKC
DDRT
DDRC
AGP
PCI
48MHz
PD#
0485G—10/13/05
17
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
1
2
10.03
7.40
10.68
7.60
.395
.291
.420
.299
a
hh xx 4455°°
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- C --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
18.31
MAX
18.55
MIN
.720
MAX
b
56
.730
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS951104yFLFT
Example:
ICS XXXXXX y F LF - T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0485G—10/13/05
18
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
c
N
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
In Inches
L
SYMBOL
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
SEE VARIATIONS
0.319 BASIC
.236
MAX
.047
.006
.041
.011
.008
E1
E
A
A1
A2
b
c
D
E
E1
e
INDEX
AREA
1
2
SEE VARIATIONS
8.10 BASIC
6.00
a
D
6.20
.244
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.030
N
α
aaa
SEE VARIATIONS
SEE VARIATIONS
A
0°
--
8°
0.10
0°
--
8°
.004
A2
A1
- CC -
VARIATIONS
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
13.90
MAX
14.10
MIN
.547
MAX
.555
b
56
aaa
C
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
6.10 mm. Body, 0.50 mm. pitch TSSOP
(20 mil)
(240 mil)
Ordering Information
ICS951104yGLFT
Example:
ICS XXXXXX y G LF - T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0485G—10/13/05
19
Integrated
Circuit
Systems, Inc.
ICS951104
Preliminary Product Preview
Revision History
Rev.
Issue Date Description
Page #
G
10/13/2005 Added LF to Ordering Information
18-19
0485G—10/13/05
20
相关型号：
ICS951104YGT
Processor Specific Clock Generator, 133.33MHz, PDSO56, 6.10 MM, 0.50 MM PITCH, TSSOP-56
IDT
ICS951402AGLF
Processor Specific Clock Generator, 210MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-48
IDT
ICS951402AGLF-T
Processor Specific Clock Generator, 210MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-48
IDT
ICS951402YG-T
Processor Specific Clock Generator, 210MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
IDT
ICS951402YGLFT
210MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
IDT
©2020 ICPDF网 联系我们和版权申明