ICS951402AGLF [IDT]
Processor Specific Clock Generator, 210MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-48;
| 型号： | ICS951402AGLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 210MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总23页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
Programmable Timing Control Hub™ for P4™ processor
Recommended Application:
ATI chipset, P4 system, Banias system
Output Features:
Pin Configuration
VDDREF 1
48 VDDSDR
47 SDRAM_OUT
46 GNDSDR
45 CPU_STOP#*
44 CPUCLKT1
43 CPUCLKC1
42 VDDCPU
41 GNDCPU
40 CPUCLKT0
39 CPUCLKC0
38 IREF
FS0/REF0 2
FS1/REF1 3
FS2/REF2 4
GNDREF 5
•
2 - Pairs of differential CPUCLKs (differential current mode)
•
•
1 - SDRAM @ 3.3V
8 - PCI @3.3V (selectable 33/66 MHz) (2 free-running)
X1 6
X2 7
GND 8
VDD 9
•
•
•
2 - AGP @ 3.3V
2- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
*VttPWR_GD/PD# 10
PCI66/33#_SEL 11
PCI_STOP#* 12
VDDPCI 13
37 GND
36 AVDD
FS3/PCICLK_F0 14
FS4/PCICLK_F1 15
PCICLK0 16
PCICLK1 17
GNDPCI 18
35 SCLK
34 SDATA
•
3- REF @3.3V, 14.318MHz.
33 GNDAGP
32 AGPCLK0
31 AGPCLK1
30 VDDAGP
29 AVDD48
28 48MHz_0
27 48MHz_1
26 24_48MHz/SEL24_48#MHz**
Features/Benefits:
•
•
Support for Intel Banias power management features
Programmable output frequency, divider ratios, output rise/
falltime, output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
VDDPCI 19
PCICLK2 20
PCICLK3 21
PCICLK4 22
PCICLK5 23
GNDPCI 24
•
•
GND48
25
•
•
Programmable watch dog safe frequency.
48-Pin TSSOP & SSOP
Support I2C Index read/write and block read/write
operations.
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
•
Supports spread spectrum for EMI reduction; default is
spread spectrum ON.
Block Diagram
Skew Requirements
PCI-PCI
< 350ps
< 350ps
< 500ps
PLL2
48MHz (0:1)
24_48MHz
AGP-AGP
CPU-AGP
CPU-PCI
/ 2
< 500ps
< 1ns
X1
X2
XTAL
OSC
REF (2:0)
3
AGP-PCI
AGP leading
CPU-SDRAM
PLL1
Spread
Spectrum
CPU
DIVDER
CPUCLKT (1:0)
CPUCLKC (1:0)
< 1ns
Stop
2
2
SDRAM
SDRAM_OUT
SDATA
SCLK
FS (4:0)
1
6
Control
Logic
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
PCI
DIVDER
Stop
PCICLK (5:0)
PCICLK_F (1:0)
AGP (1:0)
PD#
PCI_STOP#
CPU_STOP#
PD#/Vtt_PWRGD
PCI66/33#SEL
24_48SEL#
2
2
Config.
Reg.
AGP
DIVDER
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
VDDREF = Xtal, REF
I REF
0660—05/05/05
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
Pin Description
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
2
3
4
5
6
7
8
9
VDDREF
FS0/REF0
FS1/REF1
FS2/REF2
GNDREF
X1
X2
GND
VDD
PWR Ref, XTAL power supply, nominal 3.3V
I/O
I/O
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
PWR Ground pin for the REF outputs.
IN Crystal input, Nominally 14.318MHz.
OUT Crystal output, Nominally 14.318MHz
PWR Ground pin.
PWR Power supply, nominal 3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active high input. / Asynchronous active low input pin used to power
10
*VttPWR_GD/PD#
IN
down the device into a low power state.
Selects all PCI clock frequencies to be 33Mhz or 66Mhz. 0 = 33Mhz , 1
= 66Mhz
11
12
PCI66/33#_SEL
PCI_STOP#*
IN
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
input low
IN
13
14
15
16
17
18
19
20
21
22
23
24
25
VDDPCI
FS3/PCICLK_F0
FS4/PCICLK_F1
PCICLK0
PWR Power supply for PCI clocks, nominal 3.3V
I/O
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
OUT PCI clock output.
OUT PCI clock output.
PWR Ground pin for the PCI outputs
PWR Power supply for PCI clocks, nominal 3.3V
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
PWR Ground pin for the PCI outputs
PWR Ground pin for the 48MHz outputs
PCICLK1
GNDPCI
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
GND48
24/48MHz clock output / Latched select input for 24/48MHz output.
0=48MHz, 1 = 24MHz.
26
24_48MHz/SEL24_48#MHz**
I/O
27
28
29
30
31
32
33
34
35
36
37
48MHz_1
48MHz_0
AVDD48
VDDAGP
AGPCLK1
AGPCLK0
GNDAGP
SDATA
OUT 48MHz clock output.
OUT 48MHz clock output.
PWR Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V
PWR Power supply for AGP clocks, nominal 3.3V
OUT AGP clock output
OUT AGP clock output
PWR Ground pin for the AGP outputs
I/O
IN
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
SCLK
AVDD
GND
PWR 3.3V Analog Power pin for Core PLL
PWR Ground pin.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
38
IREF
OUT
standard value.
Complementary clock of differential pair CPU outputs. This clock is 180
degrees out of phase with the SDRAM clock.
39
40
CPUCLKC0
CPUCLKT0
OUT
True clock of differential pair CPU outputs. This clock is in phase with
the SDRAM clock
OUT
41
42
GNDCPU
VDDCPU
PWR Ground pin for the CPU outputs
PWR Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. This clock is 180
degrees out of phase with the SDRAM clock.
43
44
CPUCLKC1
CPUCLKT1
OUT
True clock of differential pair CPU outputs. This clock is in phase with
the SDRAM clock
OUT
45
46
47
48
CPU_STOP#*
GNDSDR
SDRAM_OUT
VDDSDR
IN
Stops all CPUCLK besides the free running clocks
PWR Ground pin for the SDRAM outputs.
OUT SDRAM seed clock output for external buffer
PWR Supply for SDRAM clocks, nominal 3.3V.
0660—05/05/05
2
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
Table 1: Clock Power Management Truth Table
Stoppable
CPU
(Not free-run)
Non-stop
CPU
(Free-run)
Byte 6
Bit 6
Byte 6
Bit 7
CPU_
STOP
PD#
Note
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
IREF x 2
IREF x 2
IREF x 6
RUN
Hi Z
Hi Z
Hi Z
RUN
Hi Z
Hi Z
IREFx6
RUN
Hi Z
Hi Z
HI Z
IREF x 2
IREF x 2
RUN
Non
Tri-state
Mode
RUN
IREF x 2
IREF x 2
RUN
RUN
Hi Z
Hi Z
RUN
RUN
Hi Z
CPU_stop#
Tri-state
Mode
PD# &
Tri-state
Mode
PD# &
CPU_stop#
Tri-state
Mode
Hi Z
RUN
RUN
RUN
0660—05/05/05
3
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
General I2C serial interface information for the ICS951402
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each
byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
*See notes on the following page.
0660—05/05/05
4
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
Serial Configuration Command Bitmap
SDRAM
MHz
USB/DOT
CPU MHz
3V66 MHz
PCI MHz
REF MHz
With Spread Enabled…
MHz
FS4 FS3 FS2 FS1 FS0
0
0
0
0
0
66.67
33.33
14.318
48.008
100.00
133.34
200.01
166.65
100.00
133.34
133.16
166.45
105.00
140.00
66.67
175.00
109.99
146.65
210.00
183.27
100.00
133.34
200.01
166.65
133.34
100.00
166.45
133.16
105.00
140.00
66.67
175.00
109.99
146.65
210.00
183.27
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.67
66.67
66.66
66.67
66.67
66.58
66.58
70.00
70.00
66.67
70.00
73.33
73.33
70.00
73.31
66.34
66.34
66.34
66.34
66.34
66.34
66.29
66.29
66.26
66.26
66.26
66.25
66.26
66.26
66.18
66.18
33.33
33.33
33.33
33.33
33.33
33.29
33.29
35.00
35.00
33.33
35.00
36.66
36.66
35.00
36.65
33.17
33.17
33.17
33.17
33.17
33.17
33.15
33.15
33.13
33.13
33.13
33.13
33.13
33.13
33.09
33.09
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
48.008
SpreaD OFF
OR
Center spread +/-0.3%
99.51
132.68
199.02
165.85
99.51
132.68
132.59
165.73
99.51
132.68
199.02
165.85
132.68
99.51
Down Spread -0.6%
165.73
132.59
99.39
132.51
198.77
165.64
99.39
132.51
132.36
165.45
99.39
132.51
198.77
165.64
132.51
99.39
Down Spread -0.8%
165.45
132.36
0660—05/05/05
5
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
I2C Table: Reserved Register
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pin #
Name
Type
0
1
PWD
Byte 0
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C Table: Reserved Register
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pin #
Name
Type
0
1
PWD
Byte 1
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C Table: Reserved Register
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pin #
Name
Type
0
1
PWD
Byte 2
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0660—05/05/05
6
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
I2C Table: Reserved Register
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pin #
Name
Type
0
1
PWD
Byte 3
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C Table: Functionality and Frequency Select Register
Control
Function
Name
Type
0
1
PWD
Pin #
Byte 4
FS3
FS2
FS1
FS0
RW
RW
RW
RW
Bit 7
Bit 6
Bit 5
Bit 4
-
Freq Select Bit 7
Freq Select Bit 6
Freq Select Bit 5
Freq Select Bit 4
0
0
0
0
See
Frequency Table
-
-
-
Frequency H/W or
IIC Select
-
FS Source
RW Latch Input
IIC
0
Bit 3
Freq Select Bit 2
SPREAD Enable
Output Control
RW
RW
RW
Bit 2
Bit 1
Bit 0
-
-
-
FS4
SS_EN
All Outputs
See Frequency Table
0
1
0
OFF
ON
Normal
Tri-state
Note: If Byte4 bit1 = 0 then FS4=0
I2C Table: Output Control and Read Back Register
Control
Function
Pin #
Name
Type
0
1
PWD
Byte 5
31
32
26
-
-
-
AGP1
AGP0
Output Control
Output Control
24 or 48 Select
FS4 Read back
FS3 Read back
FS2 Read back
FS1 Read back
FS0 Read back
RW
RW
RW
R
R
R
Disable
Disable
48MHz
Enable
Enable
24MHz
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
24_48#SEL
FS4RB
FS3RB
FS2RB
FS1RB
FS0RB
X
X
X
X
X
X
-
-
-
-
-
-
-
-
-
-
-
-
R
R
0660—05/05/05
7
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
I2C Table: Output Control Register
Control
Function
Pin #
Name
Type
0
1
PWD
Byte 6
-
-
-
-
-
-
CPU_STOP#
PD#
CPU Stop Status
RW
RW
RW
RW
RW
RW
RW
RW
1
1
0
0
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
See Table 1:
Truth Table on page 3
PD# Status
PCI_F0
PCI_F1
CPUT/C_0
CPUT/C_1
CPUT/C_0
CPUT/C_1
Free-run Control
Free-run Control
Free-run Control
Free-run Control
Output Control
Output Control
Free
Free
Free
Free
Disable
Disable
Not free
Not free
Not free
Not free
Enable
Enable
40,39
44,43
I2C Table: Output Control Register
Control
Function
Pin #
Name
Type
0
1
PWD
Byte 7
15
PCICLK_F1
PCICLK_F0
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
14
23
22
21
20
17
16
I2C Table: Byte Count Register
Control
Function
PWD
Pin #
Name
Type
0
1
Byte 8
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
Writing to this
register will configure
how many bytes will
be read back, default
is 0F= 15 bytes.
0660—05/05/05
8
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
I2C Table: Watchdog Timer Register
PWD
Pin #
Name
Control Function Type
0
1
Byte 9
-
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
1
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These bits represent
RW
-
-
-
-
-
-
-
X*293ms the
RW
watchdog timer will
RW
wait before it goes to
alarm mode. Default
is 16 X 293ms =4.688
RW
RW
RW
seconds
RW
I2C Table: WD Timer Control Register
Control
Function
PWD
Pin #
Name
Type
0
1
Byte 10
Latched
Inputs
IIC Prog.
B (11:17)
M/N Programming
Enable
-
M/NEN
RW
0
Bit 7
Watchdog Enable
WD Status Control
-
-
WDEN
RW
RW
Disable
Enable
ON
0
0
Bit 6
Bit 5
WDStatus
OFF
-
-
-
-
-
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
1
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to these bit will
configure the safe
frequency as Byte 0 Bit
(6:0)
Note: If Byte4 bit1 = 0 then FS4=0
I2C Table: VCO Frequency Control Register
Control
Function
PWD
Pin #
Name
Type
0
1
Byte 11
-
-
-
-
-
-
-
-
N Div8
M Div6
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Divider Bit 8
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal
representation of M
Div (6:0) is equal to
reference divider
value. Default at
power up = latch-in
or Byte 0 Rom table.
0660—05/05/05
9
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
I2C Table: VCO Frequency Control Register
Control
Function
PWD
Pin #
Name
Type
0
1
Byte 12
-
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal
-
-
-
-
-
-
-
representation of N
Div (8:0) is equal to
VCO divider value.
Default at power up
= latch-in or Byte 0
Rom table.
I2C Table: Spread Spectrum Control Register
Control
Function
PWD
Pin #
Name
Type
0
1
Byte 13
-
-
-
-
-
-
-
-
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread
Spectrum bits will
program the spread
percentage. It is
recommended to use
ICS Spread % table
for spread
programming.
I2C Table: Spread Spectrum Control Register
Control
PWD
Pin #
Name
Type
0
1
Byte 14
Function
Reserved
Reserved
Reserved
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
SSP12
SSP11
SSP10
SSP9
R
R
R
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
It is recommended
to use ICS Spread
% table for spread
programming.
SSP8
0660—05/05/05
10
Integrated
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Systems, Inc.
ICS951402
Advance Information
I2C Table: Output Divider Control Register
Control
Function
PWD
Pin #
Name
Type
0
1
Byte 15
-
-
-
-
-
-
-
-
SD Div3
SD Div2
SD Div1
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SDRAM divider ratio
can be configured
via these 4 bits
individually.
See Table 2: Divider
Ratio Combination
Table
SD Div0
CPU Div3
CPU Div2
CPU Div1
CPU Div0
CPU divider ratio can
be configured via
these 4 bits
See Table 2: Divider
Ratio Combination
Table
individually.
Table 2: CPU, SDRAM, AGP and PCI66 Divider Ratio Combination Table
Divider (3:2)
Bit
00
01
10
11
MSB
8
16
24
40
56
1
2
3
5
7
2
4
6
10
14
Div
4
8
12
20
28
Div
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
00
01
10
11
Address
Div
Address
Address
Address
Div
LSB
Table 3: PCI33 Divider Ratio Combination Table
Divider (3:2)
Bit
00
01
10
11
MSB
8
32
24
40
56
Div
1
4
3
5
7
2
8
6
10
14
Div
4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
00
01
10
11
16
12
20
28
Div
Address
Div
Address
Address
Address
LSB
0660—05/05/05
11
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
I2C Table: Output Divider Control Register
Control
Function
PWD
Pin #
Name
Type
0
1
Byte 16
-
-
-
-
-
-
-
-
AGP Div3
AGP Div2
AGP Div1
AGP Div0
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AGP divider ratio can
be configured via
these 4 bits
See Table 2: Divider
Ratio Combination
Table
individually
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
-
-
-
I2C Table: Output Divider Control Register
Control
Function
PWD
Pin #
Name
Type
0
1
Byte 17
AGP Phase Invert
-
-
AGPINV
Reserved
RW
RW
Default
-
Inverse
-
X
X
Bit 7
Bit 6
Reserved
SDRAM
Phase Invert
-
SDINV
RW
Default
Default
Inverse
Inverse
X
Bit 5
CPU Phase Invert
-
-
-
-
-
CPUINV
PCIDiv3
PCIDiv3
PCIDiv3
PCIDiv3
RW
RW
RW
RW
RW
X
X
X
X
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCI divider ratio can
be configured via
these 4 bits
See Table 2 & 3:
Divider Ratio
Combination Table
individually
I2C Table: Group Skew Control Register
Control
Function
PWD
Pin #
Name
Type
0
1
Byte 18
-
-
-
-
-
-
-
-
CPUSkw3
CPUSkw2
SDSkw3
CPUT
Skew Control
RW
RW
RW
RW
RW
RW
RW
RW
See 2-bit Skew
Control at table 4
1
0
0
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SDRAM
Skew Control
See 2-bit Skew
Control at table 4
SDSkw2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
-
-
-
0660—05/05/05
12
Integrated
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Systems, Inc.
ICS951402
Advance Information
Table 4:Skew Specification on Output Mode
Bit3
Bit2
Bit1
Bit0
Skew in ps
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
500
750
1000
1250
I2C Table: Group Skew Control Register
Control
Function
Reserved
Reserved
Reserved
Reserved
Pin #
Name
Type
0
1
PWD
Byte 19
-
Reserved
Reserved
Reserved
Reserved
AGPSkw3
AGPSkw2
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
AGP
Skew Control
See 2-bit Skew
Control at table 4
Reserved
Reserved
-
-
-
-
I2C Table: Group Skew Control Register
Control
Function
PWD
Pin #
Name
Type
0
1
Byte 20
-
-
-
-
-
-
-
-
PCISkw3
PCISkw2
Reserved
Reserved
PCISkw1
PCISkw0
Reserved
Reserved
PCI_F [1:0]
Skew Control
RW
RW
RW
RW
RW
RW
RW
RW
See 2-bit Skew
Control at table 4
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
PCI [5:0]
-
-
-
-
See 2-bit Skew
Control at table 4
Skew Control
Reserved
Reserved
-
-
-
-
0660—05/05/05
13
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
I2C Table: Slew Rate Control Register
Control
Function
PWD
Pin #
Name
Type
0
1
Byte 21
-
-
-
-
-
-
-
-
24_48Slw1
24_48Slw0
AGPSlw1
AGPSlw0
Reserved
Reserved
REFSlw1
REFSlw0
24_48 Slew Rate
Control
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AGP Slew Rate
Control
Reserved
Reserved
REF Slew
Rate Control
I2C Table: Slew Rate Control Register
Control
Function
PWD
Pin #
Name
Type
0
1
Byte 22
-
-
-
-
-
-
-
-
SDSlw1
SDSlw0
SDRAM Slew Rate
Control
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
PCISlw1
PCISlw0
PCISlw1
PCISlw0
Reserved
Reserved
PCI_F Slew Rate
Control
PCI Slew Rate
Control
I2C Table: Output Control Register
Control
Function
PWD
Pin #
Name
Type
0
1
Byte 23
-
27
47
28
26
4
Reserved
48MHz_1
SDRAM
48MHz_0
24_48MHz
REF2
Reserved
-
-
-
X
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
3
2
REF1
REF0
0660—05/05/05
14
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
I2C Table: Reserved Control Register
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pin #
Name
Type
0
1
PWD
Byte 24
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
I2C Table: Reserved Control Register
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pin #
Name
Type
0
1
PWD
Byte 25
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
0660—05/05/05
15
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
2
TYP MAX
VDD
UNITS
V
Input High Voltage
VIH
+0.3
VSS
0.3
-5
-
Input Low Voltage
Input High Current
VIL
IIH
0.8
5
V
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
mA
mA
IIL1
-5
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
IIL2
-200
CL = Full load; Select @ 100
Operating Supply Current
IDD3.3OP
229
220
230
233
360
mA
mA
MHz
CL =Full load; Select @ 133
IDD3.3OP
IDD3.3PD
Fi
360
45
MHz
IREF=5 mA
Powerdown Current
Input Frequency
Pin Inductance
38.1
mA
MHz
nH
VDD = 3.3 V
14.32
Lpin
7
5
CIN
Logic Inputs
pF
Input Capacitance1
Clk Stabilization1,2
COUT
CINX
Output pin capacitance
6
pF
X1 & X2 pins
From PowerUp or deassertion of
PowerDown to 1st clock.
27
36
1
45
pF
TSTAB
1.8
10
10
ms
ns
t
t
PZH,tPZL
Output enable delay (all outputs)
1
1
Delay1
PHZ,tPLZ
Output disable delay (all outputs)
ns
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for buffered and un-buffered timing requirements.
0660—05/05/05
16
Integrated
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Systems, Inc.
ICS951402
Advance Information
Electrical Characteristics - CPU (0.7V Select)
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Current Source Output
Impedance
SYMBOL
Zo1
CONDITIONS
MIN
3000
2.4
TYP MAX
UNITS
VO = Vx
Ω
Output High Voltage
VOH3
IOH = -1 mA
V
Output Low Voltage
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
VOL3
VHigh
VLow
Vovs
Vuds
IOL = 1 mA
0.4
850
150
Statistical measurement on
single ended signal using
Measurement on single ended
signal using absolute value.
660
-150
710
0
mV
1150
mV
mV
mV
-450
250
Vcross(abs)
550
140
Variation of crossing over all
edges
Crossing Voltage (var)
d-Vcross
Rise Time
Fall Time
tr
VOL = 0.175V, VOH = 0.525V
175
175
240
242
700
700
125
125
ps
ps
ps
ps
tf
VOH = 0.525V VOL = 0.175V
Rise Time Variation
Fall Time Variation
d-tr
d-tf
Measurement from differential
wavefrom
Duty Cycle
dt3
45
51
55
%
Skew
tsk3
VT = 50%
50
76
100
150
ps
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 50%
1Guaranteed by design, not 100% tested in production.
2 IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - AGP
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
CONDITIONS
MIN
TYP MAX
66.66
UNITS
MHz
W
1
VO = VDD*(0.5)
IOH = -1 mA
12
33
55
RDSP1
1
2.4
V
VOH
1
IOL = 1 mA
0.55
-33
V
VOL
V OH@MIN = 1.0 V, V
=
=
OH@MAX
1
Output High Current
Output Low Current
-33
30
mA
mA
IOH
3.135 V
VOL @MIN = 1.95 V, VOL @MAX
0.4 V
1
38
IOL
1
Rise Time
Fall Time
Duty Cycle
Skew
VOL = 0.4 V, VOH = 2.4 V
0.5
0.5
45
1.38
1.45
54.4
243
2
ns
ns
%
tr1
1
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2
tf1
1
dt1
55
250
250
1
tsk1
VT = 1.5 V
ps
ps
1
Jitter
tjcyc-cyc
VT = 1.5 V 3V66
139
1Guaranteed by design, not 100% tested in production.
0660—05/05/05
17
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
CONDITIONS
MIN
TYP MAX
48
UNITS
MHz
W
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
20
48
60
RDSP1
1
2.4
V
VOH
1
0.4
-23
V
VOL
V OH@MIN = 1.0 V, V OH@MAX
3.135 V
VOL @MIN = 1.95 V, VOL @MAX
0.4 V
=
=
1
Output High Current
Output Low Current
-29
29
mA
mA
IOH
1
27
IOL
1
48DOT Rise Time
48DOT Fall Time
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
0.5
0.5
1
0.6
0.8
1
1
ns
ns
ns
ns
%
tr1
1
tf1
1
VCH 48 USB Rise Time
VCH 48 USB Fall Time
48 DOT Duty Cycle
VCH 48 USB Duty Cycle
48 DOT Jitter
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.2
2
tr1
1
1
1.3
2
tf1
1
dt1
45
45
52.8
53.5
183
0.43
223
55
55
350
1
1
dt1
VT = 1.5 V
%
1
VT = 1.5 V
ps
ns
ps
tjcyc-cyc
1
USB to DOT Skew
VT = 1.5 V (0 OR 180 degrees)
tsk1
1
VCH Jitter
tjcyc-cyc
VT = 1.5 V
350
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD =VDDL 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN TYP MAX UNITS
1
RDSP2A
10
10
20
20
Ω
Ω
1
RDSN2A
VO = VDD*(0.5)
IOH = -28 mA
VOH2A
VOL2A
IOH2A
IOL2A
2.4
V
IOL = 19 mA
0.4
-42
V
VOH = 2.0 V
mA
mA
ns
ns
%
VOL = 0.8 V
33
0.5
0.5
45
1
tr2A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2.0
2
1
Fall Time
tf2A
1
Duty Cycle
Jitter1
dt2A
55
tcyc-cyc
VT = 1.5 V
250.0
ps
1Guaranteed by design, not 100% tested in production.
0660—05/05/05
18
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
CONDITIONS
MIN
TYP MAX
UNITS
MHz
W
1
VO = VDD*(0.5)
IOH = -1 mA
20
48
60
RDSP1
1
2.4
V
VOH
1
IOL = 1 mA
0.4
-23
V
VOL
V OH@MIN = 1.0 V, V
=
=
OH@MAX
1
Output High Current
Output Low Current
-29
29
mA
mA
IOH
3.135 V
VOL @MIN = 1.95 V, VOL @MAX
0.4 V
1
27
IOL
1
Rise Time
Fall Time
Duty Cycle
Jitter
VOL = 0.4 V, VOH = 2.4 V
1
1
1.25
1.15
53
2
2
ns
ns
%
tr1
1
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
tf1
1
dt1
45
55
1
tjcyc-cyc
VT = 1.5 V
1000
ps
1Guaranteed by design, not 100% tested in production.
0660—05/05/05
19
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0660—05/05/05
20
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their
next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low.There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUT
CPUC
0660—05/05/05
21
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
6.10 mm. Body, 0.50 mm. Pitch TSSOP
c
N
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
2
E1
e
6.00
6.20
.236
.244
a
0.50 BASIC
0.020 BASIC
D
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
VARIATIONS
A1
D mm.
D (inch)
N
- C -
MIN
12.40
MAX
12.60
MIN
.488
MAX
.496
48
e
SEATING
PLANE
Reference Doc.: JEDEC Publication 95, MO-153
b
10-0039
aaa
C
Ordering Information
ICS951402yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0660—05/05/05
22
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
300 mil SSOP
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS
COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
MAX
.110
A
A1
b
.008
.008
.005
.016
.0135
.010
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
α
h x 45°
D
N
a
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
VARIATIONS
A
D mm.
D (inch)
N
MIN
MAX
MIN
MAX
.630
A1
48
15.75
16.00
.620
- C -
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
e
SEATING
PLANE
b
.10 (.004) C
Ordering Information
ICS951402yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0660—05/05/05
23
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