ICS95V842YF-T [IDT]

PLL Based Clock Driver, 95V Series, 1 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, MO-137, SSOP-16;


型号：	ICS95V842YF-T
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	PLL Based Clock Driver, 95V Series, 1 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, MO-137, SSOP-16 驱动光电二极管逻辑集成电路
文件：	总9页 (文件大小：74K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS95V842

Integrated

Circuit

Systems, Inc.

DDR Phase Lock Loop Clock Driver (60MHz - 220MHz)

RecommendedApplication:

Pin Configuration

1:2 DDRI Clock Driver

VDD2.5 1

DDRT0 2

DDRC0 3

GND 4

16 GND

15 DDRC1

14 DDRT1

13 VDD2.5

12 FB_INC

11 FB_INT

10 FB_OUTT

9 FB_OUTC

ProductDescription/Features:

•

Low skew, low jitter PLL clock driver

Feedback pins for input to output synchronization

CLK_INT 5

CLK_INC 6

AVDD 7

•

Spread Spectrum tolerant inputs

With bypass mode mux

Operating frequency 60 to 220 MHz

AGND 8

SwitchingCharacteristics:

16 pin SSOP

•

CYCLE - CYCLE jitter: <75ps

OUTPUT - OUTPUT skew: <60ps

Period jitter:±75ps

Half-Period jitter:±75ps

Functionality

INPUTS

OUTPUTS

PLL State

AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC

GND

Bypassed/Off

2.5V

(nom)

2.5V

(nom)

Block Diagram

FB_INT

FB_INC

FB_OUTT

FB_OUTC

PLL

CLK_INC

CLK_INT

DDRT (1:0)

DDRC(1:0)

AVDD

0830A—09/10/04

ICS95V842

Pin Descriptions

PIN #

PIN NAME

VDD2.5

DDRT0

DDRC0

GND

CLK_INT

CLK_INC

AVDD

PIN TYPE

PWR

OUT

PWR

DESCRIPTION

Power supply, nominal 2.5V

"True" Clock of differential pair output.

"Complementary" Clock of differential pair output.

Ground pin.

"True" reference clock input.

"Complementary" reference clock input.

3.3V Analog Power pin for Core PLL

AGND

Analog Ground pin for Core PLL

Complement single-ended feedback output, dedicated external

feedback. It switches at the same frequency as other DDR outputs,

This output must be connect to FB_INC.

True single-ended feedback output, dedicated external feedback. It

switches at the same frequency as other DDR outputs, This output

must be connect to FB_INT.

FB_OUTC

FB_OUTT

FB_INT

OUT

True single-ended feedback input, provides feedback signal to internal

PLL for synchronization with CLK_INT to eliminate phase error.

Complement single-ended feedback input, provides feedback signal to

internal PLL for synchronization with CLK_INT to eliminate phase

error.

FB_INC

VDD2.5

DDRT1

DDRC1

GND

PWR

OUT

PWR

Power supply, nominal 2.5V

"True" Clock of differential pair output.

"Complementary" Clock of differential pair output.

Ground pin.

0830A—09/10/04

ICS95V842

Absolute Maximum Ratings

Supply Voltage: (VDD & AVDD) . . . . . . . . . . . . . . . . -0.5V to 3.6V

Input clamp current: I_IK(VI < 0 or VI > VDD). . . . . . +/- 50mA

Output clamp current: I_OK(VO < 0 or VO > VDD) . . +/- 50mA

Continuous output current: I_O(VO = 0 to VDD) . . . . +/- 50mA

Package thermal impedance, theta JA: DGG package +89°C/Ω

StorageTemperature . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These

ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose

listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect product reliability.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)

SYMBOL

MIN

TYP

MAX

UNITS

µA

PARAMETER

Input High Current

Input Low Current

CONDITIONS

V_I= V_DDor GND

C = 0pF, R =

I_IH

I_IL

µA

I_DD2.5

160

100

Operating Supply

Current

∞Ω

I_DDPD

I_OH

µA

C = 0pF, R =

Ω

∞

Output High Current

Output Low Current

V_DD= 2.3V, V_OUT= 1V

V_DD= 2.3V, V_OUT= 1.2V

-18

I_OL

I_OZ

V_IK

High Impedance

Output Current

Input Clamp Voltage

V_DD=2.7V, Vout=V_DDor GND

Iin = -18mA

±10

-1.2

µA

_DD= min to max,

_OH= -1 mA

V_DD= 2.3V,

_OH= -12 mA

V_DD- 0.1

1.7

V_OH

High-level output voltage

V_DD= min to max

I_OL=1 mA

V_DD= 2.3V

0.1

0.6

V_OL

Low-level output voltage

I_OH=12 mA

Input Capacitance¹

Output Capacitance¹

C_IN

C_OUT

VI = V_DDor GND

¹Guaranteed by design and characterization, not 100% tested in production.

0830A—09/10/04

ICS95V842

DC Electrical Characteristics

TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)

PARAMETER

Supply Voltage

SYMBOL

_DDQ, A_VDD

CONDITIONS

MIN

2.3

TYP

2.5

MAX

2.7

UNITS

CLK_INT, CLK_INC, FB_INC,

FB_INT

CLK_INT, CLK_INC, FB_INC,

FB_INT

Low level input voltage

High level input voltage

V_IL

0.4

2.1

_DD/2 - 0.18

V_IH

V_IN

V_ID

V_OD

V_OX

V_IX

T_A

_DD/2 + 0.18

-0.3

DC input signal voltage

(note 1,2)

Differential input signal

voltage (note 3)

Differential output voltage

(note 3)

Output differential cross-

voltage (note 4)

Input differential cross-

voltage (note 4)

V_DD+ 0.3

CLK_INT, CLK_INC, FB_INC,

FB_INT

CLK_INT, CLK_INC, FB_INC,

FB_INT

0.36

_DD+ 0.6

0.7

V_DD/2 - 0.15

V_DD/2 - 0.2 V_DD/2 V_DD/2 + 0.2

V_DD/2 + 0.15

Operating free-air

temperature

°C

Notes:

1 Unused inputs must be held high or low to prevent them from floating.

2 DC input signal voltage specifies the allowable DC excursion of differential input.

3 Differential input signal voltage specifies the differential voltage [VTR-VCP] required for switching,

where VTR is the true input level and VCP is the complementary input level.

4 Differential cross-point voltage is expected to track variations of VDD and is the voltage at which

the differential signal must be crossing.

Timing Requirements

T_A= 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)

CONDITIONS

PARAMETER

Max clock frequency³

Application Frequency

Range³

SYMBOL

freq_op

MIN

MAX UNITS

233

MHz

freq_App

220

MHz

Input clock duty cycle

CLK stabilization

d_tin

T_STAB

100

µs

0830A—09/10/04

ICS95V842

Switching Characteristics

T_A= 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)

PARAMETER

Max clock frequency³

SYMBOL

freq_op

CONDITION

MIN

TYP

MAX UNITS

333

MHz

Application Frequency

Range³

freq_App

220

MHz

d_tin

t_sl(I)

Input clock duty cycle

Input clock slew rate

v/ns

µs

T_STAB

CLK stabilization

100

Low-to high level propagation

delay time

High-to low level propagation

delay time

CLK_IN to any output

5.5

t_PLH

t_PHL

t_en

t_dis

Output enable time

PD# to any output

Output disable time

Period jitter

t_{jit (per)}

t_jit(hper)

t_sl(o)

-75

2.5

Half-period jitter

Output clock slew rate

Cycle to Cycle Jitter

Static Phase Offset

Output to Output Skew

Over the application

frequency range

v/ns

t_cyc-t_cyc

t_(spo)

-75

-50

t_skew

Notes:

1. Refers to transition on noninverting output in PLL bypass mode.

2. While the pulse skew is almost constant over frequency, the duty cycle error

increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,

were the cycle (tc) decreases as the frequency goes up.

3. Switching characteristics are guaranteed for application frequency range. The

PLL Locks over the Max Clock Frequency range, but the device doe not

necessarily meet other timing parameters.

4. Does not include jitter.

0830A—09/10/04

ICS95V842

Parameter Measurement Information

(CLKC)

R = 60Ω

(CLKC)

ICS95V842

GND

Figure 1. IBIS Model Output Load

DD/2

C = 14 pF

ICS95V842

-V

DD/2

SCOPE

R = 10Ω Z = 50Ω

Z = 60Ω

R = 50Ω

(TT)

R = 10Ω

Z = 50Ω

R = 50Ω

C = 14 pF

DD/2

(TT)

-V

DD/2

NOTE: V

(TT) = GND

Figure 2. Output Load Test Circuit

Y_X, FB_OUTC

Y_X, FB_OUTT

c(n+1)

c(n)

= t

± t

jit(cc) c(n) c(n+1)

Figure 3. Cycle-to-Cycle Jitter

0830A—09/10/04

ICS95V842

Parameter Measurement Information

CLK_INC

CLK_INT

FB_INC

FB_INT

( ) n

( ) n+1

n = N

( ) n

( )

(N is a large number of samples)

Figure 4. Static Phase Offset

Y_X

Y_X, FB_OUTC

Y_X, FB_OUTT

t_{(SK_O)}

Figure 5. Output Skew

Y_X, FB_OUTC

Y_X, FB_OUTT

Y_X, FB_OUTC

Y_X, FB_OUTT

f_O

t_{(jit_per)}

t_C(n)

f_O

Figure 6. Period Jitter

0830A—09/10/04

ICS95V842

Parameter Measurement Information

Y_X, FB_OUTC

Y_X, FB_OUTT

(hper_n+1)

(hper_n)

t_{(jit_Hper)}t_{(jit_Hper_n)}

2xf_O

Figure 7. Half-Period Jitter

80%

, V

ID OD

20%

Clock Inputs

and Outputs

Rise t

Fall t

Figure 8. Input and Output Slew Rates

0830A—09/10/04

ICS95V842

16-Lead, 150 mil SSOP (QSOP)

In Millimeters

In Inches

SYMBOL

COMMON DIMENSIONS COMMON DIMENSIONS

MIN

1.35

0.10

0.20

0.18

MAX

1.75

0.25

1.50

0.30

0.25

MIN

.053

.004

.008

.007

MAX

.069

.010

.059

.012

.010

SEE VARIATIONS

5.80

3.80

0.635 BASIC

6.20

4.00

.228

.150

0.025 BASIC

.244

.157

0.40

1.27

.016

.050

SEE VARIATIONS

0° 8°

SEE VARIATIONS

0° 8°

SEE VARIATIONS

VARIATIONS

D mm.

(Ref)

0.23

D (inch)

(Ref)

.009

MIN

4.80

MAX

5.00

MIN

.189

MAX

.197

Reference Doc.: JEDEC Publication 95, MO-137

10-0032

Ordering Information

ICS95V842yFLF-T

Example:

ICS XXXX y F LF- T

Designation for tape and reel packaging

Lead Free (Optional)

Package Type

F = SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

Prefix

ICS = Standard Device

0830A—09/10/04

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