ICS95V847G-T [IDT]
Clock Driver;
| 型号： | ICS95V847G-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver |
| 文件： | 总9页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS95V847
Integrated
Circuit
Systems,Inc.
2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)
RecommendedApplication:
Pin Configuration
•
•
Zero Delay Board Fan Out, SO-DIMM
Provides complete DDR registered DIMM solution
with ICSSSTV16857, ICSSSTV16859 or
ICSSSTV32852
GND
CLKC0
CLKT0
GND
1
2
3
24
23
22
21
20
19
18
17
16
15
14
13
CLKT4
CLKC4
CLKC3
CLKT3
VDD
4
ProductDescription/Features:
VDD
5
CLK_INT
CLK_INC
AVDD
AGND
CLKC1
CLKT1
VDD
6
7
8
9
10
11
12
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT2
CLKC2
GND
•
•
•
•
Low skew, low jitter PLL clock driver
1 to 5 differential clock distribution (SSTL_2)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
SwitchingCharacteristics:
•
•
•
•
CYCLE - CYCLE jitter: <60ps
OUTPUT - OUTPUT skew: <60ps
Period jitter: 30ps
24-Pin TSSOP
4.40 mm. Body, 0.65 mm. pitch
DUTY CYCLE: 49.5% - 50.5%
Functionality
Block Diagram
INPUTS
OUTPUTS
PLL State
FB_OUTT
FB_OUTC
AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
GND
GND
L
H
L
L
H
L
L
H
L
Bypassed/off
Bypassed/off
CLKT0
CLKC0
FB_INT
FB_INC
H
H
H
PLL
CLK_INC
CLK_INT
2.5V
(nom)
CLKT1
CLKC1
L
H
L
L
H
L
L
H
L
on
on
2.5V
(nom)
CLKT2
CLKC2
H
H
H
CLKT3
CLKC3
CLKT4
CLKC4
0718D—04/08/05
ICS95V847
Pin Descriptions
PIN NUMBER
5, 12, 20
PIN NAME
TYPE
DESCRIPTION
VDD
GND
PWR Power supply, 2.5V
PWR Ground
1, 4, 13
8
9
AVDD
AGND
PWR Analog power supply, 2.5V
PWR Analog ground
3, 11, 15, 21, 24 CLKT[0:4]
2, 10, 14, 22, 23 CLKC[0:4]
OUT
OUT
IN
"True" Clock of differential pair outputs
"Complementary" clocks of differential pair outputs
"True" reference clock input
6
7
CLK_INT
CLK_INC
IN
"Complementary" reference clock input
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT
16
17
FB_OUTT
FB_OUTC
OUT
OUT
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error
19
18
FB_INT
FB_INC
IN
IN
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error
This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.
ICS95V847 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to five differential
pairofclockoutputs(CLKT[4:0], CLKC[4:0])andonedifferentialpairfeedbackclockoutput(FB_OUT, FB_OUTC).The
clockoutputsarecontrolledbyinputclock(CLK_INT, CLK_INC), thefeedbackclock(FB_INT, FB_INC)andtheanalog
power input (AVDD).When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
The PLL in ICS95V847 clock driver uses the input clock (CLK_INC, CLK_INT) and the feedback clock (FB_INT,
FB_INC)toprovidehigh-performance, low-skew, low-jitterdifferentialoutputclocks(CLKT[4:0], CLKC[4:0]). ICS95V847
is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS95V847 is characterized for operation from 0°C to 85°C.
0718D—04/08/05
2
ICS95V847
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD). . . . . . . . . . . -0.5V to 4.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to VDD + 0.5V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +85°C
StorageTemperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Input High Current
Input Low Current
Operating Supply
Current
SYMBOL
CONDITIONS
VI = VDD or GND
VI = VDD or GND
MIN
5
TYP
MAX
UNITS
µA
IIH
IIL
5
µA
IDD2.5 CL = 0pf @ 200MHz
IDDPD CL = 0pf
148
100
mA
µA
High Impedance
Output Current
VDD = 2.7V, Vout = VDD or
GND
IOZ
10
mA
Input Clamp Voltage
VIK
VDD = 2.3V Iin = -18mA
-1.2
V
V
High-level output
voltage
IOH = -1 mA
VDD - 0.1
1.7V
VOH
I
I
I
OH = -12 mA
OL =1 mA
V
0.1
0.6
3.5
V
Low-level output voltage
Input Capacitance1
1Guaranteed by design at 233MHz, not 100% tested in production.
VOL
CIN
OH =12 mA
V
VI = GND or VDD
2.5
pF
0718D—04/08/05
3
ICS95V847
Recommended Operating Condition
(see note1)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Supply Voltage
SYMBOL
VDD, AVDD
CONDITIONS
MIN
2.3
TYP
2.5
MAX
2.7
UNITS
V
V
V
V
V
CLKT, CLKC, FB_INC
0.4
VDD/2 - 0.18
0.7
Low level input voltage
High level input voltage
VIL
VIH
VIN
VID
PD#
-0.3
DD/2 + 0.18
1.7
CLKT, CLKC, FB_INC
PD#
V
2.1
VDD + 0.6
VDD + 0.3
DC input signal voltage
(note 2)
Differential input signal
voltage (note 3)
-0.3
V
DC - CLKT, FB_INT
AC - CLKT, FB_INT
0.36
0.7
VDD + 0.6
VDD + 0.6
V
V
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
High level output
current
VOX
VIX
IOH
IOL
TA
VDD/2 - 0.15
VDD/2 - 0.2
VDD/2 + 0.15
V
VDD/2
VDD/2 + 0.2
V
-6.4
5.5
85
mA
mA
°C
Low level output current
Operating free-air
temperature
0
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VDD and is the
voltage at which the differential signal must be crossing.
0718D—04/08/05
4
ICS95V847
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
CONDITIONS
2.5V+0.2V @ 25oC
PARAMETER
SYMBOL
freqop
MIN
45
MAX UNITS
Max clock frequency
233
210
60
MHz
MHz
%
Application Frequency
Range
freqApp
dtin
95
40
2.5V+0.2V @ 25oC
Input clock duty cycle
CLK stabilization
TSTAB
15
µs
Switching Characteristics (see note 3)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX UNITS
Low-to high level
1
CLK_IN to any output
5.5
5.5
ns
ns
tPLH
propagation delay time
High-to low level propagation
delay time
1
CLK_IN to any output
tPLL
Output enable time
Output disable time
Period jitter
Half-period jitter
Input clock slew rate
tEN
tdis
Tjit (per)
t(jit_hper)
tsl(i)
PD# to any output
PD# to any output
100MHz to 200MHz
100MHz to 200MHz
5
5
ns
ns
ps
-30
-75
1
30
30
4
ps
V/ns
V/ns
ps
Output clock slew rate
Cycle to Cycle Jitter1
Phase error
tsl(o)
1
2.5
60
50
60
Tcyc-Tcyc
100MHz to 200MHz
4
-50
0
ps
t(phase error)
Tskew
Output to Output Skew
ps
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula:duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
0718D—04/08/05
5
ICS95V847
Parameter Measurement Information
V
DD
V
(CLKC)
R = 60Ω
V
/2
R = 60Ω
DD
V
(CLKC)
ICS95V847
GND
Figure 1. IBIS Model Output Load
VDD/2
C = 14 pF
ICS95V847
-VDD/2
SCOPE
R = 10Ω Z = 50Ω
Z = 60Ω
Z = 60Ω
R = 50Ω
(TT)
V
R = 10Ω
Z = 50Ω
R = 50Ω
C = 14 pF
-VDD/2
V
(TT)
-VDD/2
NOTE: V
(TT) = GND
Figure 2. Output Load Test Circuit
YX, FBOUTC
YX, FBOUTT
t
t
c(n+1)
c(n)
t
= t
t
jit(cc) c(n) c(n+1)
Figure 3. Cycle-to-Cycle Jitter
0718D—04/08/05
6
ICS95V847
Parameter Measurement Information
CLK_INC
CLK_INT
FB_INC
FB_INT
t
t
( ) n
( ) n+1
n = N
1
t
( ) n
t
=
( )
N
(N is a large number of samples)
Figure 4. Static Phase Offset
YX
#
YX
YX, FB_OUTC
YX, FB_OUTT
t(SK_O)
Figure 5. Output Skew
YX, FB_OUTC
YX, FB_OUTT
YX, FB_OUTC
YX, FB_OUTT
1
fO
1
t(jit_per)
tC(n)
=
-
fO
Figure 6. Period Jitter
0718D—04/08/05
7
ICS95V847
Parameter Measurement Information
YX, FB_OUTC
YX, FB_OUTT
t
t
(hper_n+1)
(hper_n)
1
f
o
t(jit_Hper) t(jit_Hper_n)
1
2xfO
=
-
Figure 7. Half-Period Jitter
80%
80%
V
, V
ID OD
20%
20%
Clock Inputs
and Outputs
Rise t
Fall t
sl
sl
Figure 8. Input and Output Slew Rates
0718D—04/08/05
8
ICS95V847
In Millimeters
In Inches
c
N
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.19
0.09
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.012
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
1
2
E1
e
4.30
4.50
.169
.177
α
0.65 BASIC
0.0256 BASIC
D
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
7.70
MAX
7.90
MIN
.303
MAX
.311
b
24
aaa
C
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
4.40 mm. Body, 0.65 mm. pitch TSSOP
(0.0256Inch)
(173 mil)
Ordering Information
ICS95V847yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0718D—04/08/05
9
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