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ICS95V857AHT [IDT]

PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), PBGA56, MO-205, MO-225, BGA-56;
ICS95V857AHT
型号： ICS95V857AHT
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), PBGA56, MO-205, MO-225, BGA-56
文件： 总13页 (文件大小：137K)
中文：  中文翻译
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ICS95V857  
Integrated  
Circuit  
Systems,Inc.  
2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)  
RecommendedApplication:  
Pin Configuration  
•
•
DDR Memory Modules / Zero Delay Board Fan Out  
Provides complete DDR registered DIMM solution  
with ICSSSTVF16857, ICSSSTVF16859 or  
ICSSSTV32852  
GND  
CLKC0  
CLKT0  
VDD  
CLKT1  
CLKC1  
GND  
1
2
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
GND  
CLKC5  
CLKT5  
VDD  
CLKT6  
CLKC6  
GND  
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
ProductDescription/Features:  
GND  
GND  
•
•
Low skew, low jitter PLL clock driver  
1 to 10 differential clock distribution (SSTL_2)  
CLKC2  
CLKT2  
VDD  
CLKC7  
CLKT7  
VDD  
•
•
Feedback pins for input to output synchronization  
PD#forpowermanagement  
VDD  
PD#  
CLK_INT  
CLK_INC  
VDD  
AVDD  
AGND  
GND  
CLKC3  
CLKT3  
VDD  
CLKT4  
CLKC4  
GND  
FB_INT  
FB_INC  
VDD  
FB_OUTC  
FB_OUTT  
GND  
CLKC8  
CLKT8  
VDD  
CLKT9  
CLKC9  
GND  
•
•
SpreadSpectrum-tolerantinputs  
Auto PD when input signal removed  
Specifications:  
•
Meets PC3200 Class A+ specification for DDR-I 400  
support  
•
Covers all DDRI speed grades  
48-Pin TSSOP/TVSOP  
6.10 mm Body, 0.50 mm Pitch = TSSOP  
4.40 mm Body, 0.40 mm Pitch = TVSOP  
SwitchingCharacteristics:  
•
•
•
CYCLE - CYCLE jitter: <50ps  
OUTPUT - OUTPUT skew: <40ps  
Period jitter: 30ps  
Block Diagram  
FB_OUTT  
FB_OUTC  
CLKT0  
CLKC0  
Functionality  
CLKT1  
CLKC1  
INPUTS  
OUTPUTS  
Control  
CLKT2  
CLKC2  
PLL State  
PD#  
AVDD PD# CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC  
Logic  
CLKT3  
CLKC3  
GND  
GND  
H
H
L
H
L
L
H
L
L
H
L
Bypassed/off  
Bypassed/off  
H
H
H
CLKT4  
CLKC4  
2.5V  
(nom)  
L
L
L
H
L
H
L
Z
Z
L
Z
Z
H
L
Z
Z
L
Z
Z
H
L
off  
off  
on  
on  
off  
FB_INT  
FB_INC  
CLKT5  
CLKC5  
2.5V  
(nom)  
PLL  
CLK_INC  
CLK_INT  
2.5V  
(nom)  
CLKT6  
CLKC6  
H
H
X
H
L
2.5V  
(nom)  
H
H
Z
H
Z
CLKT7  
CLKC7  
2.5V  
(nom)  
<20MHz)(1)  
Z
Z
CLKT8  
CLKC8  
CLKT9  
CLKC9  
0674S—12/27/04  
ICS95V857  
Pin Configuration  
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
56-Ball BGA  
Top View  
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
CLKT0  
CLKC1  
GND  
CLKT2  
VDD  
CLK_INT CLK_INC  
VDD  
AGND  
CLKC3  
CLKT4  
CLKC0  
CLKT1  
GND  
CLKC2  
VDD  
GND  
VDD  
NC  
NC  
NB  
NB  
NC  
NC  
VDD  
GND  
GND  
VDD  
NC  
NC  
NB  
NB  
NC  
NC  
VDD  
GND  
CLKC5  
CLKT6  
GND  
CLKC7  
VDD  
FB_INC  
FB_OUTC  
GND  
CLKT8  
CLKC9  
CLKT5  
CLKC6  
GND  
CLKT7  
PD#  
FB_INT  
VDD  
FB_OUTT  
CLKC8  
CLKT9  
AVDD  
GND  
CLKT3  
CLKC4  
K
40  
31  
30  
1
GND  
CLKC2  
CLKT2  
VDD  
CLKC7  
CLKT7  
VDD  
PD#  
CLK_INT  
CLK_INC  
VDD  
FB_INT  
FB_INC  
VDD  
ICS95V857  
AVDD  
VDD  
AGND  
GND 10  
FB_OUTC  
FB_OUTT  
21  
11  
20  
40-Pin MLF  
0674S—12/27/04  
2
ICS95V857  
Pin Descriptions  
PIN NAME  
TYPE  
DESCRIPTION  
VDD  
PWR Power supply, 2.5V  
PWR Ground  
GND  
AVDD  
PWR Analog power supply, 2.5V  
PWR Analog ground  
AGND  
CLKT(9:0)  
OUT  
OUT  
IN  
"True" Clock of differential pair outputs  
CLKC(9:0)  
CLK_INC  
CLK_INT  
"Complementary" clocks of differential pair outputs  
"Complementary" reference clock input  
"True" reference clock input  
IN  
"Complementary" Feedback output, dedicated for external feedback. It  
switches at the same frequency as the CLK. This output must be wired  
to FB_INC  
FB_OUTC  
OUT  
"True" " Feedback output, dedicated for external feedback. It switches  
at the same frequency as the CLK. This output must be wired to  
FB_INT  
FB_OUTT  
FB_INT  
OUT  
IN  
"True" Feedback input, provides feedback signal to the internal PLL for  
synchronization with CLK_INT to eliminate phase error  
"Complementary" Feedback input, provides signal to the internal PLL  
for synchronization with CLK_INC to eliminate phase error  
FB_INC  
PD#  
IN  
IN  
Power Down. LVCMOS input  
This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.  
The ICS95V857 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten  
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,  
FB_OUTC).The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,  
FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AVDD).When input (PD#) is low while power is  
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are tri-stated.When AVDD  
is grounded, the PLL is turned off and bypassed for test purposes.  
WhentheinputfrequencyislessthantheoperatingfrequencyofthePLL, appproximately20MHz, thedevicewillenter  
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,  
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low.When  
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and  
outputswillbeenabledandPLLwillobtainphaselockbetweenthefeedbackclockpair(FB_INT, FB_INC) andtheinput  
clock pair (CLK_INC, CLK_INT).  
The PLL to the ICS95V857 clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,  
FB_INC) provide high-performance, low-skew, low-jitter, output differential clocks (CLKT[0:9], CLKC[0:9]). The  
ICS95V857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI.  
The ICS95V857 is characterizedfor operation from 0°C to85°C, andwill meetJEDECStandard 82-1and82-1A Class  
A+ for registered DDR clock drivers.  
0674S—12/27/04  
3
ICS95V857  
Absolute Maximum Ratings  
Supply Voltage (VDD & AVDD). . . . . . . . . . . -0.5V to 4.6V  
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V  
Ambient OperatingTemperature . . . . . . . . . . 0°C to +85°C  
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C  
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These  
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose  
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions  
for extended periods may affect product reliability.  
Electrical Characteristics - Input/Supply/Common Output Parameters  
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5V 0.2V  
PARAMETER  
SYMBOL  
CONDITIONS  
VI = VDD or GND  
VI = VDD or GND  
MIN  
5
TYP  
MAX  
UNITS  
µA  
Input High Current  
IIH  
IIL  
Input Low Current  
Operating Supply  
Current  
5
µA  
IDD2.5 CL = 0pf @ 200MHz  
IDDPD CL = 0pf  
148  
170  
100  
mA  
µA  
Output High Current  
Output Low Current  
IOH  
IOL  
VDD = 2.3V, VOUT = 1V  
VDD = 2.3V, VOUT = 1.2V  
-18  
26  
-32  
35  
mA  
mA  
High Impedance  
Output Current  
Input Clamp Voltage  
IOZ  
VDD=2.7V, Vout=VDD or GND  
VDDQ = 2.3V Iin = -18mA  
10  
mA  
VIK  
-1.2  
V
V
V
DD = min to max,  
OH = -1 mA  
DDQ = 2.3V,  
OH = -12 mA  
DD = min to max  
IOL=1 mA  
DDQ = 2.3V  
OH=12 mA  
VDDQ - 0.1  
1.7  
High-level output  
voltage  
I
VOH  
V
V
V
V
I
V
0.1  
0.6  
Low-level output voltage  
VOL  
V
I
Input Capacitance1  
Output Capacitance1  
CIN  
COUT  
VI = GND or VDD  
3
3
pF  
pF  
VOUT = GND or VDD  
1Guaranteed by design at 220MHz, not 100% tested in production.  
0674S—12/27/04  
4
ICS95V857  
Recommended Operating Condition  
(see note1)  
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)  
PARAMETER  
Supply Voltage  
SYMBOL  
VDD, AVDD  
CONDITIONS  
MIN  
2.3  
TYP  
2.5  
MAX  
2.7  
UNITS  
V
V
V
V
V
CLKT, CLKC, FB_INC  
0.4  
VDD/2 - 0.18  
0.7  
Low level input voltage  
High level input voltage  
VIL  
VIH  
VIN  
VID  
PD#  
-0.3  
DD/2 + 0.18  
1.7  
CLKT, CLKC, FB_INC  
PD#  
V
2.1  
VDD + 0.6  
VDD + 0.3  
DC input signal voltage  
(note 2)  
Differential input signal  
voltage (note 3)  
-0.3  
V
DC - CLKT, FB_INT  
AC - CLKT, FB_INT  
0.36  
0.7  
VDD + 0.6  
VDD + 0.6  
V
V
Output differential cross-  
voltage (note 4)  
Input differential cross-  
voltage (note 4)  
High level output  
current  
VOX  
VIX  
IOH  
IOL  
TA  
VDD/2 - 0.15  
VDD/2 - 0.2  
VDD/2 + 0.15  
V
VDD/2  
VDD/2 + 0.2  
V
-6.4  
5.5  
85  
mA  
mA  
°C  
Low level output current  
Operating free-air  
temperature  
0
Notes:  
1. Unused inputs must be held high or low to prevent them from floating.  
2. DC input signal voltage specifies the allowable DC execution of differential input.  
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]  
required for switching, where VT is the true input level and VCP is the  
complementary input level.  
4. Differential cross-point voltage is expected to track variations of VDD and is the  
voltage at which the differential signal must be crossing.  
0674S—12/27/04  
5
ICS95V857  
Timing Requirements  
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)  
CONDITIONS  
2.5V+0.2V @ 25oC  
PARAMETER  
SYMBOL  
freqop  
MIN  
45  
MAX UNITS  
Max clock frequency  
233  
220  
60  
MHz  
MHz  
%
Application Frequency  
Range  
freqApp  
dtin  
95  
40  
2.5V+0.2V @ 25oC  
Input clock duty cycle  
CLK stabilization  
TSTAB  
15  
µs  
Switching Characteristics (see note 3)  
PARAMETER  
SYMBOL  
CONDITION  
MIN  
TYP  
MAX UNITS  
Low-to high level  
1
CLK_IN to any output  
3.5  
3.5  
ns  
ns  
tPLH  
propagation delay time  
High-to low level propagation  
delay time  
1
CLK_IN to any output  
tPLL  
Output enable time  
Output disable time  
Period jitter  
Half-period jitter  
Input clock slew rate  
tEN  
tdis  
Tjit (per)  
t(jit_hper)  
tsl(i)  
PD# to any output  
PD# to any output  
100MHz to 200MHz  
100MHz to 200MHz  
3
3
ns  
ns  
ps  
-30  
-75  
1
30  
75  
4
ps  
V/ns  
V/ns  
ps  
Output clock slew rate  
Cycle to Cycle Jitter1  
Static Phase Offset  
Output to Output Skew  
Notes:  
tsl(o)  
1
2
Tcyc-Tcyc  
100MHz to 200MHz  
-50  
-50  
50  
50  
40  
4
0
ps  
t(static phase offset)  
Tskew  
ps  
1. Refers to transition on noninverting output in PLL bypass mode.  
2. While the pulse skew is almost constant over frequency, the duty cycle error  
increases at higher frequencies.This is due to the formula:duty cycle=twH/tc, where  
the cycle (tc) decreases as the frequency goes up.  
3. Switching characteristics guaranteed for application frequency range.  
4. Static phase offset shifted by design.  
0674S—12/27/04  
6
ICS95V857  
Parameter Measurement Information  
V
DD  
V
(CLKC)  
R = 60Ω  
V
/2  
R = 60Ω  
DD  
V
(CLKC)  
ICS95V857  
GND  
Figure 1. IBIS Model Output Load  
V
DD/2  
C = 14 pF  
ICS95V857  
-V  
DD/2  
SCOPE  
R = 10Ω Z = 50Ω  
Z = 60Ω  
Z = 60Ω  
R = 50Ω  
(TT)  
V
R = 10Ω  
Z = 50Ω  
R = 50Ω  
C = 14 pF  
V
(TT)  
-V  
DD/2  
-V  
DD/2  
NOTE: V  
(TT) = GND  
Figure 2. Output Load Test Circuit  
YX, FB_OUTC  
YX, FB_OUTT  
t
t
c(n+1)  
c(n)  
t
= t  
t
jit(cc) c(n) c(n+1)  
Figure 3. Cycle-to-Cycle Jitter  
0674S—12/27/04  
7
ICS95V857  
Parameter Measurement Information  
CLK_INC  
CLK_INT  
FB_INC  
FB_INT  
t
t
( ) n  
( ) n+1  
n = N  
1
t
( ) n  
t
=
( )  
N
(N is a large number of samples)  
Figure 4. Static Phase Offset  
YX  
#
YX  
YX, FB_OUTC  
YX, FB_OUTT  
t(SK_O)  
Figure 5. Output Skew  
YX, FB_OUTC  
YX, FB_OUTT  
YX, FB_OUTC  
YX, FB_OUTT  
1
fO  
1
t(jit_per)  
tC(n)  
=
-
fO  
Figure 6. Period Jitter  
0674S—12/27/04  
8
ICS95V857  
Parameter Measurement Information  
YX, FB_OUTC  
YX, FB_OUTT  
t
t
(hper_n+1)  
(hper_n)  
1
f
o
t(jit_Hper) t(jit_Hper_n)  
1
2xfO  
=
-
Figure 7. Half-Period Jitter  
80%  
80%  
V
, V  
ID OD  
20%  
20%  
Clock Inputs  
and Outputs  
Rise t  
Fall t  
sl  
sl  
Figure 8. Input and Output Slew Rates  
0674S—12/27/04  
9
ICS95V857  
In Millimeters  
COMMON DIMENSIONS COMMON DIMENSIONS  
In Inches  
c
N
SYMBOL  
MIN  
--  
0.05  
0.80  
0.17  
0.09  
MAX  
1.20  
0.15  
1.05  
0.27  
0.20  
MIN  
--  
.002  
.032  
.007  
.0035  
MAX  
.047  
.006  
.041  
.011  
.008  
A
A1  
A2  
b
L
E1  
E
INDEX  
AREA  
c
D
E
SEE VARIATIONS  
8.10 BASIC  
SEE VARIATIONS  
0.319 BASIC  
E1  
e
6.00  
0.50 BASIC  
6.20  
.236  
.244  
1
22  
0.020 BASIC  
a
L
0.45  
0.75  
.018  
.030  
D
N
SEE VARIATIONS  
SEE VARIATIONS  
a
aaa  
0°  
--  
8°  
0.10  
0°  
--  
8°  
.004  
A
A2  
VARIATIONS  
A1  
D mm.  
D (inch)  
N
- CC --  
MIN  
MAX  
12.60  
MIN  
.488  
MAX  
.496  
48  
12.40  
e
SEATING  
PLANE  
Reference Doc.: JEDEC Publication 95, M O-153  
b
10-0039  
aaa  
C
6.10 mm. Body, 0.50 mm. pitch TSSOP  
(0.020 mil)  
(240 mil)  
Ordering Information  
ICS XXXX y G (LF) - T  
Designation for tape and reel packaging  
Lead Free (Optional)  
Package Type  
G = TSSOP  
Revision Designator (will not correlate with datasheet revision)  
Device Type  
Prefix  
ICS = Standard Device  
Example:  
ICS95V857AGLF-T  
0674S—12/27/04  
10  
ICS95V857  
In Millimeters  
COMMON DIMENSIONS COMMON DIMENSIONS  
In Inches  
c
N
SYMBOL  
MIN  
--  
0.05  
0.80  
0.13  
0.09  
MAX  
1.20  
0.15  
1.05  
0.23  
0.20  
MIN  
--  
.002  
.032  
.005  
.0035  
MAX  
.047  
.006  
.041  
.009  
.008  
A
A1  
A2  
b
L
E1  
E
INDEX  
AREA  
c
D
E
SEE VARIATIONS  
6.40 BASIC  
SEE VARIATIONS  
0.252 BASIC  
E1  
e
L
4.30  
0.40 BASIC  
0.45  
4.50  
.169  
0.016 BASIC  
.018  
.177  
1
22  
α
0.75  
.030  
D
N
SEE VARIATIONS  
SEE VARIATIONS  
a
aaa  
0°  
--  
8°  
0.08  
0°  
--  
8°  
.003  
A
A2  
VARIATIONS  
A1  
D mm.  
D (inch)  
N
- CC --  
MIN  
9.60  
MAX  
9.80  
MIN  
.378  
MAX  
.386  
48  
e
SEATING  
PLANE  
Reference Doc.: JEDEC Publication 95, M O-153  
b
10-0037  
aaa  
C
4.40 mm. Body, 0.40 mm. pitch TSSOP  
(16 mil)  
(173 mil)  
Ordering Information  
ICS XXXX y K (LF)- T  
Designation for tape and reel packaging  
Lead Free (Optional)  
Package Type  
L = TSSOP (TVSOP)  
Revision Designator (will not correlate with datasheet revision)  
Device Type  
Prefix  
ICS = Standard Device  
Example:  
ICS95V857ALLF-T  
0674S—12/27/04  
11  
ICS95V857  
(Ref.)  
ND & NE  
Even  
Seating Plane  
(ND-1)x e  
(Ref.)  
A1  
Index Area  
1
L
A3  
E2  
N
N
(Typ.)  
If ND & NE  
are Even  
e
2
1
2
Anvil  
Singulation  
2
(NE -1)x e  
r
o
E
(Ref.)  
E2  
2
Sawn  
Singulation  
Top View  
D
b
e
Thermal  
Base  
(Ref.)  
ND & NE  
Odd  
D2  
2
A
D2  
C
0.08  
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH  
QUAD FLAT / NO LEAD PLASTIC PACKAGE  
ALL DIMENSIONS IN MILLIMETERS  
40  
10  
N
ND  
NE  
SYMBOL  
MIN.  
0.80  
0
0.25 Reference  
0.18  
MAX.  
1.00  
A
A1  
A3  
b
10  
0.05  
6.00 x 6.00  
2.75 / 3.05  
2.75 / 3.05  
0.30 / 0.50  
D x E BASIC  
D2 MIN. / MAX.  
E2 MIN. / MAX.  
L MIN. / MAX.  
0.30  
0.50 BASIC  
e
Source Reference: MLF2™SE  
10-0053  
Ordering Information  
ICS XXXX y K (LF) - T  
Designation for tape and reel packaging  
Lead Free (Optional)  
Package Type  
K = MLF  
Revision Designator (will not correlate with datasheet revision)  
Device Type  
Prefix  
ICS = Standard Device  
Example:  
ICS95V857AKLF-T  
0674S—12/27/04  
12  
ICS95V857  
C
Seating  
Plane  
Numeric Designations  
for Horizontal Grid  
A1  
b
REF  
T
3 2 1  
4
A
B
C
D
Alpha Designations  
D
for Vertical Grid  
(Letters I, O, Q & S  
not used)  
d TYP  
D1  
- e - TYP  
TOP VIEW  
E
c
REF  
TYP  
- e -  
h
TYP  
E1  
0.12  
Max.  
C
ALL DIMENSIONS IN MILLIMETERS  
----- BALL GRID -----  
REF. DIMENSIONS  
D
E
T
e
HORIZ  
VERT  
TOTAL  
d
h
D1  
5.85 Bsc  
E1  
3.25 Bsc  
b
c
Min/Max  
Min/Max  
Min/Max  
7.00 Bsc  
4.50 Bsc  
0.86/1.00  
0.65 Bsc  
6
10  
60  
0.35/0.45  
0.15/0.21  
0.575  
0.625  
**  
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.  
* Source Ref.: JEDEC Publication 95,  
10-0055  
MO-205*, MO-225**  
Ordering Information  
ICS XXXX y H (LF) - T  
Designation for tape and reel packaging  
Lead Free (Optional)  
Package Type  
H = BGA  
Revision Designator (will not correlate with datasheet revision)  
Device Type  
Prefix  
ICS = Standard Device  
Example:  
ICS95V857AHLF-T  
0674S—12/27/04  
13  

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