ICS9FG108G-T [IDT]
Clock Generator, PDSO48;
| 型号： | ICS9FG108G-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO48 光电二极管 |
| 文件： | 总19页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Description
Features/Benefits
ICS9FG108 is a Frequency Timing Generator that provides 8
differential output pairs that are compliant to the Intel CK410
specification. It also provides support for PCI-Express, next
generation I/O, and SATA. The part synthesizes several output
frequencies from either a 14.31818 Mhz crystal or a 25 MHz crystal.
The device can also be driven by a reference input clock instead of
a crystal. It provides outputs with cycle-to-cycle jitter of less than 50
ps and output-to-output skew of less than 65 ps. ICS9FG108 also
provides a copy of the reference clock. Frequency selection can be
accomplished via strap pins or SMBus control.
•
Generates common frequencies from 14.318 MHz or
25 MHz
•
•
•
•
Crystal or reference input
8 - 0.7V current-mode differential output pairs
Supports Serial-ATA at 100 MHz
Two spread spectrum modes: 0 to -0.5 downspread
and +/-0.25% centerspread
•
Unused inputs may be disabled in either driven or Hi-Z
state for power management.
Key Specifications
•
•
Programmable OE Polarity
M/N Programming
•
•
•
•
•
•
Output cycle-to-cycle jitter < 50 ps
Output to output skew < 65 ps
+/-300 ppm frequency accuracy on output clocks
+/-150 ppm frequency accuracy @100 MHz outputs
48-pin SSOP/TSSOP package
Available in RoHS compliant packaging
Funtional Block Diagram
XIN/CLKIN
X2
R EFOUT
OSC
OE(7:0)
8
STOP
LOGIC
PROGRAMMABLE
SPREAD PLL
DIF(7:0)
SPREAD
SEL14M_25M#
DIF_STOP#
FS(2:0)
CONTROL
LOGIC
SDATA
SCLK
IREF
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108 REV G 04/06/07
1
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Configuration
FunctionalityTable
Frequency Select Table
SEL14M_25M#
XIN/CLKIN
X2
1
2
3
4
5
6
7
8
9
48 VDDA
47 GNDA
46 IREF
45 **FS0
44 **FS1
43 **OE_0
42 DIF_0
41 DIF_0#
40 VDD
FS2 FS1 FS0 OUTPUT(MHz)
(FS3)
VDD
GND
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.00
125.00
133.33
166.67
200.00
266.66
333.33
400.00
100.00
125.00
133.33
166.67
200.00
266.66
333.33
400.00
REFOUT
**FS2
**OE_7
DIF_7
DIF_7#
VDD 10
DIF_6 11
DIF_6# 12
*OE_6 13
VDD 14
39 DIF_1
38 DIF_1#
37 *OE_1
36 VDD
35 GND
34 *OE_2
33 DIF_2
32 DIF_2#
31 VDD
30 DIF_3
GND 15
*OE_5 16
DIF_5 17
DIF_5# 18
VDD 19
DIF_4 20
DIF_4# 21
**OE_4 22
SDATA 23
SCLK 24
29 DIF_3#
28 **OE_3
27 *SEL14M_25M#
26 **SPREAD
25 DIF_STOP#
* indicates internal 120K pull up
** indicates internal 120K pull down
48-pin SSOP & TSSOP
Power Groups
Pin Number
VDD
3
GND
4
15,35
47
Description
REFOUT, Digital Inputs, SMBus
DIF Outputs
10,14,19,31,36,40
N/A
48
IREF
47
Analog VDD & GND for PLL Core
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
2
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Description
PIN #
PIN NAME
PIN TYPE
IN
DESCRIPTION
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Reference Clock output
1
2
3
4
5
6
XIN/CLKIN
X2
VDD
GND
REFOUT
**FS2
OUT
PWR
PWR
OUT
IN
Frequency select pin.
Active high input for enabling output 7.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
Power supply, nominal 3.3V
7
**OE_7
IN
8
9
10
11
12
DIF_7
DIF_7#
VDD
DIF_6
DIF_6#
OUT
OUT
PWR
OUT
OUT
13
*OE_6
IN
14
15
VDD
GND
PWR
PWR
Ground pin.
Active high input for enabling output 5.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active high input for enabling output 4.
0 = tri-state outputs, 1= enable outputs
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
16
*OE_5
IN
17
18
19
20
21
DIF_5
DIF_5#
VDD
DIF_4
DIF_4#
OUT
OUT
PWR
OUT
OUT
22
**OE_4
IN
23
24
SDATA
SCLK
I/O
IN
Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors
Pin names followed by '*' have 120 Kohm pull UP resistors
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
3
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Description (continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
Active low input to stop differential output clocks.
Asynchronous, active high input to enable spread spectrum functionality.
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 = 25 MHz
Active high input for enabling output 3.
25
DIF_STOP#
IN
IN
IN
26
**SPREAD
27
*SEL14M_25M#
28
**OE_3
IN
0 = tri-state outputs, 1= enable outputs
29
30
31
32
33
DIF_3#
DIF_3
VDD
DIF_2#
DIF_2
OUT
OUT
PWR
OUT
OUT
0.7V differential complement clock output
0.7V differential true clock output
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active high input for enabling output 2.
0 = tri-state outputs, 1= enable outputs
34
*OE_2
IN
35
36
GND
VDD
PWR
PWR
Ground pin.
Power supply, nominal 3.3V
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
37
*OE_1
IN
38
39
40
41
42
DIF_1#
DIF_1
VDD
DIF_0#
DIF_0
OUT
OUT
PWR
OUT
OUT
0.7V differential complement clock output
0.7V differential true clock output
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active high input for enabling output 0.
0 = tri-state outputs, 1= enable outputs
43
**OE_0
IN
44
45
**FS1
**FS0
I/O
IN
Frequency select latch input pin / 3.3V 66.66MHz clock output.
3.3V Frequency select latched input pin.
This pin establishes the reference current for the differential current-mode output
pairs. This pin requires a fixed precision resistor tied to ground in order to establish
the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
46
IREF
OUT
47
48
GNDA
VDDA
PWR
PWR
3.3V power for the PLL core.
Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors
Pin names followed by '*' have 120 Kohm pull UP resistors
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
4
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
General SMBus serial interface information for the ICS9FG108
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address DC(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address DC(H)
Slave Address DC(H)
WR
WRite
WR
WRite
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
RT
Repeat starT
Slave Address DD(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
5
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Byte 0
Pin #
Name
Control Function
SEL14M_25M#1
Type
0
1
PWD
27
RW
Pin 27
Bit 7
(FS3)
See Frequency
Selection Table, Page 1
FS21
6
RW
RW
RW
RW
Pin 6
Pin 44
Pin 45
Pin 26
Bit 6
Bit 5
Bit 4
Bit 3
FS11
44
45
26
FS01
Spread Enable1
Off
On
Software
Select
Hi-Z
Enable Software Control of Frequency, Spread
Enable (Spread Type always Software Control)
DIF_STOP# drive mode
Hardware
Select
Driven
Down
-
RW
0
Bit 2
-
-
RW
RW
0
0
Bit 1
Bit 0
Spread Type
Center
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
SMBus Table: Output Enable Register
Byte 1
Bit 7
Pin #
Name
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
-
-
-
-
-
-
-
-
DIF_7 EN
DIF_6 EN
DIF_5 EN
DIF_4 EN
DIF_3 EN
DIF_2 EN
DIF_1 EN
DIF_0 EN
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Output Stop Mode Register
Byte 2
Bit 7
Pin #
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
-
-
-
-
-
-
-
-
DIF_7 STOP EN
DIF_6 STOP EN
DIF_5 STOP EN
DIF_4 STOP EN
DIF_3 STOP EN
DIF_2 STOP EN
DIF_1 STOP EN
DIF_0 STOP EN
Free Run/ Stop Enable
Free Run/ Stop Enable
Free Run/ Stop Enable
Free Run/ Stop Enable
Free Run/ Stop Enable
Free Run/ Stop Enable
Free Run/ Stop Enable
Free Run/ Stop Enable
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
0
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
6
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Frequency Select Readback Register
Byte 3
Pin #
Name
SEL14M_25M#1
(FS3)
Control Function
Type
0
1
PWD
27
State of pin 27
R
Pin 27
Bit 7
See Frequency
Selection Table, Page 1
FS21
FS11
FS01
6
State of pin 6
State of pin 44
State of pin 45
State of pin 26
R
R
R
Pin 6
Pin 44
Pin 45
Bit 6
Bit 5
Bit 4
44
45
26
SPREAD1
R
R
R
R
Off
On
Pin 26
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
X
X
X
Notes:
1. These bits reflect the state of the corresponding pins, regardless of whether software
programming is enabled or not.
SMBus Table: Vendor & Revision ID Register
Byte 4
Bit 7
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
X
X
X
X
0
0
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
SMBus Table: DEVICE ID
Byte 5 Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
R
R
R
R
R
R
R
R
0
1
PWD
-
-
-
-
-
-
-
-
DEVID7
DEVID6
DEVID5
DEVID4
DEVID3
DEVID2
DEVID1
DEVID0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
1
0
0
0
Device ID = 08 hex
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
7
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Byte Count Register
Byte 6
Bit 7
Pin #
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register will
configure how many bytes
will be read back, default is
07 = 7 bytes.
SMBus Table: Reserved Register
Byte 7 Pin # Name
Bit 7
Control Function
Reserved
Type
0
1
PWD
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Reserved Register
Byte 8 Pin # Name
Bit 7
Control Function
Reserved
Type
0
1
PWD
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: M/N Programming Enable
Byte 9
Pin #
Name
Control Function
PLL M/N Programming
Enable
Type
0
1
PWD
-
M/N_EN
RW
Disable
Enable
0
Bit 7
Select Polarity of OE inputs
RW
RW
OE#
Disable
OE
Enable
-
5
OE_Polarity
REFOUT_En
1
1
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Enables/Disables REF
Reserved
Reserved
Reserved
Reserved
Reserved
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
8
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: PLL Frequency Control Register
Byte 10
Bit 7
Pin #
Name
Control Function
N Divider Prog bit 8
N Divider Prog bit 9
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
PLL N Div8
PLL N Div9
PLL M Div5
PLL M Div4
PLL M Div3
PLL M Div2
PLL M Div1
PLL M Div0
The decimal representation of M
and N Divider in Byte 11 and 12
will configure the PLL VCO
frequency. Default at power up =
latch-in or Byte 0 Rom table.
VCO Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
M Divider Programming
bit (5:0)
SMBus Table: PLL Frequency Control Register
Byte 11
Bit 7
Pin #
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
PLL N Div7
PLL N Div6
PLL N Div5
PLL N Div4
PLL N Div3
PLL N Div2
PLL N Div1
PLL N Div0
The decimal representation of M
and N Divider in Byte 11 and 12
will configure the PLL VCO
frequency. Default at power up =
latch-in or Byte 0 Rom table.
VCO Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N Divider Programming
Byte11 bit(7:0) and Byte10
bit(7:6)
SMBus Table: PLL Spread Spectrum Control Register
Byte 12
Bit 7
Pin #
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
PLL SSP7
PLL SSP6
PLL SSP5
PLL SSP4
PLL SSP3
PLL SSP2
PLL SSP1
PLL SSP0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread Spectrum
bits in Byte 13 and 14 will
program the spread
Spread Spectrum
Programming bit(7:0)
pecentage of PLL
SMBus Table: PLL Spread Spectrum Control Register
Byte 13
Bit 7
Pin #
Name
Control Function
Reserved
Type
0
1
PWD
0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
PLL SSP14
PLL SSP13
PLL SSP12
PLL SSP11
PLL SSP10
PLL SSP9
PLL SSP8
RW
RW
RW
RW
RW
RW
RW
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread Spectrum
bits in Byte 13 and 14 will
program the spread
Spread Spectrum
Programming bit(14:8)
pecentage of PLL
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
9
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Reserved Test Register
Byte 14
Bit 7
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
1
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved Test Register. Do not write to this register, erratic device operation may
occur.
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
10
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DIF_STOP# - Assertion (transition from '1' to '0')
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus
DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =
HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is
programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP#
DIF
DIF#
DIF_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a
voltage greater than 200mV.
DIF_Stop#
DIF
DIF#
DIF Internal
Tdrive_DIF_Stop, 15nS >200mV
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
11
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Absolute Max
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
V
V
DD + 0.5V
DD + 0.5V
V
V
VDD_In 3.3V Logic Input Supply Voltage GND - 0.5
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
-65
0
150
70
115
°C
°C
°C
Input ESD protection
human body model
ESD prot
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
VDD + 0.3
Input High Voltage
VIH
3.3 V +/-5%
2
V
VSS
-
Input Low Voltage
Input High Current
VIL
IIH
3.3 V +/-5%
0.8
5
V
0.3
VIN = VDD
VIN = 0 V; Inputs with no pull-
up resistors
-5
-5
uA
uA
IIL1
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
IIL2
-200
uA
Full Active, CL = Full load;
f = 400 MHz
Full Active, CL = Full load;
215
180
250
200
mA
mA
1
1
IDD3.3OP
Operating Supply Current
Input Frequency3
f = 100 MHz
All outputs stopped driven
All outputs stopped Hi-Z
180
51
200
60
25
7
mA
mA
MHz
nH
1
1
3
1
IDD3.3STOP
Fi
VDD = 3.3 V
14
Pin Inductance1
Input/Output
Capacitance1
Lpin
CIN
Logic Inputs
1.5
5
6
pF
pF
1
1
COUT
Output pin capacitance
From VDD Power-Up and after
input clock stabilization to 1st
clock
Clk Stabilization1,2
TSTAB
1
1.8
ms
1,2
Modulation Frequency
DIF output enable
fMOD
Triangular Modulation
DIF output enable after
DIF_Stop# de-assertion
30
33
15
kHz
ns
1
1
tDIFOE
9.8
Input Rise and Fall times
tR/tF
20% to 80% of VDD
5
ns
1
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25
MHz to meet
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
12
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
Zo1
CONDITIONS
MIN
TYP
MAX
850
UNITS NOTES
Current Source Output
Impedance
VO = Vx
3000
Ω
1
Statistical measurement on single
ended signal using oscilloscope
math function.
Voltage High
Voltage Low
VHigh
VLow
660
1
1
mV
-150
150
Measurement on single ended
signal using absolute value.
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
1150
1
1
1
mV
mV
mV
-300
250
550
140
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
Crossing variation over all edges
1
see Tperiod min-max values
400MHz nominal
-300
300
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
1,2,5
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
1
1
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
Average period
Tperiod
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
Tabsmin
Absolute min period
tr
tf
d-tr
d-tf
dt3
tsk3
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Duty Cycle
700
700
125
125
55
VOH = 0.525V VOL = 0.175V
175
ps
%
ps
Measured Differentially
VT = 50%
45
Skew, output to output
65
22MHz/1.5MHz/1.5MHz/10ns,
14.31818 MHz REF Clock
22MHz/1.5MHz/1.5MHz/10ns,
25 MHz REF Clock
tjPCI-ephase14
tjPCI-ephase25
tjcyc-cyc
Jitter, PCI-e SRC phase
Jitter, PCI-e SRC phase
Jitter, Cycle to cycle
42
39
50
ps
ps
ps
4
4
1
Measurement from differential
wavefrom
40
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
or 25 MHz
3 Figures are for down spread.
4 This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit
http://www.pcisig.com for additional details
5 +/- 150 ppm for 100 MHz outputs
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
13
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Electrical Characteristics - REF-14.318/25 MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
Tperiod
Tperiod
VOH
CONDITIONS
see Tperiod min-max values
14.318MHz output nominal
25.000MHz output nominal
IOH = -1 mA
MIN
-300
TYP
0
MAX UNITS Notes
300
ppm
ns
ns
V
1
1,2
1,2
1
69.8270 69.8413 69.8550
Clock period
39.9880 40.0000 40.0120
Output High Voltage
2.4
Output Low Voltage
VOL
IOL = 1 mA
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
V
1
Output High Current
IOH
-29
29
-23
27
mA
mA
1
1
Output Low Current
IOL
Rise Time
Fall Time
Duty Cycle
Jitter
tr1
tf1
1
1
1.6
1.6
2
2
ns
ns
%
1
1
1
1
dt1
45
55
500
tjcyc-cyc
VT = 1.5 V
350
ps
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818 or
25.00 MHz
Electrical Characteristics - Phase Jitter (Applies to: Revision D Devices, Revision ID = 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS Notes
PCIe Gen 1 specs
(1.5 - 22 MHz)
FBD specs
(11-33 MHz)
PCIe Gen 2 specs
(5-16 MHz, 8-16 MHz)
40
108
3
ps
1
1
Jitter, Phase
tjphasePLL
ps rms
ps rms
2.23
3.1
1, 2
Notes on Phase Jitter:
1 Applicable to all DIF outputs. See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested
in production.
2 Specification applies to revision D and later devices.
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
14
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DIF Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
Unit Figure
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
Rs
Rt
0.5 max
0.2 max
0.2 max
33
inch
inch
inch
ohm
ohm
1
1
1
1
1
49.9
Down Device Differential Routing
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Unit Figure
inch
inch
1
1
Differential Routing to PCI Express Connector
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
0.25 to 14 max
0.225 min to 12.6 max inch
Unit Figure
inch
2
2
Figure 1 Down device routing.
L1
L2
L2
L4
Rs
Rs
L4’
L1’
Rt
Rt
HSCL Output
Buffer
PCI Ex Board
Down Device
REF_CLK Input
L3’ L3
Figure 1
Figure 2 PCI Express Connector Routing.
L1
Rs
L2
L4
L4’
L1’
Rs
L2’
Rt
Rt
HSCL Output
Buffer
PCI Ex
Add In Board
L3’ L3
REF_CLK Input
Figure 2
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
15
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Alternative termination for LVDS and other common differential signals. Figure 3.
Vdiff
0.45 v
0.58
0.80
0.60
Vp-p
0.22v
0.28
0.40
0.3
Vcm
1.08
0.6
0.6
1.2
R1
33
33
33
33
R2
R3
R4
Note
150
78.7
78.7
174
100
137
none
140
100
100
100
100
ICS874003i-02 input compatible
Standard LVDS
R1a = R1b = R1
Figure_3.
L1
L2
R3
R4
L4
R1a
R1b
L4’
L1’
L2’
R2a
R2b
HSCL Output
Buffer
Down Device
REF_CLK Input
L3’
L3
R2a = R2b = R2
Cable connected AC coupled application, figure 4
Component
R5a,R5b
R6a,R6b
Cc
Value
8.2K
Note
5%
1K
0.1
5%
uF
0.350
Vcm
volts
3.3 Volts
R5a
R5b
R6b
L4
Cc
L4’
Cc
R6a
PCIe Device
REF_CLK Input
Figure_4.
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
16
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
48-Lead 300 mil SSOP
c
N
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
SYMBOL
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
h
L
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
0.635 BASIC
0.025 BASIC
α
h x 45°
D
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
VARIATIONS
A1
D mm.
D (inch)
- C -
N
MIN
15.75
MAX
16.00
MIN
.620
MAX
.630
e
SEATING
PLANE
48
b
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS9FG108yFLF-T
Example:
ICS XXXX y F - LF T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
17
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil) (20 mil)
In Millimeters
COMMON DIMENSIONS
c
N
In Inches
COMMON DIMENSIONS
L
SYMBOL
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
SEE VARIATIONS
0.319 BASIC
.236
0.020 BASIC
.018 .030
SEE VARIATIONS
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
c
D
E
E1
e
L
N
E1
E
INDEX
AREA
1
2
SEE VARIATIONS
8.10 BASIC
6.00
0.50 BASIC
0.45
SEE VARIATIONS
0°
--
a
D
6.20
.244
0.75
A
α
8°
0.10
0°
--
8°
.004
A2
aaa
A1
- C -
VARIATIONS
D mm.
D (inch)
e
SEATING
PLANE
N
b
MIN
12.40
MAX
12.60
MIN
.488
MAX
.496
48
aaa
C
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS9FG108yGLF-T
Example:
ICS XXXX y G - LF T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
18
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Revision History
Rev.
Issue Date Description
1. Updated SMBus Byte 0 Bit 6 and 4.
Page #
C
6/1/2005 2. Updated LF Ordering Information to RoHS Compliant.
1. Corrected Pin-Type for Pin 5.
9, 15-16
D
E
F
1/13/2006 2. Corrected Revision History Rev. Sequence.
4/13/2006 1. Added +/- 150 ppm accuracy spec for 100 MHz outputs.
4/2/2007 Added Phase Jitter Table
2, 17
1, 6
14
G
4/6/2007 Updated Pin 26 Description.
4
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
800-345-7015
408-284-6578
408-284-8200
pcclockhelp@idt.com
Fax: 408-284-2775
Corporate Headquarters
Asia Pacific and Japan
Europe
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
+408 284 8200 (outside U.S.)
+65 6 887 5505
TM
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks
or registered trademarks used to identify products or services of their respective owners.
Printed in USA
19
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