ICSSSTV16857CL-T [IDT]
D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, 0.173 INCH, TVSOP-48;型号: | ICSSSTV16857CL-T |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, 0.173 INCH, TVSOP-48 光电二极管 逻辑集成电路 触发器 电视 |
文件: | 总8页 (文件大小:69K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ICSSSTV16857C
Integrated
Circuit
Systems, Inc.
DDR 14-Bit Registered Buffer
Recommended Applications:
Pin Configuration
•
DDR Memory Modules
•
Provides complete DDR DIMM logic solution with
ICS93V857 or ICS95V857
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK#
CLK
VDD
GND
VREF
RESET#
D8
•
SSTL_2 compatible data registers
Product Features:
•
Differential clock signal
•
•
•
Meets SSTL_2 signal data
Supports SSTL_2 class I & II specifications
Low-voltage operation
- VDD = 2.3V to 2.7V
48 pin TSSOP package
Q7
VDDQ
GND
Q8
Q9
•
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
D9
D10
D11
D12
VDD
GND
D13
D14
Truth Table1
Inputs
CLK CLK#
X or X or
Q Outputs
Q
RESET#
D
X or
L
L
Floating Floating Floating
48-Pin TSSOP & TVSOP
H
H
↑
↑
↓
↓
H
L
H
L
6.10 mm. Body, 0.50 mm. pitch = TSSOP
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
H
L or H
L or H
X
Q0(2)
Notes:
1.
H = High Signal Level
L = Low Signal Level
↑ = Transition LOW-to-HIGH
↓ = Transition HIGH -to LOW
X = Irrelevant
Block Diagram
2.
Output level before the indicated
steady state input conditions were
established.
38
39
CLK
CLK#
34
RESET#
R
1
Q1
CLK
48
35
D1
VREF
D1
To 13 Other Channels
0002F—10/25/02
ICSSSTV16857C
General Description
The 14-bit ICSSSTV16857C is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels,
except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#).The positive edge
of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an
LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTV16857C supports low-power
standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset to the logic
“Low”state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off.Please note that RESET# must always
be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic
“Low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable the
differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until the
input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
24, 23, 20, 19, 18,
15, 14, 11, 10, 7,
6, 5, 2, 1
Q (14:1)
OUTPUT
Data output
3, 8, 13, 22,
27, 36, 46
GND
PWR
PWR
Ground
4, 9, 12, 16, 21
VDDQ
Output supply voltage
25, 26, 29, 30, 31,
32, 33, 40, 41, 42,
43, 44, 47, 48
D (14:1)
INPUT
Data input
38
39
CLK
CLK#
INPUT
INPUT
PWR
Positive clock input
Negative clock input
Core supply voltage
Reset (active low)
28, 37, 45
34
VDD
RESET#
VREF
INPUT
INPUT
35
Input reference voltage
0002F—10/25/02
2
ICSSSTV16857C
Absolute Maximum Ratings
Notes:
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V
Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5
Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDDQ +0.5
Input Clamp Current . . . . . . . . . . . . . . . . . . . . ±50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous Output Current . . . . . . . . . . . . . . . ±50 mA
VDD, VDDQ or GND Current/Pin . . . . . . . . . . . . ±100 mA
1. The input and output negative voltage
ratings may be excluded if the input
andoutputclampratingsareobserved.
2. This current will flow only when the
output is in the high state level
V0 >VDDQ
.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Package Thermal Impedance3 . . . . . . . . . . . . . . . . 55°C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed in
the operational sections of the specifications is not implied.Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Recommended Operating Conditions
DESCRIPTION
PARAMETER
MIN
2.3
TYP
2.5
MAX
2.7
UNITS
Supply Voltage
VDD
I/O Supply Voltage
VDDQ
VREF
2.3
2.5
2.7
Reference Voltage
1.15
1.25
VREF
1.35
Termination Voltage
Input Voltage
VTT
VREF - 0.04
0
VREF + 0.04
VDDQ
VI
VIH (DC)
VIH (AC)
VIL (DC)
VIL (DC)
VIH
DC Input High Voltage
AC Input High Voltage
DC Input Low Voltage
AC Input Low Voltage
Input High Voltage Level
Input Low Voltage Level
Common mode Input Range
Differential Input Voltage
VREF + 0.15
VREF + 0.31
Data Inputs
V
VREF - 0.15
VREF - 0.31
1.7
RESET#
VIL
0.7
VICR
0.97
0.36
1.53
CLK, CLK#
VID
Cross Point Voltage of Differential Clock
Pair
VIX
(VDDQ/2) - 0.2
(VDDQ/2) + 0.2
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
IOH
IOL
TA
-20
20
70
mA
°C
0
1Guarenteed by design, not 100% tested in production.
0002F—10/25/02
3
ICSSSTV16857C
Electrical Characteristics - DC
TA = 0 - 70º C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated)
CONDITIONS
SYMBOL
VIK
PARAMETERS
VDDQ
2.3V
MIN
TYP MAX
-1.2
UNITS
V
II = -18mA
VDDQ
0.2
-
I
OH = -100µA
2.3V-2.7V
VOH
I
OH = -16mA
2.3V
2.3V-2.7V
2.3V
1.95
IOL = 100µA
0.2
0.35
±5
VOL
II
IOL = 16mA
All Inputs
VI = VDD or GND
RESET# = GND
VI = VIH(AC) or VIL(AC)
RESET# = VDD
2.7V
µA
µA
Standby (Static)
0.01
IDD
,
Operating (Static)
52
75
mA
RESET# = VDD
,
Dynamic operating
(clock only)
µA/clock
MHz
VI = VIH(AC) or VIL(AC)
,
CLK and CLK# switching
50% duty cycle.
IO = 0
2.7V
RESET# = VDD
,
IDDD
VI = VIH(AC) or VIL (AC)
,
CLK and CLK# switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
Dynamic Operating
(per each data input)
µA/ clock
MHz/data
15
rOH
rOL
Output High
Output Low
IOH = -20mA
2.3V-2.7V
2.3V-2.7V
7
7
13.5
13
20
20
Ω
Ω
IOL = 20mA
[rOH - rOL] each
separate bit
Data Inputs
rO(D)
I
O = 20mA, TA = 25° C
2.5V
2.5V
4
Ω
VI = VREF ±350mV
VICR = 1.25V, VI(PP) = 360mV
2.5
2.5
3.5
3.5
Ci
pF
CLK and CLK#
Notes:
1 - Guaranteed by design, not 100% tested in production.
0002F—10/25/02
4
ICSSSTV16857C
Timing Requirements1
(over recommended operating free-air temperature range, unless otherwise noted)
VDDQ = 2.5±0.2V
SYMBOL
PARAMETERS
UNITS
MIN
MAX
200
2.5
3.5
4
fclock
tPD
tRST
tSL
Clock frequency
MHz
ns
Clock to output time
Reset to output time
Output slew rate
Setup time, fast slew rate 2 & 4
Setup time, slow slew rate 3 & 4
Hold time, fast slew rate 2 & 4
Hold time, slow slew rate 3 & 4
1.7
ns
1
V/ns
ns
0.4
0.5
0.4
0.5
tS
Data before CLK↑ , CLK#↓
Data after CLK↑ , CLK#↓
ns
ns
Th
ns
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate ≥ 1V/ns.
3 - For data signal input slew rate ≥ 0.5V/ns and < 1V/ns.
4 - CLK, CLK# signals input slew rates are ≥ 1V/ns.
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
From
(Input)
To
(Output)
VDD = 2.5V ±0.2V
SYMBOL
UNITS
MIN
200
1.7
TYP
2.1
MAX
fmax
tPD
tphl
MHz
ns
CLK, CLK#
RESET#
Q
Q
2.5
3.5
ns
0002F—10/25/02
5
ICSSSTV16857C
VTT
RL 50Ω
=
From Output
Under Test
Test Point
CL = 30 pF
(see Note 1)
Load Circuit
LVCMOS
RESET#
Input
VDDQ
0 V
VDDQ/2
VDDQ/2
VI(pp)
Timing
Input
VICR
VICR
tinact
tact
IDDH
tPHL
tPHL
IDD
90%
(see note 2)
10%
VOH
VOL
IDDL
VTT
VTT
Voltage and Current Waveforms
Inputs Active and Inactive Times
Output
Voltage Waveforms - Propagation Delay Times
tw
VIH
VIL
Input
VREF
VREF
Voltage Waveforms - Pulse Duration
LVCMOS
RESET#
Input
VIH
VI(pp)
VDD/2
VIL
Timing
Input
VICR
tPHL
VOH
VOL
Output
th
tS
VTT
Voltage Waveforms - Propagation Delay Times
VIH
VIL
VREF
Input
VREF
Voltage Waveforms - Setup and Hold Times
Figure 1 - Parameter Measurement Information (V
= 2.5V ±0.2V)
DDQ
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDDQ or GND, and IO = 0 mA.
3. All input pulses are supplied by generators having the following characteristics: PRR @10 MHz,
Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDDQ/2
6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDDQ for LVCMOS input.
7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. tPLH and tPHL are the same as tpd
0002F—10/25/02
6
ICSSSTV16857C
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
22
E1
e
6.00
6.20
.236
0.020 BASIC
.244
a
0.50 BASIC
D
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
0°
--
8°
0.10
0°
--
8°
.004
α
aaa
A
A2
VARIATIONS
A1
D mm.
D (inch)
- CC --
N
MIN
12.40
MAX
12.60
MIN
.488
MAX
.496
e
SEATING
PLANE
48
b
Reference Doc.: JEDEC Publication 95, M O-153
aaa
C
10-0039
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
(240 mil)
Ordering Information
ICSSSTV16857CG-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0002F—10/25/02
7
ICSSSTV16857C
c
N
In Millimeters
In Inches
SYMBOL
L
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.13
0.09
MAX
1.20
0.15
1.05
0.23
0.20
MIN
--
.002
.032
.005
.0035
MAX
.047
.006
.041
.009
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
1
22
α
E1
e
4.30
4.50
.169
0.016 BASIC
.177
D
0.40 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
0°
--
8°
0.08
0°
--
8°
.003
α
aaa
A
A2
VARIATIONS
A1
D mm.
D (inch)
- CC --
N
MIN
9.60
MAX
9.80
MIN
.378
MAX
.386
e
SEATING
PLANE
48
b
Reference Doc.: JEDEC P ublicatio n 95, M O-153
aaa
C
10-0037
4.40 mm. Body, 0.40 mm. pitch TSSOP
(16 mil)
(173 mil)
Ordering Information
ICSSSTV16857CL-T
Example:
ICS XXXX y L - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
L = TSSOP (TVSOP)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0002F—10/25/02
8
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