ICSSSTV16857CYL-T [IDT]

Low Skew Clock Driver, 14 True Output(s), 0 Inverted Output(s), PDSO48, 4.40 MM, 0.40 MM PITCH, MO-153, TVSOP-48;


型号：	ICSSSTV16857CYL-T
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Low Skew Clock Driver, 14 True Output(s), 0 Inverted Output(s), PDSO48, 4.40 MM, 0.40 MM PITCH, MO-153, TVSOP-48 驱动光电二极管逻辑集成电路电视
文件：	总8页 (文件大小：81K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Integrated

Circuit

Systems, Inc.

ICSSSTV16857C

DDR 14-Bit Registered Buffer

Recommended Application:

DDR Memory Modules

Product Features:

Pin Configuration

GND

VDDQ

GND

VDDQ

GND

VDD

CLK#

CLK

VDD

GND

VREF

RESET#

•

Differential clock signal

Meets SSTL_2 signal data

Supports SSTL_2 class I & II specifications

Low-voltage operation

VDD = 2.3V to 2.7V

•

48 pin TSSOP package

VDDQ

GND

Truth Table¹

VDDQ

GND

Q10

Q11

Q12

VDDQ

GND

Q13

Q14

D10

D11

D12

VDD

GND

D13

D14

Inputs

CLK#

Q Outputs

RESET#

CLK

X or

Floating

X or

Floating

X or

Floating

Q₀⁽²⁾

↑

↓

48-Pin TSSOP & TVSOP

6.10 mm. Body, 0.50 mm. pitch = TSSOP

L or H

4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)

Notes:

H = High Signal Level

L = Low Signal Level

↑ = Transition LOW-to-HIGH

↓ = Transition HIGH -to LOW

X = Irrelevant

Output level before the indicated

steady state input conditions were

established.

Block Diagram

CLK

CLK#

RESET#

CLK

VREF

To 13 Other Channels

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

16857C Rev C 11/21/01

Third party brands and names are the property of their respective owners.

information being relied upon by the customer is current and accurate.

ICSSSTV16857C

General Description

The 14-bit ICSSTV16857 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels

except for the RESET# input which is LVCMOS.

Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the

positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supported with LVCMOS

levels as VREF may not be stable during power-up. RESET# is asynchronous and is intended for power-up only and

when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and

clock are switched off.

Pin Configuration

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

24, 23, 20, 19, 18,

15, 14, 11, 10, 7, 6,

5, 2, 1

Q (14:1)

OUTPUT

Data output

3, 8, 13, 22,

27, 36, 46

GND

PWR

Ground

4, 9, 12, 16, 21

VDDQ

Output supply voltage

25, 26, 29, 30, 31,

32, 33, 40, 41, 42,

43, 44, 47, 48

D (14:1)

INPUT

Data input

CLK

CLK#

VDD

INPUT

PWR

Positive clock input

Negative clock input

Core supply voltage

Reset (active low)

28, 37, 45

RESET#

VREF

INPUT

Input reference voltage

Third party brands and names are the property of their respective owners.

ICSSSTV16857C

Absolute Maximum Ratings

Notes:

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V

Input Voltage¹. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5

Output Voltage^1,2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDDQ +0.5

Input Clamp Current . . . . . . . . . . . . . . . . . . . . . . . ±50 mA

Output Clamp Current . . . . . . . . . . . . . . . . . . . . . ±50mA

Continuous Output Current . . . . . . . . . . . . . . . . . ±50mA

VDD, VDDQ or GND Current/Pin . . . . . . . . . . . . ±100mA

1. The input and output negative voltage

ratings may be excluded if the input

and output clamp ratings are observed.

2. This current will flow only whtn the

output is in the high state level

V₀>V_DDQ

3. The package thermal impedance is

calculated in accordance with

JESD 51.

Package Thermal Impedance³. . . . . . . . . . . . . . . . . . . . 55°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only and functional operation of the device at these or any other conditions above those listed in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect product reliability.

Recommended Operating Conditions

PARAMETER

DESCRIPTION

MIN

2.3

TYP

2.5

MAX

2.7

UNITS

Supply Voltage

V_DD

I/O Supply Voltage

V_DDQ

V_REF

V_TT

2.3

2.5

2.7

Reference Voltage V_REF= 0.5X V_DDQ

Termination Voltage

Input Voltage

1.15

1.25

V_REF

1.35

V_REF-0.04

V_DD

V_I

V_IH

DC Input High Voltage

AC Input High Voltage

V_REF+0.15

V_REF+0.31

V_IH

Data Inputs

V_IL

DC Input Low Voltage

V_REF-0.15

V_REF-0.31

V_IL

AC Input Low Voltage

V_IH

Input High Voltage Level

Input Low Voltage Level

Common mode Input Range

Differential Input Voltage

1.7

RESET#

V_IL

0.7

V_ICR

V_ID

0.97

0.36

1.53

CLK, CLK#

Cross Point Voltage of Differential Clock

Pair

(V_DDQ/2)

+0.2

-20

V_IX

(V_DDQ/2) -0.2

High-Level Output Current

Low-Level Output Current

Operating Free-Air Temperature

I_OH

I_OL

T_A

°C

¹Guarenteed by design, not 100% tested in production.

Third party brands and names are the property of their respective owners.

ICSSSTV16857C

Electrical Characteristics - DC

T_A= 0 - 70º C; V_DD= 2.5 V +/-200mV, V_DDQ=2.5V 200mV; (unless otherwise stated)

SYMBOL

V_IK

PARAMETERS

CONDITIONS

I_I= -18mA

I_OH= -100µA

_OH= -16mA

VDD

2.3V

MIN

TYP MAX

-1.2

UNITS

2.3V-2.7 VDD -0.2

V_OH

2.3V

2.3-2.7V

2.3V

1.95

I_OL= 100µA

0.2

0.35

±5

V_OL

I_I

I_OL= 16mA

All Inputs

V_I= V_DDor GND

RESET# = GND

V_I= V_{IH (AC#)}or V_{IL (AC)}

RESET# = V_DD

2.7V

µA

Standby (Static)

0.01

I_DD

Operating (Static)

RESET# = V_DD, V_I= V_IH(AC)

or V_{IL (AC)}, CK and CK#

switching 50% duty cycle.

RESET# = V_DD, V_I= V_IH(AC)

or V_{IL (AC)}, CK and CK#

switching 50% duty cycle.

One data input switching at

half clock frequency, 50%

duty cycle

Dynamic operating

clock only

µA/clock MHz

IO = 0

2.7V

I_DDD

µA/ clock

MHz/data

Dynamic Operating

per each data input

r_OH

r_OL

Output High

Output Low

[r_OH- r_OL] each

separate bit

Data Inputs

CK and CK#

I_OH= -20mA

2.3-2.7V

I_OL= 20mA

r_O(D)

I_O= 20mA, T_A= 25° C

V_I= V_REF±310mV

2.5V

2.5

3.5

C_i

V_ICR= 1.25V, V_I(PP)= 360mV

Notes:

1 - Guaranteed by design, not 100% tested in production.

Third party brands and names are the property of their respective owners.

ICSSSTV16857C

Timing Requirements

(over recommended operating free-air temperature range, unless otherwise noted)

SYMBOL

PARAMETERS

VDD=2.5±0.2V

UNITS

MIN

TYP

133

MAX

200

2.6

3.3

f_clock

t_PD

t_RST

t_SL

Clock frequency

MHz

Clock to output time

Reset to output time

Output slew rate

1.6

2.5

2.7

1.5

V/ns

Setup time, fast slew rate ^{2, 4}

Data before CK , CK#

! "

0.75

0.9

0.75

0.9

0.018

3, 4

Setup time, slow slew rate

t_SU

2,4

Hold time, fast slew rate

Hold time, slow slew rate

Data after CK , CK#

! "

0.145

3, 4

T_h

Notes:

1 - Guaranteed by design, not 100% tested in production.

2 - For data signal input slew rate ?1V/ns.

4 - CLK, CLK# signals input slew rates are ?1V/ns.

3 - For data signal input slew rate ?0.5V/ns and < 1V/ns.

Switching Characteristics

(over recommended operating free-air temperature range, unless otherwise noted)

SYMBOL

From

VDD=2.5±0.2V

UNITS

(Input)

(Output)

MIN

TYP

133

MAX

f_clock

t_PD

200

2.6

3.3

MHz

CLK, CLK#

RESET

1.6

2.5

t_ph1

2.7

Third party brands and names are the property of their respective owners.

ICSSSTV16857C

V_TT

R_L5W0

From Output

Under Test

Test Point

C_L= 30 pF

(see Note 1)

Load Circuit

LVCMOS

RESET#

Input

V_DD

0 V

V_DD/2

V_I(pp)

Timing

Input

V_ICR

t_inact

t_act

I_DDH

t_PHL

I_DD

90%

(see note 2)

10%

V_OH

V_OL

I_DDL

V_TT

Voltage and Current Waveforms

Inputs Active and Inactive Times

Output

Voltage Waveforms - Propagation Delay Times

t_w

V_IH

V_IL

Input

V_REF

Voltage Waveforms - Pulse Duration

LVCMOS

RESET#

Input

V_IH

V_IL

V_I(pp)

DD/2

Timing

Input

V_ICR

t_PHL

V_OH

V_OL

Output

t_h

t_SU

V_TT

Voltage Waveforms - Propagation Delay Times

V_IH

V_IL

V_REF

Input

V_REF

Voltage Waveforms - Setup and Hold Times

Parameter Measurement Information (V_DD= 2.5V ±±.2Vꢀ

Notes: 1. CL incluces probe and jig capacitance.

2. I_DDtested with clock and data inputs held at V_DDor GND, and Io = 0mA.

3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz, Zo=50Ω, input

slew rate = 1 V/ns ±20% (unless otherwise specified).

4. The outputs are measured one at a time with one transition per measurement.

5. V_TT= V_REF= V_DDQ/2

6. V_IH= V_REF+ 310mV (ac voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS input.

7. V_IL= V_REF-310mV (ac voltage levels) for differential inputs. V_IL= GND for LVCMOS input.

8. t_PLHand t_PHLare the same as t_pd

Third party brands and names are the property of their respective owners.

ICSSSTV16857C

In Millimeters

In Inches

SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS

MIN

0.05

0.80

0.17

0.09

MAX

1.20

0.15

1.05

0.27

0.20

MIN

.002

.032

.007

.0035

MAX

.047

.006

.041

.011

.008

INDEX

AREA

SEE VARIATIONS

8.10 BASIC

SEE VARIATIONS

0.319 BASIC

6.00

6.20

.236

.244

0.50 BASIC

0.020 BASIC

0.45

0.75

.018

.030

SEE VARIATIONS

aaa

0°

8°

0.10

0°

8°

.004

VARIATIONS

- CC -

D mm.

D (inch)

MIN

12.40

MAX

12.60

MIN

.488

MAX

.496

SEATING

PLANE

Reference Doc.: JEDEC Publication 95, MO-153

aaa

10-0039

6.10 mm. Body, 0.50 mm. pitch TSSOP

(0.020 mil)

(240 mil)

Ordering Information

ICSSSTV16857CyG-T

Example:

ICS XXXX y G - PPP - T

Designation for tape and reel packaging

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

G=TSSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

Third party brands and names are the property of their respective owners.

information being relied upon by the customer is current and accurate.

ICSSSTV16857C

In Millimeters

In Inches

SYMBOL

COMMON DIMENSIONS COMMON DIMENSIONS

MIN

0.05

0.80

0.13

0.09

MAX

1.20

0.15

1.05

0.23

0.20

MIN

.002

.032

.005

.0035

MAX

.047

.006

.041

.009

.008

INDEX

AREA

SEE VARIATIONS

6.40 BASIC

SEE VARIATIONS

0.252 BASIC

4.30

4.50

.169

.177

0.40 BASIC

0.016 BASIC

0.45

0.75

.018

.030

SEE VARIATIONS

aaa

0°

8°

0.08

0°

8°

.003

VARIATIONS

D mm.

D (inch)

- C -

MIN

9.60

MAX

9.80

MIN

.378

MAX

.386

SEATING

PLANE

Reference Doc.: JEDEC Publication 95, MO-153

aaa

10-0037

4.40 mm. Body, 0.40 mm. pitch TSSOP

(16 mil)

(173 mil)

Ordering Information

ICSSSTV16857CyL-T

Example:

ICS XXXX y L - PPP - T

Designation for tape and reel packaging

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

L=TSSOP (TVSOP)

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

Third party brands and names are the property of their respective owners.

information being relied upon by the customer is current and accurate.

ICSSSTV16857CYL-T [IDT]

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