IDT10504S7C [IDT]

Standard SRAM, 64KX4, 7ns, CDIP32;


型号：	IDT10504S7C
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Standard SRAM, 64KX4, 7ns, CDIP32 CD 静态存储器内存集成电路
文件：	总7页 (文件大小：83K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT10504

IDT100504

IDT101504

HIGH-SPEED BiCMOS

ECL STATIC RAM

256K (64K x 4-BIT) SRAM

Integrated Device Technology, Inc.

These devices are part of a family of asynchronous four-

bit-wide ECL SRAMs. The devices have been configured to

follow the standard ECL SRAM JEDEC pinout. Because they

are manufactured in BiCEMOS technology, power dissipa-

tion is greatly reduced over equivalent bipolar devices. Low

power operation provides higher system reliability and makes

possible the use of the plastic SOJ package for high-density

surface mount assembly.

The fast access time and guaranteed Output Hold time

allowgreatermarginforsystemtimingvariation. DataINsetup

time specified with respect to the trailing edge of Write Pulse

eases write timing allowing balanced Read and Write cycle

times.

FEATURES:

• 65,536-words x 4-bit organization

• Address access time: 7/8/10/12/15 ns

• Low power dissipation: 1000mW (typ.)

• Guaranteed Output Hold time

• Fully compatible with ECL logic levels

• Separate data input and output

• Standard through-hole and surface mount packages

• Guaranteed-performance die available for MCMs/hybrids

DESCRIPTION:

The IDT10504, IDT100504 and IDT101504 are 262,144-

bit high-speed BiCEMOS

ECL static random access

memories organized as 64Kx4, with separate data inputs and

outputs. All I/Os are fully compatible with ECL levels.

FUNCTIONAL BLOCK DIAGRAM

65,536-BIT

MEMORY

ARRAY

VCC

VEE

DECODER

A15

SENSE AMPS

AND READ/WRITE

CONTROL

2780 drw 01

BiCEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

SEPTEMBER 1992

1992 Integrated Device Technology, Inc.

IDT10504, IDT100504, IDT101504

HIGH-SPEED BiCMOS ECL STATIC RAM 256K (64K x 4-BIT) SRAM

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION

PACKAGES

30 NC

29 NC

300-Mil-Wide

PLASTIC SOJ PACKAGE

SO32-2

400-Mil-Wde

CERAMIC PACKAGE

C32-2

2780 drw 04

2780 drw 03

2780 drw 02

Top View

PIN DESCRIPTIONS

Symbol

Pin Name

A0 through A15

D0 through D3

Q0 through Q3

Address Inputs

Data Inputs

Data Outputs

Hi-Rel Die

For Hybrid and MCM

Applications

Write Enable Input

Chip Select Input (Internal pull down)

More Negative Supply Voltage

Less Negative Supply Voltage

2780 drw 05

VEE

VCC

2780 tbl 01

LOGIC SYMBOL

CAPACITANCE (TA = +25°C, f = 1.0MHz)

DIP

Typ.

SOJ

D0 D1 D2 D3

Symbol Parameter

Max.

—

Typ.

Max. Unit

CIN

Input

Capacitance

—

COUT

Output

Capacitance

—

2780 tbl 02

TRUTH TABLE⁽¹⁾

DataOUT

Function

Deselected

Read

A10

A11

A12

A13

A14

A15

RAM Data

Write

NOTE:

1. H=High, L=Low, X=Don’t Care

2780 tbl 03

CS WE

2780 drw 06

IDT10504, IDT100504, IDT101504

HIGH-SPEED BiCMOS ECL STATIC RAM 256K (64K x 4-BIT) SRAM

COMMERCIAL TEMPERATURE RANGE

(1)

ABSOLUTE MAXIMUM RATINGS

AC/DC ELECTRICAL OPERATING RANGES

Symbol

Rating

Value

Unit

I/O

VEE

10K

100K

-5.2V ± 5%

-4.5V ± 5%

0 to +75°C, air flow exceeding 2 m/sec

0 to +85°C, air flow exceeding 2 m/sec

VTERM

Terminal Voltage

With Respect to GND

+0.5 to -7.0

Operating

Temperature

10K

100K

101K

0 to +75

0 to +85

0 to +75

°C

101K -4.75V to -5.46V 0 to +75°C, air flow exceeding 2 m/sec

2780 tbl 05

TBIAS

TSTG

Temperature Under Bias

-55 to +125

°C

Storage Ceramic

Temperatuure Plastic

Power Dissipation

-65 to +150

-55 to +125

1.5

-50

IOUT

DC Output Current

(Output High)

NOTE:

2780 tbl 04

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating

onlyandfunctionaloperationofthedeviceattheseoranyotherconditions

above those indicated in the operational sections of this specification is

not implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS (1)

10K

100K/101K

Min.

Symbol

Parameter

Min.

Max.

Unit

VOH

Output HIGH Voltage

(VIN= VIH(Max) or VIL(Min))

-1000

-960

-900

-840

-810

-720

0°C

25°C

75°C

-1025

-1810

-1035

—

-880

VOL

VOHC

VOLC

VIH

VIL

Output LOW Voltage

(VIN= VIH(Max) or VIL(Min))

-1870

-1850

-1830

-1665

-1650

-1625

0°C

25°C

75°C

-1620

—

Output Threshold HIGH Voltage

(VIN= VIH(Min) or VIL(Max))

-1020

-980

-920

—

0°C

25°C

75°C

Output Threshold LOW Voltage

(VIN= VIH(Min) or VIL(Max))

—

-1645

-1630

-1605

0°C

25°C

75°C

-1610

-880

-1475

Input HIGH Voltage

(Guaranteed Input Voltage

High for All Inputs)

-1145

-1105

-1045

-840

-810

-720

0°C

25°C

75°C

-1165

-1810

Input LOW Voltage

(Guaranteed Input Voltage

Low for All Inputs)

-1870

-1850

-1830

-1490

-1475

-1450

0°C

25°C

75°C

IIH

Input HIGH Current

VIN= VIH(Max)

Others

—

220

110

—

220

110

µA

IIL

Input LOW Current

VIN= VIL(Min)

Others

0.5

-50

170

—

0.5

-50

170

µA

IEE

Supply Current

-220

—

-200 (100K)

-220 (101K)

—

NOTE:

1. RL = 50Ω to -2V, air flow exceeding 2 m/sec.

IDT10504, IDT100504, IDT101504

HIGH-SPEED BiCMOS ECL STATIC RAM 256K (64K x 4-BIT) SRAM

COMMERCIAL TEMPERATURE RANGE

AC TEST LOAD CONDITION

AC TEST INPUT PULSE

VCC (GND)

DATAOUT

-0.9V

-1.7V

80%

20%

50Ω

tR = tF = 1.5ns typ.

0.01µF

-2.0V

VEE

Note: All timing measurements are

referenced to 50% input levels.

2780 drw 07

*Includes probe and jig capacitance.

C < 5pF (7ns speed grade)

C < 30pF (all other speed grades)

2780 drw 08

RISE/FALL TIME

Symbol Parameter

Min.

—

Typ.

Max.

—

Unit

Output Rise Time

Output Fall Time

1.5

—

2780 tbl 06

FUNCTIONAL DESCRIPTION

The IDT10504, IDT100504, and IDT101504 BiCEMOS

ECL static RAMs provide high speed with low power dissipa-

WRITE TIMING

To write data to the device, a Write Pulse need be formed

tion typical of BiCMOS ECL. These devices follow the on the Write Enable input (WE) to control the write to the

conventional center power pinout and functionality for 64Kx4 SRAM array. While CS and ADDR must be set-up when WE

ECL SRAMs.

goes low, DataIN can settle after the falling edge ofWE, giving

the data path extra margin. Data is written to the memory cell

at the end of the Write Pulse, and addresses and Chip Select

must be held after the rising edge of the Write Pulse to ensure

satisfactory completion of the cycle.

DataOUT is disabled (held low) during the Write Cycle. If

CS is held low (active) and addresses remain unchanged, the

Data OUT pins will output the written data after "Write Recov-

ery time" (tWR).

READ TIMING

The read timing on these asynchronous devices is straight-

forward. DataOUT is held low until the device is selected by

Chip Select (CS). The Address (ADDR) settles and data

appears on the output after time tAA. Note that DataOUT is

held for a short time (tOH) after the address begins to change

for the next access, then ambiguous data is on the bus until a

new time tAA.

Because of the very short Write Pulse requirement, these

devices can be cycled as quickly for Writes as for Reads.

IDT10504, IDT100504, IDT101504

HIGH-SPEED BiCMOS ECL STATIC RAM 256K (64K x 4-BIT) SRAM

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)

S10

S12, 15

(1)

Symbol Parameter

Read Cycle

Min. Max. Min. Max. Min. Max. Min. Max. Unit

tACS

tRCS

tAA

Chip Select Access Time

Chip Select Recovery Time

Address Access Time

—

tOH

Data Hold from Address

Change

—

NOTE:

2780 tbl 07

1. Input and Output reference level is 50% point of waveform.

2. Output load capacitance, C < 5pF (7ns speed grade only), see "AC Load Test Condition" on previous page.

READ CYCLE GATED BY CHIP SELECT (1, 2)

tACS

tRCS

DATAOUT

2780 drw 09

READ CYCLE GATED BY ADDRESS (1, 3)

ADDR

tAA

tOH

DATAOUT

2780 drw 10

NOTE:

1. WE is high for read cycle.

2. Address valid prior to or minimum of tAA-tACS beforeCS active.

3. CS active prior to or minimum tAA-tACS after address valid.

IDT10504, IDT100504, IDT101504

HIGH-SPEED BiCMOS ECL STATIC RAM 256K (64K x 4-BIT) SRAM

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)

S10

S12, 15

(1)

Symbol Parameter

Write Cycle

Min. Max. Min. Max. Min. Max. Min. Max. Unit

Write Pulse Width

(tWSA = minimum)

—

tWSD

tWSD2

tWSA

Data Set-up Time

—

(2)

Data Set-up Time to WE High

Address Set-up Time

(tW = minimum)

tWSCS

tWHD

Chip Select Set-up Time

Data Hold Time

—

tWHA

tWHCS

tWS

Address Hold Time

Chip Select Hold Time

Write Disable Time

Write Recovery Time

—

(3)

tWR

NOTE:

2780 tbl 08

1. Input and Output reference level is 50% point of waveform.

2. tWSD is specified with respect to the falling edge of WE for compatibility with bipolar part specifications, but this device actually only requires tWSD2 with

respect to rising edge of WE.

3. tWR is defined as the time to reflect the newly written data on the Data Outputs (Q0 to Q3) when no new Address Transition occurs.

WRITE CYCLE TIMING DIAGRAM

tWSCS

tWSA

tWSD

tWHCS

tWHA

tWHD

ADDR

DATAIN

tWSD2

tWS

tWR

DATAOUT

2780 drw 11

IDT10504, IDT100504, IDT101504

HIGH-SPEED BiCMOS ECL STATIC RAM 256K (64K x 4-BIT) SRAM

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

nnnnn

IDT

Device Type Architecture

Speed Package

Process/

Temp. Range

Blank

Commercial

U(1)

Sidebraze DIP

Hi-Rel Die for MCMs and/or Hybrids

Plastic SOJ

Speed in Nanoseconds

Standard Architecture

10504

256K (64K x 4-bits) BiCMOS ECL-10K

Static RAM

100504 256K (64K x 4-bits) BiCMOS

ECL-100K Static RAM

101504 256K (64K x 4-bits) BiCMOS

ECL-101K Static RAM

2780 drw 12

NOTE:

1. Please contact your IDT Sales Representative for more information on

specifications and availability of Die products.

Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible product.

Integrated Device Technology, Inc.

2975 Stender Way, Santa Clara, CA 95054-3090

Telephone: (408) 727-6116

FAX 408-492-8674

IDT10504S7C [IDT]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E