IDT54FCT373AP [IDT]
FAST CMOS OCTAL TRANSPARENT LATCHES; 快速CMOS八路透明锁存器
| 型号： | IDT54FCT373AP |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS OCTAL TRANSPARENT LATCHES |
| 文件： | 总8页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT373/A/C
IDT54/74FCT533/A/C
IDT54/74FCT573/A/C
FAST CMOS OCTAL
TRANSPARENT LATCHES
Integrated Device Technology, Inc.
FEATURES
• IDT54/74FCT373/533/573 equivalent to FAST speed
DESCRIPTION
The IDT54/74FCT373/A/C, IDT54/74FCT533/A/C and
IDT54/74FCT573/A/C are octal transparent latches built us-
ing an advanced dual metal CMOS technology. These octal
latcheshave3-stateoutputsandareintendedforbusoriented
applications. The flip-flops appear transparent to the data
when Latch Enable (LE) is HIGH. When LE is LOW, the data
that meets the set-up time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OEis HIGH, the
bus output is in the high-impedance state.
and drive
• IDT54/74FCT373A/533A/573A up to 30% faster than
FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typ. static)
• Octal transparent latch with 3-state output control
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAMS
IDT54/74FCT373 AND IDT54/74FCT573
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D7
D
D
D
D
D
D
D
D
O
O
O
O
O
O
O
O
G
G
G
G
G
G
G
G
LE
OE
O
0
O1
O2
O3
O4
O5
O
6
O7
2602 cnv* 01
IDT54/74FCT533
D0
D1
D2
D3
D4
D5
D6
D7
D
D
D
D
D
D
D
D
O
O
O
O
O
O
O
O
G
G
G
G
G
G
G
G
LE
OE
O0
O1
O2
O3
O4
O5
O6
O7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
2602 cnv* 02
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1992
1992 Integrated Device Technology, Inc.
7.12
DSC-4624/2
1
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT373
INDEX
OE
1
20
19
18
17
16
15
14
13
12
11
VCC
O7
D7
O0
D0
D1
2
3
4
3
2
20 19
1
D6
4
5
6
7
8
18
P20-1
D20-1
SO20-2
&
D1
D7
D6
O6
O1
O2
5
17
16
15
14
O1
O2
6
O5
D5
D4
O6
O5
L20-2
D2
D3
7
D2
D3
E20-1
8
D5
9 10 11 12 13
O3
9
O4
LE
GND
10
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
IDT54/74FCT573
INDEX
1
20
19
18
17
V
CC
OE
D
0
2
3
4
O
O
O
O
O
0
1
2
3
4
D
D
1
2
3
2
20 19
1
4
5
6
7
8
18
D
2
3
4
O
1
2
3
4
5
P20-1
17
16
15
14
D
D
D
D
D
3
4
5
6
7
5
D20-1 16
D
D
O
O
O
O
SO20-2
6
15
&
14
L20-2
7
O
5
6
D
D
5
6
E20-1
O
8
13
12
11
9 10 11 12 13
9
O
7
GND
10
LE
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
IDT54/74FCT533
INDEX
OE
O0
D0
D1
O1
1
20
19
18
17
VCC
O7
D7
2
3
4
3
2
20 19
1
D6
D1
4
18
17
16
15
14
D7
D6
P20-1
5
D20-1 16
O6
O5
D5
D4
O4
LE
5
6
7
8
O1
O2
D2
D3
SO20-2
O2
D2
6
15
&
14
L20-2
O6
7
O5
D5
E20-1
D3
8
13
12
11
9 10 11 12 13
O3
9
GND
10
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
2602 cnv* 03–08
7.12
2
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE (FCT373 and FCT573)(1)
FUNCTION TABLE (FCT533)(1)
Inputs
Outputs
Inputs
LE
Outputs
ON
DN
H
LE
H
N
O
DN
H
OE
L
OE
L
L
H
H
X
H
L
L
H
L
H
Z
L
L
X
X
H
X
H
Z
NOTE:
2602 tbl 06
NOTE:
2602 tbl 05
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
Z = High Impedance
PIN DESCRIPTION
Pin Names
Description
DN
LE
OE
ON
ON
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-State Outputs
Complementary 3-State Outputs
2602 tbl 07
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
Military
Unit
Symbol
Parameter
Input
Capacitance
Output
Conditions
Typ. Max. Unit
(2)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to +7.0
–0.5 to +7.0
V
CIN
VIN = 0V
6
10
pF
COUT
VOUT = 0V
8
12
pF
(3)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to VCC
–0.5 to VCC
V
Capacitance
NOTE:
2602 tbl 02
1. This parameter is measured at characterization but not tested.
TA
Operating
0 to +70
–55 to +125
–65 to +135
–65 to +150
°C
°C
°C
Temperature
Temperature
Under Bias
Storage
TBIAS
TSTG
–55 to +125
–55 to +125
Temperature
Power Dissipation
PT
0.5
0.5
W
IOUT
DC Output
Current
120
120
mA
NOTES:
2602 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
7.12
3
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
0.8
5
V
VIL
II H
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH Current
VCC = Max.
VI = VCC
—
—
µA
VI = 2.7V
VI = 0.5V
VI = GND
VO = VCC
VO = 2.7V
VO = 0.5V
VO = GND
—
—
5(4)
–5(4)
–5
II L
Input LOW Current
—
—
—
—
IOZH
IOZL
Off State (High Impedance)
Output Current
VCC = Max.
—
—
10
µA
—
—
10(4)
–10(4)
–10
–1.2
—
—
—
—
—
VIK
IOS
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
VCC = Min., IN = –18mA
VCC = Max.(3), VO = GND
—
–0.7
–120
VCC
VCC
4.3
4.3
GND
V
mA
V
–60
VHC
VHC
2.4
2.4
—
VOH
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
—
VCC = Min.
IOH = –300µA
—
VIN = VIH or VIL
IOH = –12mA MIL.
IOH = –15mA COM'L.
—
—
VOL
Output LOW Voltage
VCC = 3V, VIN = VLC or VHC, IOL = 300µA
VLC
(4)
V
VCC = Min.
IOL = 300µA
—
GND VLC
VIN = VIH or VIL
IOL = 32mA MIL.
IOL = 48mA COM'L.
—
0.3
0.3
0.5
0.5
—
NOTES:
2602 tbl 03
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.12
4
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
Quiescent Power Supply Current
VCC = Max.
VIN ≥ VHC; V IN ≤ VLC
ICC
—
0.2
1.5
mA
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
∆ICC
—
—
0.5
2.0
mA
VIN = 3.4V(3)
VCC = Max.
ICCD
Dynamic Power Supply
Current(4)
VIN ≥ VHC
VIN ≤ VLC
0.15
0.25
mA/
MHz
Outputs Open
OE = GND
One Input Toggling
50% Duty Cycle
VCC = Max.
Outputs Open
fi = 10MHz
IC
Total Power Supply Current(6)
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
—
1.7
2.0
4.0
5.0
mA
50% Duty Cycle
OE = GND
VIN = 3.4V
VIN = GND
LE = VCC
One Bit Toggling
VCC = Max.
Outputs Open
fi = 2.5MHz
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
—
3.2
5.2
6.5(5)
50% Duty Cycle
OE = GND
VIN = 3.4V
VIN = GND
14.5(5)
LE = VCC
Eight Bits Toggling
NOTES:
2602 tbl 04
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
7.12
5
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT373/A/C/FCT573/A/C
FCT373/573
Com'l.(2) Mil.(2)
FCT373A/573A
Com'l.(2) Mil.(2)
FCT373C/573C
Com'l. (2) Mil.(2)
Symbol
Parameter
Propagation Delay
DN to ON
Conditions(1)
CL = 50pF
RL = 500Ω
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tPLH
tPHL
1.5 8.0 1.5 8.5 1.5 5.2 1.5 5.6 1.5 4.2 1.5 5.1 ns
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Propagation Delay
LE to ON
2.0 13.0 2.0 15.0 2.0 8.5 2.0 9.8 2.0 5.5 2.0 8.0 ns
1.5 12.0 1.5 13.5 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.3 ns
1.5 7.5 1.5 10.0 1.5 5.5 1.5 6.5 1.5 5.0 1.5 5.9 ns
Output Enable Time
Output Disable Time
Set-up Time HIGH
or LOW, DN to LE
Hold Time HIGH
or LOW, DN to LE
LE Pulse Width HIGH
2.0
1.5
6.0
—
—
—
2.0
1.5
6.0
—
—
—
2.0
1.5
5.0
—
—
—
2.0
1.5
6.0
—
—
—
2.0
1.5
5.0
—
—
—
2.0
1.5
6.0
—
—
—
ns
ns
tH
tW
ns
2602 tbl 08
SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT533/A/C
FCT533
Com'l.(2) Mil.(2)
FCT533A
Com'l.(2) Mil.(2)
FCT533C
Com'l.(2) Mil.(2)
Symbol
tPLH
Parameter
Propagation Delay
DN to ON
Conditions(1)
CL = 50pF
RL = 500Ω
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
1.5 10.0 1.5 12.0 1.5 5.2 1.5 5.6 1.5 4.7 1.5 5.1 ns
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Propagation Delay
LE to ON
2.0 13.0 2.0 14.0 2.0 8.5 2.0 9.8 2.0 6.9 2.0 8.0 ns
1.5 11.0 1.5 12.5 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.3 ns
1.5 7.0 1.5 8.5 1.5 5.5 1.5 6.5 1.5 5.0 1.5 5.9 ns
Output Enable Time
Output Disable Time
Set-up Time HIGH
or LOW, DN to LE
Hold Time HIGH
or LOW, DN to LE
LE Pulse Width HIGH
2.0
1.5
6.0
—
—
—
2.0
1.5
6.0
—
—
—
2.0
1.5
5.0
—
—
—
2.0
1.5
6.0
—
—
—
2.0
1.5
5.0
—
—
—
2.0
1.5
6.0
—
—
—
ns
ns
tH
tW
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2602 tbl 09
7.12
6
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC
SWITCH POSITION
Test
Switch
Closed
Open
7.0V
Open Drain
Disable Low
Enable Low
500Ω
V OUT
VIN
Pulse
Generator
D.U.T.
All Other Tests
50pF
C L
500Ω
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
2537 tbl 10
RT
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
1.5V
0V
DATA
INPUT
tSU
t H
LOW-HIGH-LOW
1.5V
3V
1.5V
0V
TIMING
INPUT
PULSE
t W
ASYNCHRONOUS CONTROL
t REM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
3V
1.5V
0V
tH
t SU
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
3V
CONTROL
INPUT
1.5V
0V
SAME PHASE
INPUT TRANSITION
1.5V
0V
tPZL
tPLZ
tPHL
tPLH
3.5V
1.5V
3.5V
OUTPUT
NORMALLY
LOW
VOH
SWITCH
CLOSED
OUTPUT
1.5V
0.3V
0.3V
VOL
VOH
tPZH
tPHZ
VOL
tPLH
tPHL
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
3V
1.5V
0V
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
0V
NOTES
2537 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.12
7
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
FCT
XXXX
X
X
Temp. Range
Device Type
Package
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
SO
L
E
Small Outline IC
Leadless Chip Carrier
CERPACK
373
Non-Inverting Octal Transparent Latch
573
Non-Inverting Octal Transparent Latch
533
Inverting Octal Transparent Latch
373A
573A
533A
373C
573C
533C
Fast Non-Inverting Octal Transparent Latch
Fast Non-Inverting Octal Transparent Latch
Fast Inverting Octal Transparent Latch
Super Fast Non-Inverting Octal Transparent Latch
Super Fast Non-Inverting Octal Transparent Latch
Super Fast Inverting Octal Transparent Latch
54
74
–55
°C to +125°C
C to +70°C
0°
2602 cnv* 14
7.12
8
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