IDT5T93GL161PFGI8 [IDT]
Low Skew Clock Driver, 5T Series, 16 True Output(s), 0 Inverted Output(s), CMOS, PQFP64, GREEN, TQFP-64;
| 型号： | IDT5T93GL161PFGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 5T Series, 16 True Output(s), 0 Inverted Output(s), CMOS, PQFP64, GREEN, TQFP-64 |
| 文件： | 总20页 (文件大小：871K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5V LVDS, 1:16 GLITCHLESS CLOCK BUFFER
TERABUFFER™ II
IDT5T93GL161
General Description
Features
The IDT5T93GL161 2.5V differential clock buffer is a
• Guaranteed low skew: <75ps (maximum)
user-selectable differential input to sixteen LVDS outputs. The
fanout from a differential input to sixteen LVDS outputs reduces
loading on the preceding driver and provides an efficient clock
distribution network. The IDT5T93GL161 can act as a translator
from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V
/ 2.5V LVTTL input can also be used to translate to LVDS outputs.
The redundant input capability allows for a glitchless change-over
from a primary clock source to a secondary clock source.
Selectable inputs are controlled by SEL. During the switchover,
the output will disable LOW for up to three clock cycles of the
previously-selected input clock. The outputs will remain LOW for
up to three clock cycles of the newly-selected clock, after which
the outputs will start from the newly-selected input. A FSEL pin
has been implemented to control the switchover in cases where a
clock source is absent or is driven to DC levels below the minimum
specifications.
• Very low duty cycle distortion: <100ps (maximum)
• High speed propagation delay: <2.2ns (maximum)
• Up to 450MHz operation
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML or LVDS input interface
• Selectable differential inputs to sixteen LVDS outputs
• Power-down mode
• At power-up, FSEL should be LOW
• 2.5V VDD
• -40°C to 85°C ambient operating temperature
• Available in TQFP package
The IDT5T93GL161 outputs can be asynchronously
enabled/disabled. When disabled, the outputs will drive to the
value selected by the GL pin. Multiple power and grounds reduce
noise.
Applications
Pin Assignment
• Clock distribution
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
G1
GND
GND
48
47
46
G2
GND
GND
VDD
VDD
45
44
43
Q1
Q1
Q12
Q12
Q11
Q11
Q10
IDT5T93GL161
64-Lead TQFP E-Pad
10mm x 10mm x 1.0mm package body
Y package
Q2
Q2
Q3
42
41
40
Q3
Q4
Q4
10
11
12
Q10
Q9
39
38
37
Top View
Q9
V
DD
13
V
DD
36
35
34
A1 14
A1
GND 16
17 18 19 20 21
A2
A2
15
GND
33
23 24 25 26 27 28 29 30 31 32
22
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2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Block Diagram
GL
G1
Q1
Q1
OUTPUT
CONTROL
Q2
Q2
OUTPUT
CONTROL
Q3
Q3
OUTPUT
CONTROL
PD
Q4
Q4
OUTPUT
CONTROL
Q5
Q5
OUTPUT
CONTROL
A1
A1
1
0
Q6
Q6
OUTPUT
CONTROL
A2
A2
Q7
Q7
OUTPUT
CONTROL
SEL
Q8
Q8
OUTPUT
CONTROL
FSEL
G2
Q9
Q9
OUTPUT
CONTROL
Q10
Q10
OUTPUT
CONTROL
Q11
Q11
OUTPUT
CONTROL
Q12
Q12
OUTPUT
CONTROL
Q13
Q13
OUTPUT
CONTROL
Q14
Q14
OUTPUT
CONTROL
Q15
Q15
OUTPUT
CONTROL
Q16
Q16
OUTPUT
CONTROL
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Table 1. Pin Descriptions
Name
Type
Description
A[1:2]
Input
Input
Adjustable (1, 4) Clock input. A[1:2] is the "true" side of the differential clock input.
Complementary clock inputs. A[1:2] is the complementary side of A[1:2].
For LVTTL single-ended operation, A[1:2] should be set to the desired toggle
Adjustable (1, 4) voltage for A[1:2]:
A[1:2]
3.3V LVTTL VREF = 1650mV
2.5V LVTTL VREF = 1250mV
Gate control for differential outputs Q1 and Q1 through Q8 and Q8. When G1 is
G1
G2
GL
Input
Input
Input
LVTTL
LVTTL
LVTTL
LOW, the differential outputs are active. When G1 is HIGH, the differential
outputs are asynchronously driven to the level designated by GL(2)
.
Gate control for differential outputs Q9 and Q9 through Q16 and Q16. When G2
is LOW, the differential outputs are active. When G2 is HIGH, the differential
outputs are asynchronously driven to the level designated by GL(2)
.
Specifies output disable level. If HIGH, "true" outputs disable HIGH and
"complementary" outputs disable LOW. If LOW, "true" outputs disable LOW
and "complementary" outputs disable HIGH.
Q[1:16]
Q{1:16}
Output
Output
LVDS
LVDS
Clock outputs.
Complementary clock outputs.
Reference clock select. When LOW, selects A2 and A2.
When HIGH, selects A1 and A1.
SEL
PD
Input
Input
Input
LVTTL
LVTTL
LVTTL
Power-down control. Shuts off entire chip. If LOW, the device goes into LOW
power mode. Inputs and outputs are disabled. Both "true" and "complementary"
outputs will pull to VDD. Set HIGH for normal operation.(3)
At a rising edge, FSEL forces select to the input designated by SEL.
Set LOW for normal operation. At power-up, FSEL should be LOW.
FSEL
VDD
Power
Power
Power supply for the device core and inputs.
Ground.
GND
NOTES:
1.
Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2.
3.
4.
Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting PD.
The user must take precautions with any differential input interface standard being used in order to prevent instability when there is
no input signal.
Table 2. Pin Characteristics (TA = +25°C, F = 1.0MHz)
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
3
pF
NOTE: This parameter is measured at characterization but not tested.
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Function Tables
Table 3A. Gate Control Output Table
Control Outputs
Outputs
GL
0
G
0
1
0
1
Q[1:16]
Toggling
LOW
Q[1:16]
Toggling
HIGH
0
1
Toggling
HIGH
Toggling
LOW
1
Table 3B. Input Selection Table
Selection SEL pin
Inputs
A2/A2
A1/A1
0
1
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC
Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Item
Rating
Power Supply Voltage, VDD
Input Voltage, VI
-0.5V to +3.6V
-0.5V to +3.6V
Output Voltage, VO
Not to exceed 3.6V
-0.5 to VDD +0.5V
Storage Temperature, TSTG
Junction Temperature, TJ
-65°C to +150°C
150°C
Recommended Operating Range
Symbol
TA
Description
Minimum
Typical
+25
Maximum
+85
Units
°C
Ambient Operating Temperature
Internal Power Supply Voltage
-40
2.3
VDD
2.5
2.7
V
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics(1), TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical(2)
Maximum
Units
Quiescent VDD
Power Supply Current
VDD = Max.,
IDDQ
ITOT
IPD
350
mA
All Input Clocks = LOW(2); Outputs enabled
Total Power
VDD Supply Current
VDD = 2.7V;
FREFERENCE Clock = 450MHz
360
5
mA
mA
Total Power Down
Supply Current
PD = LOW
NOTE 1: These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.
NOTE 2: The true input is held LOW and the complementary input is held HIGH.
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Table 4B. LVTTL DC Characteristics(1), TA = -40°C to 85°C
Symbol Parameter
Test Conditions
VDD = 2.7V
Minimum
Typical(2)
Maximum
Units
µA
µA
V
IIH
Input High Current
5
5
IIL
Input Low Current
VDD = 2.7V
VIK
VIN
VIH
VIL
VTHI
Clamp Diode Voltage
DC Input Voltage
VDD = 2.3V, IIN = -18mA
-0.7
-1.2
3.6
-0.3
1.7
V
DC Input High Voltage
DC Input Low Voltage
DC Input Threshold Crossing Voltage
V
0.7
V
VDD/2
1.65
V
3.3V LVTTL
2.5V LVTTL
V
VREF
Single-Ended Reference Voltage (3)
1.25
V
NOTE 1: See Recommended Operating Range table.
NOTE 2: Typical values are at VDD = 2.5V, +25°C ambient.
NOTE 3: For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage.
Table 4C. Differential DC Characteristics(1), TA = -40°C to 85°C
Symbol
IIH
Parameter
Test Conditions
VDD = = 2.7V
Minimum
Typical(2)
Maximum
Units
µA
µA
V
Input High Current
5
5
IIL
Input Low Current
VDD = = 2.7V
VIK
Clamp Diode Voltage
DC Input Voltage
DC Differential Voltage(3)
VDD = 2.3V, IIN = -18mA
-0.7
-1.2
3.6
VIN
-0.3
0.1
V
VDIF
VCM
V
DC Common Mode Input Voltage
0.05
VDD
V
NOTE 1: See Recommended Operating Range table.
NOTE 2: VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and
VCP is the "complement" input level. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW
input. The AC differential voltage must be achieved to guarantee switching to a new state.
NOTE 3: VCM specifies the maximum allowable range of (VTR + VCP) /2.
NOTE 4: Typical values are at VDD = 2.5V, +25°C ambient.
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Table 4D. LVDS DC Characteristics(1), TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical(2)
Maximum
Units
Differential Output Voltage for the
True Binary State
VOT(+)
VOT(–)
∆VOT
VOS
247
454
mV
Differential Output Voltage for the
False Binary State
247
454
50
mV
mV
V
Change in VOT Between Complementary
Output States
Output Common Mode Voltage
(Offset Voltage)
1.125
1.2
1.375
50
Change in VOS Between Complementary
Output States
∆VOS
mV
IOS
Outputs Short Circuit Current
VOUT+ and VOUT– = 0V
VOUT+ = VOUT–
12
6
24
12
mA
mA
IOSD
Differential Outputs Short Circuit Current
NOTE 1: See Recommended Operating Range table.
NOTE 2: Typical values are at VDD = 2.5V, +25°C ambient.
AC Electrical Characteristics
Table 5A. HSTL Differential Input AC Characteristics, TA = -40°C to 85°C
Symbol Parameter
Value
Units
VDIF
VX
Input Signal Swing(1)
Differential Input Signal Crossing Point(2)
1
V
mV
%
750
DH
Duty Cycle
50
VTHI
tR / tF
Input Timing Measurement Reference Level(3)
Input Signal Edge Rate(4)
Crossing Point
2
V
V/ns
NOTE 1.The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)
environment. This device meets the VDIF (AC) specification under actual use conditions.
NOTE 2.A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)
environment. This device meets the VX specification under actual use conditions.
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
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2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Table 5B. eHSTL AC Differential Input Characteristics, TA = -40°C to 85°C
Symbol
VDIF
VX
Parameter
Input Signal Swing(1)
Differential Input Signal Crossing Point(2)
Value
Units
V
1
900
mV
%
DH
Duty Cycle
50
VTHI
tR / tF
Input Timing Measurement Reference Level(3)
Input Signal Edge Rate(4)
Crossing Point
2
V
V/ns
NOTE 1.The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)
environment. This device meets the VDIF (AC) specification under actual use conditions.
NOTE 2.A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)
environment. This device meets the VX specification under actual use conditions.
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
Table 5C. LVEPECL (2.5V) and LVPECL (3.3V) Differential Input AC Characteristics, TA = -40°C to 85°C
Symbol
Parameter
Input Signal Swing(1)
Maximum
Units
mV
mV
m
VDIF
732
LVEPECL
LVPECL
1082
VX
Differential Input Cross Point Voltage(2)
1880
DH
Duty Cycle
50
%
VTHI
tR / tF
Input Timing Measurement Reference Level(3)
Input Signal Edge Rate(4)
Crossing Point
2
V
V/ns
NOTE 1.The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment
(ATE) environment. This device meets the VDIF (AC) specification under actual use conditions.
NOTE 2.A 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point level is specified to allow consistent, repeatable results
in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions.
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
Table 5D. LVDS Differential Input AC Characteristics, TA = -40°C to 85°C
Symbol
VDIF
VX
Parameter
Input Signal Swing(1)
Differential Input Cross Point Voltage(2)
Maximum
Units
mV
V
400
1.2
DH
Duty Cycle
50
%
VTHI
tR / tF
Input Timing Measurement Reference Level(3)
Input Signal Edge Rate(4)
Crossing Point
2
V
V/ns
NOTE 1.The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment
(ATE) environment. This device meets the VDIF (AC) specification under actual use conditions.
NOTE 2.A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.
This device meets the VX specification under actual use conditions.
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
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2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Table 5E. AC Differential Input Characteristics(1), TA = -40°C to 85°C
Symbol
VDIF
VIX
Parameter
Minimum
0.1
Typical
Maximum
3.6
Units
AC Differential Voltage(2)
Differential Input Cross Point Voltage
Common Mode Input Voltage Range(3)
Input Voltage
V
V
V
V
0.05
VDD
VCM
VIN
0.05
VDD
-0.3
3.6
NOTE 1.The output will not change state until the inputs have crossed and the minimum differential voltage range defined by VDIF has
been met or exceeded.
NOTE 2.VDIF specifies the minimum input voltage (VTR – VCP) required for switching where VTR is the “true” input level and VCP is the
“complement” input level. The AC differential voltage must be achieved to guarantee switching to a new state.
NOTE 3.IVCM specified the maximum allowable range of (VTR + VCP) /2.
Table 5F. AC Characteristics(1,5), TA = -40°C to 85°C
Symbol
tsk(o)
tsk(p)
tsk(pp)
tpLH
Parameter
Test Conditions
Minimum
Typical
Maximum
75
Units
ps
Same Device Output Pin-to-Pin Skew (2)
Pulse Skew(3)
Part-to-Part Skew(4)
100
ps
300
ps
Propagation Delay, Low-to-High
Propagation Delay, High-to-Low
Frequency Range(6)
1.5
1.5
2.2
ns
A/A Crosspoint to Qn/Qn
Crosspoint
tpHL
2.2
ns
fo
450
MHz
Output Gate Enable Crossing
VTHI-to-Qn/Qn Crosspoint
tPGE
3.5
3.5
ns
ns
Output Gate Disable Crossing
VTHI-to-Qn/Qn Crosspoint Driven to
GL Designated Level
tPGD
tPWRDN
tPWRUP
PD Crossing VTHI-to-Qn = VDD, Qn = VDD
100
100
µS
µS
Output Gate Disable Crossing VTHI to
Qn/Qn Driven to GL Designated Level
NOTE 1. AC propagation measurements should not be taken within the first 100 cycles of startup.
NOTE 2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and
load conditions on any one device.
NOTE 3. Skew measured is the difference between propagation delay times tpHL and tpLH of any single differential output pair under
identical input and output interfaces, transitions and load conditions on any one device.
NOTE 4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two
devices, given identical transitions and load conditions at identical VDD levels and temperature.
NOTE 5. All parameters are tested with a 50% input duty cycle.
NOTE 6. Guaranteed by design but not production tested.
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2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Differential AC Timing Waveforms
Output Propagation and Skew Waveforms
1/fo
+ VDIF
VDIF = 0
- VDIF
A[1:2] - A[1:2]
tPHL
tPLH
+ VDIF
VDIF = 0
- VDIF
Qn - Qn
tSK(O)
tSK(O)
+ VDIF
VDIF = 0
- VDIF
Qm - Qm
NOTE 1: Pulse skew is calculated using the following expression:
tsk(p) = |tpHL – tpLH|
Note that the tpHL and tpLH shown above are not valid measurements for this calculation because they are not taken from the same pulse.
NOTE 2: AC propagation measurements should not be taken within the first 100 cycles of startup.
Differential Gate Disabled/Endable Showing Runt Pulse Generation
+ VDIF
V
DIF = 0
A
[1:2] - A[1:2]
- VDIF
V
V
V
IH
THI
IL
GL
t
PLH
V
V
V
IH
THI
IL
Gx
t
PGD
tPGE
+ VDIF
DIF = 0
V
- VDIF
Qn - Qn
NOTE 1: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user’s responsibility to time
the G signal to avoid this problem.
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2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Glitchless Output Operation with Switching Input Clock Selection
+ VDIF
VDIF = 0
- VDIF
A1 - A1
+ VDIF
VDIF = 0
- VDIF
A2 - A2
SEL
VIH
VTHI
VIL
+ VDIF
VDIF = 0
- VDIF
Qn - Qn
1. When SEL changes, the output clock goes LOW on the falling edge of the output clock up to three cycles later. The output then stays
LOW for up to three clock cycles of the new input clock. After this, the output starts with the rising edge of the new input clock.
2. AC propagation measurements should not be taken within the first 100 cycles of startup.
FSEL Operation for When Current Clock Dies
1. When the differential on the selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When
this happens, the SEL pin should be toggled and FSEL asserted in order to force selection of the new input clock. The output clock will
start up after a number of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that
the unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.
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2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
FSEL Operation for When Opposite Clock Dies
1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state.
When this happens, the FSEL pin should be asserted in order to force selection of the new input clock. The output clock will start up after
a number of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that
the unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.
Selection of Input While Protecting Against When Opposite Clock Dies
+VDIF
A1 - A1
A2 - A2
FSEL
SEL
VDIF=0
-VDIF
+VDIF
VDIF=0
-VDIF
VIH
VTHI
VIL
VIH
VTHI
VIL
+VDIF
VDIF=0
-VDIF
Qn - Qn
1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock.
2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart
with the input clock selected by the SEL pin.
3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output
will be driven LOW and will restart with the input clock selected by the SEL pin.
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
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2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Power Down Timing
+VDIF
VDIF=0
-VDIF
A1 - A1
+VDIF
VDIF=0
-VDIF
A2 - A2
VIH
VTHI
VIL
Gx
VIH
VTHI
VIL
PD
+VDIF
VDIF=0
-VDIF
Qn - Qn
NOTE 1: It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting PD.
NOTE 2: The Power Down Timing diagram assumes that GL is HIGH.
NOTE 3: It should be noted that during power-down mode, the outputs are both pulled to VDD. In the Power Down Timing diagram this is
shown when Qn/Qn goes to VDIF = 0.
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Test Circuits and Conditions
Test Circuit for Differential Input
~50
VIN
Transmission Line
VDD/2
A
A
D.U.T.
Pulse
Generator
~50
VIN
Transmission Line
-VDD/2
Scope
50
50
Table 6A. Differential Input Test Conditions
Symbol
VDD = 2.5V 0.2V
Unit
VTHI
Crossing of A and A
V
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Test Circuit for DC Outputs and Power Down Tests
VDD
A
A
Qn
Qn
Pulse
Generator
RL
RL
D.U.T.
VOS
VOD
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing
VDD/2
SCOPE
CL
Z = 50
A
A
Qn
Qn
Pulse
Generator
50
50
D.U.T.
Z = 50
CL
-VDD/2
Table 6B. Differential Input Test Conditions
Symbol
V
DD = 2.5V 0.2V
Unit
pF
pF
Ω
0(1)
8(1,2)
50
CL
RL
NOTE 1: Specifications only apply to “Normal Operations” test condition. The TIA/EIA specification load is for reference only.
NOTE 2: The scope inputs are assumed to have a 2pF load to ground. TIA/EIA – 644 specifies 5pF between the output pair.
With CL = 8pF, this gives the test circuit appropriate 5pF equivalent load.
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
15
IDT5T93GL161 REV. A SEPTEMBER 12, 2008
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Package Outline
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
16
IDT5T93GL161 REV. A SEPTEMBER 12, 2008
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Package Dimensions
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
17
IDT5T93GL161 REV. A SEPTEMBER 12, 2008
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Ordering Information
Table 7. Ordering Information
XX
X
XXXXX
IDT
Package Process
Device Type
I
-40 C to +85 C (Industrial)
Thin Quad Flat Pack
TQFP - Green
PF
PFG
2.5V LVDS 1:16 Glitchless Clock Buffer
Terabuffer II
5T93GL161
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
18
IDT5T93GL161 REV. A SEPTEMBER 12, 2008
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Revision History Sheet
Rev
Table
Page
Description of Change
Date
T3A
T3B
4
4
Added Gate Control Output Table.
Added Selection Table.
A
16
17
Added Package Outline.
9/12/08
Added Package Dimensions.
Updated datasheet format.
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Contact Information:
www.IDT.com
Corporate Headquarters
Sales
Technical Support
Integrated Device Technology, Inc.
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
+480-763-2056
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
www.IDT.com/go/contactIDT
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
www.IDT.com
Printed in USA
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