IDT5V2528PGGI8 [IDT]
PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO28, TSSOP-28;
| 型号： | IDT5V2528PGGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO28, TSSOP-28 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：58K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5V / 3.3V PHASE-LOCK
LOOP CLOCK DRIVER
ZERO DELAY BUFFER
IDT5V2528/A
The IDT5V2528 inputs, PLL core, Y0, Y1, andFBOUT buffers operate from
the 3.3V VDD and AVDD power supply pins.
FEATURES:
• Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ
• 1:10 fanout
One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of
the ten outputs, up to seven may be configured for 2.5V or 3.3V LVTTL
outputs. The number of 2.5V outputs is controlled by 3-level input signals
G_CtrlandT_Ctrl, andbyconnectingtheappropriateVDDQ pinsto2.5Vor
3.3V. The 3-level input signals may be hard-wired to high-mid-low levels.
Outputsignaldutycyclesareadjustedto50percent,independentoftheduty
cycleatCLK. TheoutputscanbeenabledordisabledviatheG_Ctrl input.
When the G_Ctrl input is mid or high, the outputs switch in phase and
frequencywithCLK;whentheG_Ctrlislow, alloutputs(exceptFBOUT)are
disabledtothelogic-lowstate.
UnlikemanyproductscontainingPLLs,theIDT5V2528doesnotrequire
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the IDT5V2528 requires a
stabilization time to achieve phase lock of the feedback signal to the
referencesignal.Thisstabilizationtimeisrequired,followingpowerupand
• 3-level inputs for output control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
• No external RC network required for PLL loop stability
• Configurable 2.5V or 3.3V LVTTL outputs
• tPD Phase Error at 100MHz to 166MHz: ±150ps
• Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps
• Spread spectrum compatible
• Operating Frequency:
−
Std: 25MHz to 140MHz
A: 25MHz to 167MHz
−
• Available in TSSOP package
DESCRIPTION:
TheIDT5V2528isahighperformance, low-skew, low-jitter, phase-lock application of a fixed-frequency, fixed-phase signal at CLK, as well as
loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency following any changes to the PLL reference or feedback signals. The PLL
and phase, the feedback (FBOUT) output to the clock (CLK) input signal. can be bypassed for test purposes by strapping AVDD to ground.
FUNCTIONALBLOCKDIAGRAM
28
G_Ctrl
3
1
T_Ctrl
TY0, VDDQ pin 4
TY1, VDDQ pin 25
26
24
TY2, VDDQ pin 25
TY3, VDDQ pin 15
TY4, VDDQ pin 15
MODE
SELECT
17
16
13
TY5, VDDQ pin 11
TY6, VDDQ pin 11
12
10
6
7
TY7, VDDQ pin 11
Y0, VDD pin 21
CLK
PLL
20
19
FBIN
AVDD
Y1, VDD pin 21
5
22
FBOUT, VDD pin 21
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JUNE 2003
1
c
2002 Integrated Device Technology, Inc.
DSC 5971/11
IDT5V2528/A
2.5/3.3VPHASE-LOCKLOOPCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
Rating
Max.
–0.5to+4.6
–0.5to+5.5
–0.5to
Unit
V
VDD, VDDQ, AVDD
SupplyVoltageRange
InputVoltageRange
T_Ctrl
GND
1
28
27
26
25
24
23
22
21
20
19
18
G_Ctrl
GND
TY1
(2)
VI
V
2
(2)
VO
VoltageRangeappliedtoany
V
3
output in the HIGH or LOW state VDD+0.5
TY0
IIK (VI < 0)
InputClampCurrent
OutputClampCurrent
–50
mA
mA
VDDQ
4
VDDQ
TY2
IOK
±50
AVDD
CLK
5
(VO < 0 or VO > VDD)
6
GND
FBOUT
VDD
IO
ContinuousOutputCurrent
±50
mA
FBIN
AGND
GND
TY7
7
(VO = 0 to VDD)
VDD or GND
TSTG
8
ContinuousCurrent
±200
–65to+150
+150
mA
°C
°C
9
Y0
StorageTemperatureRange
JunctionTemperature
10
11
Y1
TJ
NOTES:
VDDQ
GND
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TY6
TY5
12
13
17
16
TY3
TY4
GND
14
15
VDDQ
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
TSSOP
TOP VIEW
of 150°C and a board trace length of 750 mils.
CAPACITANCE(1)
Symbol
Description
Input Capacitance
VI = VDD or GND
Min
Typ.
Max. Unit
CIN
—
5
—
pF
pF
pF
CO
CL
Output Capacitance
VI = VDD or GND
—
6
—
Load Capacitance 2.5V outputs
3.3V outputs
—
—
20
30
—
—
NOTE:
1. Unused inputs must be held HIGH or LOW to prevent them from floating.
RECOMMENDEDOPERATINGRANGE
Symbol
Description
Min.
Typ.
Max.
Unit
V
(1)
VDD, AVDD
Power Supply Voltage
Power Supply Voltage
3
3.3
3.6
(1)
VDDQ
2.5VOutputs
3.3VOutputs
2.3
3
2.5
3.3
2.7
3.6
V
TA
AmbientOperatingTemperature
–40
+25
+85
°C
NOTE:
1. All power supplies should operate in tandem. If VDD or VDDQ is at a maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
2
IDT5V2528/A
2.5/3.3VPHASE-LOCKLOOPCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
PINDESCRIPTION
Terminal
Name
CLK(1)
FBIN
No.
6
Type
Description
Clockinput
I
7
I
Feedbackinput
G_Ctrl(2)
28
3-level
3-levelinputfor2.5V/3.3VOutputSelect/Outputbankenable. When G_CtrlisLOW,alloutputsexceptFBOUTaredisabled
to a logic-LOW state. When G_Ctrl is MID or HIGH, all outputs are enabled and switch at the same frequency as CLK (see
OUTPUT SELECTION table).
T_Ctrl(2)
FBOUT
TY(7:0)
1
3-level
3-level input for 2.5V / 3.3V Output Select (see OUTPUT SELECTION table)
Feedbackoutput
22
3, 10, 12, 13,
16, 17, 24, 26
19,20
O
O
2.5Vor3.3VClockoutputs. 1,2,3,5,or7oftheseoutputsmaybeselectedas2.5Voutputs(seeOUTPUTSELECTIONtable).
Y(1:0)
O
3.3V Clock Outputs
(3)
AVDD
5
Power
Ground
Power
Power
Ground
3.3V Analog power supply. AVDD provides the power reference for the analog circuitry.
AGND
VDD
8
Analogground. AGNDprovidesthegroundreferencefortheanalogcircuitry.
21
3.3V Power supply
VDDQ
GND
4, 11, 15, 25
2, 9, 14, 18
23,27
2.5V or 3.3V Power supply for TY outputs
Ground
NOTES:
1. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time of 1ms
is required for the PLL to phase lock the feedback signal to the reference signal.
2. 3-level inputs will float to MID logic level if left unconnected.
3. AVDD can be used to bypass the PLL for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the outputs.
(1)
STATIC FUNCTION TABLE (AVDD = 0V)
OUTPUTSELECTION
Inputs
T_Ctrl
X
Outputs
VDDQ
Configuration
Pin 4 (2.5V)
Pins 11, 15, 25 (3.3V)
Pin 25 (2.5V)
Pins 4, 11, 15 (3.3V)
Pins 4, 25 (2.5V)
Pins 11, 15 (3.3V)
Pins 4, 15, 25 (2.5V)
Pin 11 (3.3V)
Pins 11, 15, 25 (2.5V)
Pin 4 (3.3V)
Pins 4, 11, 15, 25 (3.3V)
G_Ctrl
CLK
TY(7:0)
Y(1:0)
FBOUT
G_Ctrl
T_Ctrl
TY(7:0)
L
L
L
H
H
L
L
H
L
L
H
L
M
L
TY0(2.5V)
X
H
H
TY1 - TY7 (3.3V)
TY1,TY2(2.5V)
TY0, TY3 - TY7 (3.3V)
TY0 - TY2 (2.5V)
TY3 - TY7 (3.3V)
TY0 - TY4 (2.5V)
TY5 - TY7 (3.3V)
TY1 - TY7 (2.5V)
TY0 (3.3V)
see
M
M
H
H
H
M
H
L
OUTPUT SELECTION
table
L
L
L
L
running
running
running
running
NOTE:
1. AVDD should be powered up along with VDD, before setting AVDD to ground, to put the
control pins in a valid state.
M
H
TYo - TY7 (3.3V)
DYNAMIC FUNCTION TABLE (AVDD = 3.3V)
Inputs
T_Ctrl
X
Outputs
Y(1:0)
G_Ctrl
L
L
CLK
L
H
TY(7:0)
L
L
FBOUT
L
L
L
L
H
L
X
see OUTPUT
L
L
SELECTION table
H
H
H
H
3
IDT5V2528/A
2.5/3.3VPHASE-LOCKLOOPCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
Symbol
VIK
Parameter
Test Conditions
Min.
Typ.(1)
Max
Unit
V
InputClampVoltage
Input HIGH Level
II = -18mA
- 1.2
VIH
CLK, FBIN
2
V
VIL
InputLOWLevel
CLK, FBIN
0.8
V
VIHH
VIMM
VILL
VOH
Input HIGH Voltage Level(2)
Input MID Voltage Level(2)
InputLOWVoltageLevel(2)
Output HIGH Voltage Level
(3.3VOutputs)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
IOH = -100µA
IOH = -12mA
IOH = -100µA
IOH = -12mA
IOL = 100µA
IOL = 12mA
VDD - 0.6
V
VDD/2 - 0.3
VDD/2 + 0.3
0.6
V
V
VDD - 0.2
2.4
V
VOH
VOL
VOL
I3
Output HIGH Voltage Level
(2.5VOutputs)
VDD - 0.1
2
V
V
OutputLOWVoltageLevel
(3.3VOutputs)
0.2
0.4
OutputLOWVoltageLevel
(2.5VOutputs)
IOL = 100µA
IOL = 12mA
0.1
V
0.4
3-LevelInputDCCurrent
(G_Ctrl,T_Ctrl)
VIN = VDD
HIGH Level
MID Level
LOW Level
+200
+50
VIN = VDD/2
–50
µA
µA
VIN = GND
–200
II
InputCurrent
VI = VDD or GND
±5
NOTES:
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
2. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias floating inputs to VDD/2. If these inputs are switched, the function and timing of
the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
POWERSUPPLYCHARACTERISTICS
Symbol
IDDPD
IDDA
Parameter
Test Conditions
Typ.(1)
8
Max
40
Unit
µA
mA
Power Down Supply Current
AVDD Supply Current
VDD = 3.6, VDDQ = 2.7V / 3.3V, AVDD = 0V
VDD = AVDD = 3.6V, VDDQ = 2.7V / 3.3V, CLK = 0 or VDD
3.5
10
IDD
Dynamic Power Supply Current VDD = AVDD = 3.6V, VDDQ = 2.7V / 3.3V, CL = 0pF
500
15
—
µA/MHz
VDD = AVDD = VDDQ = 3.6V
—
IDDD
Dynamic Power Supply
CurrentperOutput
CL = 30pF, CLK = 100MHz
mA
VDD = AVDD = 3.6V, VDDQ = 2.7V
CL = 20pF, CLK = 100MHz
12
—
NOTE:
1. For nominal voltage and temperature.
4
IDT5V2528/A
2.5/3.3VPHASE-LOCKLOOPCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
INPUTTIMINGREQUIREMENTSOVEROPERATINGRANGE
5V2528
5V2528A
Min
25
Max
140
60%
1
Min
25
Max
167
60%
1
Units
fCLOCK
tLOCK
Clockfrequency
MHz
Input clock duty cycle
Stabilizationtime(1)
40%
40%
ms
NOTE:
1.Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference
signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are
not applicable.
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE-5V2528(1)
Symbol
Parameter(2)
Phase Error from Rising Edge CLK to Rising Edge FBIN (100MHz-133MHz)
Phase Error minus Jitter from Rising Edge CLK to Rising Edge FBIN (133MHz)
OutputSkewbetween3.3VOutputs
Min.
–150
–50
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
Max.
150
50
Unit
ps
ps
ps
ps
ps
ps
%
tPHASEerror
tPHASE error-jitter(3)
(4)
tSK1(0)
150
150
200
75
(4)
tSK2(0)
OutputSkewbetween2.5VOutputs
—
(4,5)
tSK3(0)
Output Skew between 2.5V and 3.3V Outputs
Cycle-to-CycleOutputJitter(Peak-to-Peak)at133MHz
Duty Cycle
—
tJ
–75
45
55
tR
tF
tR
tF
Output Rise Time for 3.3V Outputs (20% to 80%)
Output Fall Time for 3.3V Outputs (20% to 80%)
Output Rise Time for 2.5V Outputs (20% to 80%)
Output Fall Time for 2.5V Outputs (20% to 80%)
0.8
2.1
2.1
1.5
1.5
ns
ns
ns
ns
0.8
0.5
0.5
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE-5V2528A(1)
Symbol
Parameter(2)
Phase Error from Rising Edge CLK to Rising Edge FBIN (100MHz-166MHz)
Phase Error minus Jitter from Rising Edge CLK to Rising Edge FBIN (166MHz)
OutputSkewbetween3.3VOutputs
Min.
–150
–50
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
Max.
150
50
Unit
ps
tPHASEerror
tPHASE error-jitter(3)
ps
(4)
tSK1(0)
150
150
200
250
75
ps
(4)
tSK2(0)
OutputSkewbetween2.5VOutputs
—
ps
(4,5)
tSK3(0)
Output Skew between 2.5V and 3.3V Outputs 25MHz to 133MHz
133MHz to 166MHz
—
ps
—
tJ
Cycle-to-CycleOutputJitter(Peak-to-Peak)at166MHz
Duty Cycle
–75
45
ps
%
55
tR
tF
tR
tF
Output Rise Time for 3.3V Outputs (20% to 80%)
Output Fall Time for 3.3V Outputs (20% to 80%)
Output Rise Time for 2.5V Outputs (20% to 80%)
Output Fall Time for 2.5V Outputs (20% to 80%)
0.8
2.1
2.1
1.5
1.5
ns
ns
ns
ns
0.8
0.5
0.5
NOTES:
1. All parameters are measured with the following load conditions: 30pF || 500Ω for 3.3V outputs and 20pF || 500Ω for 2.5V outputs.
2. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
3. Phase error does not include jitter.
4. All skew parameters are only valid for equal loading of all outputs.
5. Measured for VDDQ = 2.3V and 3V, 2.5V and 3.3V, or 2.7V and 3.6V.
5
IDT5V2528/A
2.5/3.3VPHASE-LOCKLOOPCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITANDVOLTAGEWAVEFORMS
From Output
Under Test
From Output
Under Test
500Ω
500Ω
CL=30pF(2)
CL=20pF(2)
Test Circuit for 3.3V Outputs
Test Circuit for 2.5V Outputs
VDD/2
CLK
VDD/2
tPHASE ERROR
FBIN
Y, TY
CL
CLK
80%
20%
FBOUT
or
Any Y, TY (3.3V)
VDDQ/2
tR
tF
IDT5V2528/A
500Ω
on each Y,
TY output
(2)
VDDQ/2
VDDQ/2
tSK1(o)
FBOUT
Any Y, TY (3.3V)
FBIN
(4)
CF
tSK3(o)
500Ω
PCBTRACE
80%
20%
VDDQ/2
Any TY (2.5V)
Any TY (2.5V)
tR
tF
VDDQ/2
VDDQ/2
tSK2(o)
PHASE ERROR AND SKEW CALCULATIONS(3,4)
NOTES:
1. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz ZO = 50Ω, tR ≤ 1.2 ns, tF ≤ 1.2 ns.
2. CL includes probe and jig capacitance.
3. The outputs are measured one at a time with one transition per measurement.
4. Phase error measurements require equal loading at outputs Y, TY, and FBOUT. CF = CL – CFBIN – CPCBtrace; CFBIN ≅ 5pF.
6
IDT5V2528/A
2.5/3.3VPHASE-LOCKLOOPCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT XXXXX
Device Type Package
XX
X
Process
I
-40°C to +85°C (Industrial)
PG
PGG
Thin Shrink Small Outline Package
TSSOP - Green
5V2528
2.5V / 3.3V Phase-Lock Loop Clock Driver
5V2528A
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
logichelp@idt.com
(408) 654-6459
www.idt.com
7
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