IDT5V9955BFI [IDT]
PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PBGA96, FBGA-52;
| 型号： | IDT5V9955BFI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PBGA96, FBGA-52 |
| 文件： | 总11页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V PROGRAMMABLE
SKEW DUAL PLL CLOCK
DRIVER TURBOCLOCK™ W
IDT5V9955
FEATURES:
DESCRIPTION
• Ref input is 5V tolerant
The IDT5V9955is a highfanout3.3VPLLbasedclockdriverintended
forhighperformancecomputinganddata-communicationsapplications.A
keyfeatureoftheprogrammableskewistheabilityofoutputstoleadorlag
the REF input signal. The IDT5V9955 has sixteen programmable skew
outputs in eight banks of 2. The two separate PLLs allow the user to
independentlycontrolAandBbanks.Skewis controlledby3-levelinput
signals that may be hard-wired to appropriate HIGH-MID-LOW levels.
The feedbackinputallows divide-by-functionalityfrom1to12through
the use of the xDS[1:0] inputs. This provides the user with frequency
multiplicationfrom1to12withoutusingdividedoutputs forfeedback.
WhenthexsOEpinis heldlow,allthexbankoutputs aresynchronously
enabled.However,ifxsOEis heldhigh,allthexbankoutputs exceptx2Q0
and x2Q1 are synchronously disabled. The xLOCK is high when the
xbank PLL has achieved phase lock.
• 8 pairs of programmable skew outputs
• Two separate A and B banks for individual control
• Low skew: 185ps same pair, 250ps same bank, 350ps both
banks
• Selectable positive or negative edge synchronization on each
bank: excellent for DSP applications
• Synchronous output enable on each bank
• Input frequency: 2MHz to 200MHz
• Output frequency: 6MHz to 200MHz
• 3-level inputs for skew and PLL range control
• 3-level inputs for feedback divide selection multiply / divide
ratios of (1-6, 8, 10, 12) / (2, 4)
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter: <100ps cycle-to-cycle
• Power-down mode on each bank
• Lock indicator on each bank
Furthermore, whenxPEis heldhigh, allthe outputs are synchronized
withthepositiveedgeoftheREFclockinput.WhenxPEis heldlow,allthe
xbank outputs are synchronized with the negative edge of REF. The
IDT5V9955has LVTTLoutputs with12mAbalanceddrive outputs.
• Available in BGA package
FUNCTIONALBLOCKDIAGRAM
BLOCK
BPE
BFS
ALOCK
APE
AFS
TEST
REF
BPD
APD
BsOE
AsOE
3
3
3
3
PLL
PLL
/ N
/ N
BFB
AFB
3
3
3
3
BDS1:0
ADS1:0
A1F1:0
B1Q0
B1Q1
3
3
A1Q0
A1Q1
3
3
Skew
Skew
Select
B1F1:0
B2F1:0
B3F1:0
B4F1:0
Select
3
3
B2Q0
B2Q1
A2Q0
A2Q1
3
3
Skew
Select
Skew
Select
A2F1:0
A3F1:0
A4F1:0
3
3
3
3
B3Q0
B3Q1
A3Q0
A3Q1
Skew
Select
Skew
Select
3
3
B4Q0
B4Q1
A4Q0
A4Q1
3
3
Skew
Select
Skew
Select
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
NOVEMBER 2004
1
c
2004 Integrated Device Technology, Inc.
DSC 5974/11
IDT5V9955
3.3VPROGRAMMABLESKEWDUALPLLCLOCKDRIVERTURBOCLOCKW
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
6
A3Q1
A4Q0
A4Q1
APE
APD
A4F1
A3F1
AFS
B2F1
B1F1
BDS1
BLOCK
BVDDQ
B1Q0
B1Q1
B2Q0
B2Q1
BFB
5
4
A3Q0
AGND
AFB
AGND AGND
AGND AGND
AGND AGND
AGND AGND
AGND
AVDDQ
AVDDQ
AVDDQ
ASOE
AVDDQ
AVDDQ
ADS0
A4F0
AVDDQ
AVDDQ
A1F0
A3F0
AVDD
AVDDQ
REF
BGND
TEST
BVDDQ
BVDD
B2F0
B1F0
BDS0
BVDDQ BGND BGND
BVDDQ
BVDDQ
BVDDQ
BVDDQ
BGND BGND
AVDDQ
3
2
BVDDQ
B3F0
BVDDQ
B4F0
BVDDQ
BSOE
BVDDQ BGND BGND BGND
AVDDQ
A2F0
A2Q1
AGND
BGND BGND BGND
B3Q0
1
A2Q0
A
A1Q1
B
A1Q0
C
AVDDQ
D
ALOCK
ADS1
F
A1F1
G
A2F1
H
BFS
J
B3F1
K
B4F1
L
BPD
M
BPE
N
B4Q1
P
B4Q0
R
B3Q1
T
E
FPBGA
TOP VIEW
96 BALL FPBGA PACKAGE ATTRIBUTES
1.5mm Max.
1.4mm Nom.
1.3mm Min.
0.8mm
6
5
4
TOP VIEW
3
2
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
K
K
L
L
M
M
N
N
P
P
R
T
T
J
R
1
2
3
4
5
6
5.5mm
13.5mm
2
IDT5V9955
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWDUALPLLCLOCKDRIVERTURBOCLOCKW
ABSOLUTEMAXIMUMRATINGS(1)
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Symbol
Description
Max
–0.5 to +4.6
–0.5 to VDD+0.5
–0.5 to +5.5
1.1
Unit
V
Parameter Description
InputCapacitance
Typ. Max.
Unit
VDDQ, VDD Supply Voltage to Ground
CIN
REF
8
5
10
7
pF
VI
DC Input Voltage
REF Input Voltage
Maximum Power
Dissipation
V
Others
V
NOTE:
1. Capacitance applies to all inputs except TEST, xFS, xnF[1:0], and xDS[1:0].
TA = 85°C
TA = 55°C
W
1.9
TSTG
Storage Temperature Range
–65 to +150
° C
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
PINDESCRIPTION
Pin Name
REF
Type
IN
Description
ReferenceClockInput
xFB
IN
IndividualFeedbackInputs forAandBbanks
TEST(1)
IN
WhenMIDorHIGH,disables PLLforAandBbanks (exceptforconditions ofNote1). REFgoes toalloutputs. SkewSelections (See
ControlSummaryTable)remainineffect. SetLOWfornormaloperation.
xsOE(1)
IN
IndividualSynchronous OutputEnableforAandBbanks. WhenHIGH,itstops clockoutputs (exceptx2Q0 andx2Q1)inaLOWstate
(for xPE = H) - x2Q0 and x2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE
is HIGH, the nF[1:0] pins act as output disable controls for individual banks when xnF[1:0] = LL. Set xsOE LOW for normal operation
(hasinternalpull-down).
xPE
IN
IndividualSelectablepositiveornegativeedgecontrolforAandBbanks. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/
positiveedgeofthereferenceclock(hasinternalpull-up).
xnF[1:0]
xFS
IN
IN
3-levelinputsforselecting1of9skewtapsorfrequencyfunctions
Selectsappropriateoscillatorcircuitbasedonanticipatedfrequencyrange. (SeeProgrammableSkewRange.) IndividualcontrolonA
and B banks.
xnQ[1:0]
xDS[1:0]
xPD
OUT
IN
Eightbanksoftwooutputswithprogrammableskew
3-levelinputsforfeedbackdividerselectionforAandBbanks
IN
Power down control. Shuts off either A or B bank of the chip when LOW (has internal pull-up).
xLOCK
OUT
PLL lock indication signal for A and B banks. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be
synchronizedtotheinputs. (FormoreinformationonapplicationspecificuseoftheLOCKpin,pleaseseeAN237.)
VDDQ
VDD
PWR
PWR
PWR
Powersupplyforoutputbuffers
Powersupplyforphaselockedloop,lockoutput,andotherinternalcircuitry
Ground
GND
NOTE:
1. When TEST = MID and xsOE = HIGH, PLL remains active with xnF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain
in effect unless xnF[1:0] = LL.
3
IDT5V9955
3.3VPROGRAMMABLESKEWDUALPLLCLOCKDRIVERTURBOCLOCKW
INDUSTRIALTEMPERATURERANGE
PROGRAMMABLESKEW
Output skew with respect to the REF input is adjustable to compensate order to minimize the number of control pins, 3-level inputs (HIGH-MID-
for PCB trace delays, backplane propagation delays or to accommodate LOW) are used, they are intended for but not restricted to hard-wiring.
requirements for special timing relationships between clocked compo- Undriven 3-level inputs default to the MID level. Where programmable
nents. Skew is selectable as a multiple of a time unit (tU) which ranges skew is not a requirement, the control pins can be left open for the zero
from 625ps to 1.3ns (see Programmable Skew Range and Resolution skew default setting. The Control Summary Table shows how to select
Table). There are nine skew configurations available for each output specific skew taps by using the xnF1:0 control pins.
pair. These configurations are chosen by the xnF1:0 control pins. In
EXTERNALFEEDBACK
By providing two separate external feedbacks, the IDT5V9955 gives
An internal loop filter moderates the response of the VCO to the
users flexibility with regard to skew adjustment. The xFB signal is com- phase detector. The loop filter transfer function has been chosen to
pared with the input REF signal at the phase detector in order to drive provide minimal jitter (or frequency variation) while still providing accu-
the VCO. Phase differences cause the VCO of the PLL to adjust up- rate responses to input frequency changes.
wards or downwards accordingly.
PROGRAMMABLESKEWRANGEANDRESOLUTIONTABLE
xFS = LOW
1/(32 x FNOM)
24 to 50MHz
xFS = MID
1/(16 x FNOM)
48 to 100MHz
xFS = HIGH
1/(8 x FNOM)
96 to 200MHz
Comments
TimingUnitCalculation(tU)
VCOFrequencyRange(FNOM)(1,2)
SkewAdjustmentRange(3)
MaxAdjustment:
±7.8125ns
±67.5°
±18.75%
tU =1.25ns
tU =0.833ns
tU =0.625ns
—
±7.8125ns
±135°
±7.8125ns
±270°
ns
PhaseDegrees
% of Cycle Time
±37.5%
—
±75%
—
Example 1, FNOM = 25MHz
Example 2, FNOM = 37.5MHz
Example 3, FNOM = 50MHz
Example 4, FNOM = 75MHz
Example 5, FNOM = 100MHz
Example 6, FNOM = 150MHz
Example 7, FNOM = 200MHz
—
—
tU =1.25ns
tU =0.833ns
tU =0.625ns
—
—
—
—
tU =1.25ns
tU =0.833ns
tU =0.625ns
—
—
—
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
2. The level to be set on xFS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at x1Q1:0, x2Q1:0, and
the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and xFB inputs will be FNOM when the output connected to xFB is
undivided and xDS[1:0] = MM. The frequency of the REF and xFB inputs will be FNOM /2 or FNOM /4 when the part is configured for frequency multiplication by using a divided
output as the xFB input and setting xDS[1:0] = MM. Using the xDS[1:0] inputs allows a different method for frequency multiplication (see Divide Selection Table).
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed xQ output is used for feedback, then adjustment range will be greater. For example
if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.
4
IDT5V9955
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWDUALPLLCLOCKDRIVERTURBOCLOCKW
DIVIDESELECTIONTABLE
xDS[1:0]
LL
xFB Divide-by-n
Permitted Output Divide-by-n connected to xFB(1)
2
3
1 or 2
1
LM
LH
4
1, 2, or 4
1 or 2
1, 2, or 4
1 or 2
1 or 2
1
ML
5
MM
MH
HL
1
6
8
HM
HH
10
12
1
NOTE:
1. Permissible output division ratios connected to xFB. The frequency of the REF input will be FNOM/N when the part is configured for frequency multiplication by using an undivided
output for xFB and setting xDS[1:0] to N (N = 1-6, 8, 10, 12).
CONTROLSUMMARYTABLEFORFEEDBACKSIGNALS
nF1:0
LL(1)
LM
Skew (Pair #1, #2)
Skew (Pair #3)
Divide by 2
–6tU
Skew (Pair #4)
Divide by 2
–6tU
–4tU
–3tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
–2tU
MM
MH
HL
ZeroSkew
1tU
ZeroSkew
2tU
ZeroSkew
2tU
2tU
4tU
4tU
HM
HH
3tU
6tU
6tU
Inverted(2)
4tU
Divide by 4
NOTES:
1. LL disables outputs if TEST = MID and xsOE = HIGH.
2. When pair #4 is set to HH (inverted), xsOE disables pair #4 HIGH when xPE = HIGH, xsOE disables pair #4 LOW when xPE = LOW.
RECOMMENDEDOPERATINGRANGE
Symbol
VDD/VDDQ
TA
Description
Min.
3
Typ.
3.3
Max.
Unit
V
Power Supply Voltage
AmbientOperatingTemperature
3.6
-40
+25
+85
° C
5
IDT5V9955
3.3VPROGRAMMABLESKEWDUALPLLCLOCKDRIVERTURBOCLOCKW
INDUSTRIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Conditions(1)
Guaranteed Logic HIGH (REF, xFB Inputs Only)
Guaranteed Logic LOW (REF, xFB Inputs Only)
3-Level Inputs Only
Min.
Max.
—
Unit
V
VIH
Input HIGH Voltage
2
VIL
InputLOWVoltage
—
0.8
V
VIHH
VIMM
VILL
IIN
Input HIGH Voltage(2)
InputMIDVoltage(2)
InputLOWVoltage(2)
InputLeakageCurrent
(REF, xFB Inputs Only)
VDD−0.6
VDD/2−0.3
—
—
V
3-Level Inputs Only
VDD/2+0.3
0.6
V
3-Level Inputs Only
V
VIN = VDD or GND
−5
+5
µA
VDD = Max.
VIN = VDD
HIGH Level
MID Level
LOW Level
—
−100
−400
−25
—
+400
+100
—
I3
3-LevelInputDCCurrent
VIN = VDD/2
µ A
(TEST, xFS, xnF[1:0], xDS[1:0])
Input Pull-Up Current (xPE, xPD)
Input Pull-Down Current (xsOE)
OutputHIGHVoltage
VIN = GND
IPU
IPD
VDD = Max., VIN = GND
VDD = Max., VIN = VDD
—
µ A
µ A
V
+100
—
VOH
VDD = Min., IOH = −2mA (xLOCK Output)
VDDQ = Min., IOH = −12mA (xnQ[1:0] Outputs)
VDD = Min., IOL = 2mA (xLOCK Output)
VDDQ = Min., IOL = 12mA (xnQ[1:0] Outputs)
2.4
2.4
—
VOL
OutputLOWVoltage
—
0.4
V
—
0.4
NOTES:
1. All conditions apply to A and B banks.
2. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and timing
of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Typ.(2)
Max.
Unit
IDDQ
QuiescentPowerSupplyCurrent
VDD = Max., TEST = MID, REF = LOW,
xPE = LOW, xsOE = LOW, xPD = HIGH
xFS = MID, All outputs unloaded
40
60
mA
IDDPD
ΔIDD
IDDD
Power Down Current
VDD = Max., PD = LOW, xsOE = LOW
xPE = HIGH, TEST = HIGH, xFS = HIGH
xnF[1:0] = HH, xDS[1:0] = HH
—
1
50
60
μA
μA
Power Supply Current per Input HIGH
(REF and xFB inputs only)
VIN = 3V, VDD = Max., xPD = LOW, TEST = HIGH
xFS = L
190
150
130
112
160
250
290
230
200
—
Dynamic Power Supply Current per Output
TotalPowerSupplyCurrent
xFS = M
μA/MHz
mA
xFS = H
xFS = L, FVCO = 50MHz, CL = 0pF
xFS = M, FVCO = 100MHz, CL = 0pF
xFS = H, FVCO = 200MHz, CL = 0pF
ITOT
—
—
NOTES:
1. Measurements are for divide-by-1 outputs, xnF[1:0] = MM, and xDS[1:0] = MM. All conditions apply to A and B banks.
2. For nominal voltage and temperature.
6
IDT5V9955
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWDUALPLLCLOCKDRIVERTURBOCLOCKW
INPUTTIMINGREQUIREMENTS
Symbol
tR,tF
tPWC
Description(1)
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
Min.
—
2
Max.
10
Unit
ns/V
ns
—
DH
10
2
90
%
xFS = LOW
xFS = MID
xFS = HIGH
50
FREF
Referenceclockinputfrequency
4
100
200
MHz
8
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
7
IDT5V9955
3.3VPROGRAMMABLESKEWDUALPLLCLOCKDRIVERTURBOCLOCKW
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
Symbol
FNOM
tRPWH
tRPWL
tU
Parameter
Min.
Typ.
Max.
Unit
VCO Frequency Range
SeeProgrammableSkewRangeandResolutionTable
(1)
REF Pulse Width HIGH
2
2
—
—
—
ns
ns
(1)
REF Pulse Width LOW
—
ProgrammableSkewTimeUnit
SeeControlSummaryTable
tSKEWPR
tSKEWB
tSKEW0
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tDEV
Zero Output Matched-Pair Skew (xnQ0, xnQ1)(2,3)
—
—
50
0.1
0.1
0.1
0.2
0.15
0.3
—
—
—
—
—
—
0
185
0.35
0.25
0.25
0.5
0.5
0.9
0.75
0.25
0.25
0.5
0.7
1
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
(4)
Bank Skew
(5)
Zero Output Skew (All Outputs from the same A or B bank)
—
(6)
OutputSkew(Rise-Rise, Fall-Fall, Same Class Outputs)
—
(6)
OutputSkew(Rise-Fall,Nominal-Inverted,Divided-Divided)
—
(6)
OutputSkew(Rise-Rise,Fall-Fall,DifferentClassOutputs)
—
(2)
OutputSkew(Rise-Fall,Nominal-Divided,Divided-Inverted)
—
(2,7)
Device-to-Device Skew
—
(8)
t(φ)1-3
Static Phase Offset (xFS = L, M, H) (FB Divide-by-n = 1, 2, 3)
−0.25
−0.25
−0.5
−0.7
−1
−1
—
(8)
t(φ)H
Static Phase Offset (xFS = H)
(8)
t(φ)M
Static Phase Offset (xFS = M)
(8)
t(φ)L1-6
t(φ)L8-12
tODCV
tPWH
Static Phase Offset (xFS = L) (xFB Divide-by-n = 1, 2, 3, 4, 5, 6)
(8)
Static Phase Offset (xFS = L) (xFB Divide-by-n = 8, 10, 12)
Output Duty Cycle Variation from 50%
1
(9)
Output HIGH Time Deviation from 50%
—
—
0.7
0.7
—
—
1.5
2
(10)
tPWL
OutputLOWTimeDeviationfrom50%
—
tORISE
tOFALL
tLOCK
tCCJH
OutputRiseTime
0.15
0.15
—
1.5
1.5
0.5
100
OutputFallTime
PLLLockTime(11,12)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, xFS = H, FB divide-by-n=1,2)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, xFS = H, FB divide-by-n=any)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, xFS = M)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, xFS = L, FREF > 3MHz)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, xFS = L, FREF < 3MHz)
—
tCCJHA
tCCJM
tCCJL
—
—
—
—
—
—
—
—
150
150
200
300
ps
tCCJLA
NOTES:
1. Refer to Input Timing Requirements table for more detail.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified
load.
3. tSKEWPR is the skew between a pair of outputs (xnQ0 and xnQ1) when all sixteen outputs are selected for 0tU.
4. tSKEWB is the skew between outputs (xnQ0 and xnQ1) from A and B banks when they are selected for 0tU.
5. tSK(0) is the skew between outputs when they are selected for 0tU.
6. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (x4Q0 and x4Q1 only with x4F0 = x4F1 = HIGH), and Divided (x3Q1:0 and x4Q1:0 only in Divide-
by-2 or Divide-by-4 mode). Test condition: xnF0:1=MM is set on unused outputs.
7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
8. tφ is measured with REF input rise and fall times (from 0.8V to 2V) of 0.5ns. Measured from 1.5V on REF to 1.5V on xFB.
8. Measured at 2V.
10. Measured at 0.8V.
11. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or xFB until tPD is within specified limits.
12. Lock detector may be unreliable for input frequencies less than approximately 4MHz, or for input signals which contain significant jitter.
8
IDT5V9955
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWDUALPLLCLOCKDRIVERTURBOCLOCKW
AC TEST LOADS AND WAVEFORMS
VDDQ
150Ω
150Ω
Output
Output
20pF
20pF
For LOCK output
For all other outputs
tOFALL
tORISE
2.0V
VTH = 1.5V
0.8V
tPWH
tPWL
LVTTL Output Waveform
≤1ns
≤1ns
3.0V
2.0V
VTH = 1.5V
0.8V
0V
LVTTL Input Test Waveform
9
IDT5V9955
3.3VPROGRAMMABLESKEWDUALPLLCLOCKDRIVERTURBOCLOCKW
INDUSTRIALTEMPERATURERANGE
AC TIMING DIAGRAM
tRPWL
tREF
tRPWH
REF
FB
Q
t(φ)
tODCV
tODCV
tCCJH, HA,
M, L, LA
tSKEWPR,B
tSKEW0, 1
tSKEWPR,B
tSKEW0, 1
OTHER Q
tSKEW2
tSKEW2
INVERTED Q
tSKEW3, 4
tSKEW3, 4
tSKEW3, 4
tSKEW2, 4
REF DIVIDED BY 2
tSKEW1, 3, 4
REF DIVIDED BY 4
NOTES:
PE:
The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge
of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated
with 75Ω to VDDQ/2.
tSKEWPR:
tSKEWB:
tSKEW0:
tDEV:
The skew between a pair of outputs (xnQ0 and xnQ1) when all eight outputs are selected for 0tU.
The skew between outputs (xnQ0 and xnQ1) from A and B banks when they are selected for 0tU.
The skew between outputs when they are selected for 0tU
.
The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tODCV:
tPWH is measured at 2V.
tPWL is measured at 0.8V.
tORISE and tOFALL are measured between 0.8V and 2V.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
10
IDT5V9955
INDUSTRIALTEMPERATURERANGE
3.3VPROGRAMMABLESKEWDUALPLLCLOCKDRIVERTURBOCLOCKW
ORDERINGINFORMATION
X
XXXXX
XX
IDT
Package
Package
Device Type
I
-40°C to +85°C (Industrial)
Fine Pitch Ball Grid Array
FPBGA - green
BF
BFG
5V9955
3.3V Programmable Skew Dual PLL Clock
Driver TurboClock W
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11
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